| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY | |
| /home/m/Builds/CaravelSoomRV-8/openlane/user_project_wrapper,user_project_wrapper,22_11_22_11_32,flow completed,7h11m32s0ms,2h30m13s0ms,43808.374844333746,10.2784,17523.3499377335,23.28,29957.02,180112,0,0,0,0,0,0,-1,-1,0,-1,-1,21241886,2121525,-143.03,-143.03,-1,-0.86,-0.76,-143.03,-86261.94,-1,-0.86,-0.76,15396015869.0,0.0,54.51,66.35,28.8,50.41,-1,169790,231212,2147,60846,0,0,0,193180,4968,444,2780,7907,27790,15212,3076,70689,24130,23804,56,4480,120358,0,124838,10173980.1536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.76,48.16955684007707,20,DELAY 4,10,40,1,180,180,0.25,0.3,sky130_fd_sc_hd,4 |