| commit | 5058a4c5b20386391d96e1a4acbf6a80e8b49da7 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 01:45:05 2023 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 01:45:05 2023 -0800 |
| tree | 19407924ddeb481eefe8aaa1af77dfe3018b9f97 | |
| parent | 0d4f799927e4362c7c8c5fdb5a8ccad7e9ba563d [diff] |
final gds oasis
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.
