| commit | 0d4f799927e4362c7c8c5fdb5a8ccad7e9ba563d | [log] [tgz] |
|---|---|---|
| author | Mathis Salmen <mathis.salmen@matsal.de> | Fri Dec 02 01:29:42 2022 +0100 |
| committer | Mathis Salmen <mathis.salmen@matsal.de> | Fri Dec 02 01:29:42 2022 +0100 |
| tree | 08c3ce7cdfef15442a2357a0bdc6ed632b1dc1c8 | |
| parent | 72ec47a41292988ca8da52d5041346239ae37896 [diff] |
Re-harden, more reduced routing on m2
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.