verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes	     
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/Core.v
-v $(USER_PROJECT_VERILOG)/rtl/InstrDecoder.v
-v $(USER_PROJECT_VERILOG)/rtl/IntALU.v
-v $(USER_PROJECT_VERILOG)/rtl/Load.v
-v $(USER_PROJECT_VERILOG)/rtl/AGU.v
-v $(USER_PROJECT_VERILOG)/rtl/StoreAGU.v
-v $(USER_PROJECT_VERILOG)/rtl/ProgramCounter.v
-v $(USER_PROJECT_VERILOG)/rtl/Rename.v
-v $(USER_PROJECT_VERILOG)/rtl/FPU.v
-v $(USER_PROJECT_VERILOG)/rtl/FDiv.v
-v $(USER_PROJECT_VERILOG)/rtl/FMul.v
-v $(USER_PROJECT_VERILOG)/gl/RF.v
-v $(USER_PROJECT_VERILOG)/rtl/ROB.v
-v $(USER_PROJECT_VERILOG)/rtl/BranchPredictor.v
-v $(USER_PROJECT_VERILOG)/rtl/IndirectBranchPredictor.v
-v $(USER_PROJECT_VERILOG)/rtl/LoadBuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/StoreQueue.v
-v $(USER_PROJECT_VERILOG)/rtl/Multiply.v
-v $(USER_PROJECT_VERILOG)/rtl/Divide.v
-v $(USER_PROJECT_VERILOG)/rtl/ControlRegs.v
-v $(USER_PROJECT_VERILOG)/rtl/PopCnt.v
-v $(USER_PROJECT_VERILOG)/rtl/LZCnt.v
-v $(USER_PROJECT_VERILOG)/rtl/BranchSelector.v
-v $(USER_PROJECT_VERILOG)/rtl/PreDecode.v
-v $(USER_PROJECT_VERILOG)/rtl/RenameTable.v
-v $(USER_PROJECT_VERILOG)/rtl/TagBuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/IssueQueue.v
-v $(USER_PROJECT_VERILOG)/rtl/CacheController.v
-v $(USER_PROJECT_VERILOG)/rtl/MemoryController.v
-v $(USER_PROJECT_VERILOG)/rtl/SRAMWrapperDC.v
-v $(USER_PROJECT_VERILOG)/rtl/SRAMWrapperIC.v
-v $(USER_PROJECT_VERILOG)/rtl/PCFile.v
-v $(USER_PROJECT_VERILOG)/rtl/LoadStoreUnit.v
-v $(USER_PROJECT_VERILOG)/rtl/TageTable.v
-v $(USER_PROJECT_VERILOG)/rtl/TagePredictor.v
-v $(USER_PROJECT_VERILOG)/rtl/BranchTargetBuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/ICacheTable.v
-v $(USER_PROJECT_VERILOG)/rtl/BranchPredictionTable.v
-v $(USER_PROJECT_VERILOG)/rtl/ReturnStack.v
-v $(USER_PROJECT_VERILOG)/rtl/ExternalMemorySim.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_8kbyte_1rw_64x1024_8.v
-v $(USER_PROJECT_VERILOG)/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/addRecFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/compareRecFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/fNToRecFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/HardFloat_primitives.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/HardFloat_specialize.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/recFNToIN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/recFNToFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/mulRecFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/HardFloat_rawFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/isSigNaNRecFN.v
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/iNToRecFN.v   
-v $(USER_PROJECT_VERILOG)/rtl/hardfloat/divSqrtRecFN_small.v