Re-harden, reduced routing on m2
18 files changed
tree: 75f5b9b87a4f829a923c75b7c97fdf33909dc3bb
- .github/
- def/
- docs/
- gds/
- lef/
- lib/
- mag/
- maglef/
- openlane/
- sdc/
- sdf/
- signoff/
- spef/
- spi/
- verilog/
- .gitignore
- LICENSE
- Makefile
- README.md
README.md
SoomRV
Description
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
Features
- RV32IMCZfinxZbaZbbZicbom Instruction Set (other instructions can be emulated via traps)
- 4-wide, Ports: 2 Integer/FP, 1 Load, 1 Store
- Fully Out-of-Order Load/Store
- TAGE-Predictor with 64-entry 8-way associative BTB.
- Tag-based OoO execution, 64 registers
- 64 entry Reorder Buffer
- 4KiB ICache + 4KiB DCache
- 32-bit bus (on GPIOs) for memory expansion
Repo
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.
