| commit | 72ec47a41292988ca8da52d5041346239ae37896 | [log] [tgz] |
|---|---|---|
| author | Mathis Salmen <mathis.salmen@matsal.de> | Wed Nov 30 18:41:55 2022 +0100 |
| committer | Mathis Salmen <mathis.salmen@matsal.de> | Wed Nov 30 18:41:55 2022 +0100 |
| tree | 75f5b9b87a4f829a923c75b7c97fdf33909dc3bb | |
| parent | e9f8aeff8e9cd4a6c3da52f8c41d228ed12d1e78 [diff] |
Re-harden, reduced routing on m2
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.