| /****************************************************************************** |
| ** Logisim-evolution goes FPGA automatic generated Verilog code ** |
| ** https://github.com/logisim-evolution/ ** |
| ** ** |
| ** Component : clock_gen_2 ** |
| ** ** |
| *****************************************************************************/ |
| |
| module clock_gen_2( CLK, |
| CLK1, |
| CLK2, |
| O_S, |
| RST, |
| RST_C ); |
| |
| /******************************************************************************* |
| ** The inputs are defined here ** |
| *******************************************************************************/ |
| input CLK; |
| input RST; |
| input RST_C; |
| |
| /******************************************************************************* |
| ** The outputs are defined here ** |
| *******************************************************************************/ |
| output CLK1; |
| output CLK2; |
| output O_S; |
| |
| /******************************************************************************* |
| ** The wires are defined here ** |
| *******************************************************************************/ |
| wire s_logisimNet0; |
| wire s_logisimNet1; |
| wire s_logisimNet10; |
| wire s_logisimNet2; |
| wire s_logisimNet3; |
| wire s_logisimNet4; |
| wire s_logisimNet5; |
| wire s_logisimNet6; |
| wire s_logisimNet7; |
| wire s_logisimNet8; |
| wire s_logisimNet9; |
| |
| /******************************************************************************* |
| ** The module functionality is described here ** |
| *******************************************************************************/ |
| |
| /******************************************************************************* |
| ** Here all input connections are defined ** |
| *******************************************************************************/ |
| assign s_logisimNet2 = RST_C; |
| assign s_logisimNet6 = CLK; |
| |
| /******************************************************************************* |
| ** Here all output connections are defined ** |
| *******************************************************************************/ |
| assign CLK1 = s_logisimNet0; |
| assign CLK2 = s_logisimNet4; |
| assign O_S = s_logisimNet10; |
| |
| /******************************************************************************* |
| ** Here all normal components are defined ** |
| *******************************************************************************/ |
| AND_GATE #(.BubblesMask(2'b00)) |
| GATES_1 (.input1(s_logisimNet1), |
| .input2(s_logisimNet7), |
| .result(s_logisimNet0)); |
| |
| AND_GATE #(.BubblesMask(2'b00)) |
| GATES_2 (.input1(s_logisimNet1), |
| .input2(s_logisimNet8), |
| .result(s_logisimNet4)); |
| |
| OR_GATE #(.BubblesMask(2'b00)) |
| GATES_3 (.input1(s_logisimNet0), |
| .input2(s_logisimNet4), |
| .result(s_logisimNet9)); |
| |
| D_FLIPFLOP #(.invertClockEnable(0)) |
| MEMORY_4 (.clock(s_logisimNet9), |
| .d(s_logisimNet5), |
| .preset(s_logisimNet2), |
| .q(s_logisimNet10), |
| .qBar(s_logisimNet5), |
| .reset(1'b0), |
| .tick(1'b1)); |
| |
| D_FLIPFLOP #(.invertClockEnable(0)) |
| MEMORY_5 (.clock(s_logisimNet6), |
| .d(s_logisimNet3), |
| .preset(1'b0), |
| .q(s_logisimNet1), |
| .qBar(s_logisimNet3), |
| .reset(s_logisimNet2), |
| .tick(1'b1)); |
| |
| D_FLIPFLOP #(.invertClockEnable(0)) |
| MEMORY_6 (.clock(s_logisimNet3), |
| .d(s_logisimNet7), |
| .preset(1'b0), |
| .q(s_logisimNet8), |
| .qBar(s_logisimNet7), |
| .reset(s_logisimNet2), |
| .tick(1'b1)); |
| |
| |
| endmodule |