commit	d978890c8e74bcdc0100a1a5ae9eb2e817a32faf	[log] [tgz]
author	Matt Venn <matt@mattvenn.net>	Mon Nov 14 18:27:18 2022 +0100
committer	Matt Venn <matt@mattvenn.net>	Mon Nov 14 18:27:18 2022 +0100
tree	7aa73276e543349a7829e37f2d533c1f1cb23fcb
parent	bcf653fcf0cc9192675eabe1be5d5dcb751032b6 [diff]

added new designs, configure now checks top level ports are valid

README.md[diff]
configure.py[diff]
def/user_project_wrapper.def[diff]
gds/aidan_McCoy.gds.gz[diff]
gds/alu_top.gds.gz[diff]
gds/chrisruk_matrix.gds.gz[diff]
gds/jar_illegal_logic.gds.gz[Added - diff]
gds/mbikovitsky_top.gds.gz[Added - diff]
gds/meriac_tt02_play_tune.gds.gz[Added - diff]
gds/moyes0_top_module.gds.gz[Added - diff]
gds/phasenoisepon_seven_segment_seconds.gds.gz[Added - diff]
gds/rc5_top.gds.gz[Added - diff]
gds/rolfmobile99_alu_fsm_top.gds.gz[Added - diff]
gds/s4ga.gds.gz[diff]
gds/thezoq2_yafpga.gds.gz[Added - diff]
gds/tholin_avalonsemi_5401.gds.gz[diff]
gds/top.gds.gz[diff]
gds/tt2_tholin_multiplexed_counter.gds.gz[Added - diff]
gds/tt2_tholin_multiplier.gds.gz[Added - diff]
gds/user_module.gds.gz[Added - diff]
gds/user_module_340805072482992722.gds.gz[diff]
gds/user_module_341516949939814994.gds.gz[Added - diff]
gds/user_module_341535056611770964.gds.gz[diff]
gds/user_module_341541108650607187.gds.gz[Added - diff]
gds/user_module_341614374571475540.gds.gz[Added - diff]
gds/user_module_341620484740219475.gds.gz[Added - diff]
gds/user_module_347592305412145748.gds.gz[diff]
gds/user_module_347787021138264660.gds.gz[diff]
gds/user_module_348242239268323922.gds.gz[Added - diff]
gds/user_module_348255968419643987.gds.gz[Added - diff]
gds/user_module_348260124451668562.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz[diff]
gds/xyz_peppergray_Potato1_top.gds.gz[Added - diff]
gds/yubex_egg_timer.gds.gz[Added - diff]
gds/yupferris_bitslam.gds.gz[Added - diff]
gds/zoechip.gds.gz[Added - diff]
lef/alu_top.lef[diff]
lef/chrisruk_matrix.lef[diff]
lef/cpu_top.lef[Deleted - diff]
lef/jar_illegal_logic.lef[Copied from lef/asic_multiplier.lef - diff]
lef/mbikovitsky_top.lef[Copied from lef/asic_multiplier.lef - diff]
lef/meriac_tt02_play_tune.lef[Copied from lef/asic_multiplier.lef - diff]
lef/moyes0_top_module.lef[Copied from lef/top_tto.lef - diff]
lef/phasenoisepon_seven_segment_seconds.lef[Copied from lef/asic_multiplier.lef - diff]
lef/rc5_top.lef[Copied from lef/asic_multiplier.lef - diff]
lef/rolfmobile99_alu_fsm_top.lef[Copied from lef/asic_multiplier.lef - diff]
lef/s4ga.lef[diff]
lef/thezoq2_yafpga.lef[Copied from lef/asic_multiplier.lef - diff]
lef/top.lef[diff]
lef/tt2_tholin_multiplexed_counter.lef[Copied from lef/asic_multiplier.lef - diff]
lef/tt2_tholin_multiplier.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module.lef[Renamed from lef/asic_multiplier.lef - diff]
lef/user_module_340805072482992722.lef[diff]
lef/user_module_341516949939814994.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module_341535056611770964.lef[diff]
lef/user_module_341541108650607187.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module_341614374571475540.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module_341620484740219475.lef[Copied from lef/top_tto.lef - diff]
lef/user_module_347592305412145748.lef[diff]
lef/user_module_348242239268323922.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module_348255968419643987.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_module_348260124451668562.lef[Copied from lef/asic_multiplier.lef - diff]
lef/user_project_wrapper.lef[diff]
lef/xyz_peppergray_Potato1_top.lef[Renamed from lef/top_tto.lef - diff]
lef/yubex_egg_timer.lef[Copied from lef/asic_multiplier.lef - diff]
lef/yupferris_bitslam.lef[Copied from lef/top_tto.lef - diff]
lef/zoechip.lef[Copied from lef/asic_multiplier.lef - diff]
mag/user_project_wrapper.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/user_project_wrapper/extra_lef_gds.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
openlane/user_project_wrapper/macro_power.tcl[diff]
pre_build.sh[Renamed from integrate_new_projects.sh - diff]
project_urls.py[diff]
spef/user_project_wrapper.spef[diff]
spi/lvs/user_project_wrapper.spice[diff]
tinytapeout.png[diff]
tt_docs[diff]
update_repo.sh[Deleted - diff]
verilog/gl/alu_top.v[diff]
verilog/gl/chrisruk_matrix.v[diff]
verilog/gl/jar_illegal_logic.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/mbikovitsky_top.v[Copied from verilog/gl/asic_multiplier.v - diff]
verilog/gl/meriac_tt02_play_tune.v[Copied from verilog/gl/asic_multiplier.v - diff]
verilog/gl/moyes0_top_module.v[Added - diff]
verilog/gl/phasenoisepon_seven_segment_seconds.v[Copied from verilog/gl/asic_multiplier.v - diff]
verilog/gl/rc5_top.v[Renamed from verilog/gl/asic_multiplier.v - diff]
verilog/gl/rolfmobile99_alu_fsm_top.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/s4ga.v[diff]
verilog/gl/scan_controller.v[Deleted - diff]
verilog/gl/scan_wrapper_019235602376235615.v[Deleted - diff]
verilog/gl/scan_wrapper_1f985e14df1ed789231bb6e0189d6e39.v[Deleted - diff]
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verilog/gl/scan_wrapper_bc4d7220e4fdbf20a574d56ea112a8e1.v[Deleted - diff]
verilog/gl/scan_wrapper_coralmw_manual_verilog.v[Deleted - diff]
verilog/gl/scan_wrapper_hamming74.v[Deleted - diff]
verilog/gl/thezoq2_yafpga.v[Added - diff]
verilog/gl/top.v[diff]
verilog/gl/top_tto.v[Deleted - diff]
verilog/gl/tt2_tholin_multiplexed_counter.v[Copied from verilog/gl/asic_multiplier.v - diff]
verilog/gl/tt2_tholin_multiplier.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_340805072482992722.v[diff]
verilog/gl/user_module_341516949939814994.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_341535056611770964.v[diff]
verilog/gl/user_module_341541108650607187.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_341614374571475540.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_341620484740219475.v[Added - diff]
verilog/gl/user_module_347592305412145748.v[diff]
verilog/gl/user_module_348242239268323922.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_348255968419643987.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_module_348260124451668562.v[Copied from verilog/gl/cpu_top.v - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/gl/xyz_peppergray_Potato1_top.v[Added - diff]
verilog/gl/yubex_egg_timer.v[Copied from verilog/gl/asic_multiplier.v - diff]
verilog/gl/yupferris_bitslam.v[Added - diff]
verilog/gl/zoechip.v[Renamed from verilog/gl/cpu_top.v - diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/0_simon.v[Deleted - diff]
verilog/rtl/10_sram_top.v[Deleted - diff]
verilog/rtl/14_tiny_fft.v[Deleted - diff]
verilog/rtl/19_top.v[Deleted - diff]
verilog/rtl/1_matrix.v[Added - diff]
verilog/rtl/1_tomkeddie_top_tto.v[Deleted - diff]
verilog/rtl/1_top_tto.v[Deleted - diff]
verilog/rtl/21_asic_multiplier.v[Deleted - diff]
verilog/rtl/21_asic_multiplier_wrapper.v[Renamed from verilog/rtl/22_asic_multiplier_wrapper.v - diff]
verilog/rtl/21_logisimTopLevelShell.v[Deleted - diff]
verilog/rtl/22_asic_multiplier.v[Deleted - diff]
verilog/rtl/23_logisimTopLevelShell.v[Deleted - diff]
verilog/rtl/23_tomkeddie_top_tto_a.v[Renamed from verilog/rtl/24_tomkeddie_top_tto_a.v - diff]
verilog/rtl/24_ledmatrix.v[Renamed from verilog/rtl/25_ledmatrix.v - diff]
verilog/rtl/27_yubex_egg_timer.v[Added - diff]
verilog/rtl/28_potato1.v[Added - diff]
verilog/rtl/29_yubex_egg_timer.v[Added - diff]
verilog/rtl/29_zoechip.v[Added - diff]
verilog/rtl/2_matrix.v[Deleted - diff]
verilog/rtl/2_sequencer.v[Renamed from verilog/rtl/3_sequencer.v - diff]
verilog/rtl/2_top_tto.v[Deleted - diff]
verilog/rtl/30_potato1.v[Added - diff]
verilog/rtl/31_mbikovitsky_top.v[Added - diff]
verilog/rtl/31_zoechip.v[Added - diff]
verilog/rtl/33_mbikovitsky_top.v[Added - diff]
verilog/rtl/33_top.v[Added - diff]
verilog/rtl/34_illegal_logic.v[Added - diff]
verilog/rtl/35_top.v[Added - diff]
verilog/rtl/36_illegal_logic.v[Added - diff]
verilog/rtl/36_wrapper.v[Added - diff]
verilog/rtl/37_core.v[Added - diff]
verilog/rtl/38_wrapper.v[Added - diff]
verilog/rtl/38_yupferris_bitslam.v[Added - diff]
verilog/rtl/39_core.v[Added - diff]
verilog/rtl/3_matrix.v[diff]
verilog/rtl/3_top.v[Renamed from verilog/rtl/4_top.v - diff]
verilog/rtl/40_top.v[Added - diff]
verilog/rtl/40_user_module.v[Added - diff]
verilog/rtl/40_yupferris_bitslam.v[Added - diff]
verilog/rtl/41_rc5_top.v[Added - diff]
verilog/rtl/42_rc5_top.v[Added - diff]
verilog/rtl/43_player.v[Added - diff]
verilog/rtl/44_counter.v[Added - diff]
verilog/rtl/44_player.v[Added - diff]
verilog/rtl/45_counter.v[Added - diff]
verilog/rtl/47_logisimTopLevelShell.v[Added - diff]
verilog/rtl/48_logisimTopLevelShell.v[Added - diff]
verilog/rtl/4_s4ga.v[Renamed from verilog/rtl/5_s4ga.v - diff]
verilog/rtl/5_alu_top.v[Renamed from verilog/rtl/6_alu_top.v - diff]
verilog/rtl/5_cpu_top.v[Deleted - diff]
verilog/rtl/6_cpu_top.v[Deleted - diff]
verilog/rtl/6_s4ga.v[diff]
verilog/rtl/7_mccoy.v[Deleted - diff]
verilog/rtl/8_binary_clock.v[Deleted - diff]
verilog/rtl/circuit/CPU.v[Added - diff]
verilog/rtl/circuit/clock_gen_2.v[Added - diff]
verilog/rtl/circuit/dest_reg_sel_new.v[Added - diff]
verilog/rtl/circuit/eq_0.v[Added - diff]
verilog/rtl/circuit/inst_dec.v[Added - diff]
verilog/rtl/circuit/int_memory.v[Added - diff]
verilog/rtl/circuit/main.v[Added - diff]
verilog/rtl/circuit/output_logic.v[Added - diff]
verilog/rtl/gates/AND_GATE.v[Added - diff]
verilog/rtl/gates/AND_GATE_BUS.v[Added - diff]
verilog/rtl/gates/NAND_GATE.v[Added - diff]
verilog/rtl/gates/NOR_GATE.v[Added - diff]
verilog/rtl/gates/OR_GATE.v[Added - diff]
verilog/rtl/gates/OR_GATE_BUS.v[Added - diff]
verilog/rtl/gates/OR_GATE_BUS_3_INPUTS.v[Added - diff]
verilog/rtl/gates/OR_GATE_BUS_4_INPUTS.v[Added - diff]
verilog/rtl/gates/XOR_GATE_ONEHOT.v[Added - diff]
verilog/rtl/memory/D_FLIPFLOP.v[Added - diff]
verilog/rtl/memory/REGISTER_FLIP_FLOP.v[Added - diff]
verilog/rtl/plexers/Demultiplexer_8.v[Added - diff]
verilog/rtl/toplevel/logisimTopLevelShell.v[Renamed from verilog/rtl/13_logisimTopLevelShell.v - diff]
verilog/rtl/user_module_341516949939814994.v[Added - diff]
verilog/rtl/user_module_341541108650607187.v[Added - diff]
verilog/rtl/user_module_341614374571475540.v[Added - diff]
verilog/rtl/user_module_341620484740219475.v[Added - diff]
verilog/rtl/user_module_347592305412145748.v[diff]
verilog/rtl/user_module_348242239268323922.v[Added - diff]
verilog/rtl/user_module_348255968419643987.v[Added - diff]
verilog/rtl/user_module_348260124451668562.v[Added - diff]
verilog/rtl/user_project_includes.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

362 files changed

tree: 7aa73276e543349a7829e37f2d533c1f1cb23fcb

README.md

TinyTapeout

Visit https://tinytapeout.com for more information on the project and how to get involved.
Read INFO for how the project is built and technical project notes.
Read Verification for how we verify the project.

Datasheet

We are building a datasheet of all the projects. To read it, click the tt_datasheet badge above, then download the PDF artifact.

GDS layout of all projects

tiny tapeout

Project Index

Author	Title	Git Repo
Matt Venn	Test Straight Project	https://github.com/TinyTapeout/tt02-test-straight
Chris	Scrolling Binary Matrix display	https://github.com/chrisruk/matrixchip
Jon Klein	Power supply sequencer	https://github.com/loxodes/tt02-submission-loxodes
Marcelo Pouso / Miguel Correia	Duty Controler	https://github.com/migcorre/tt02-dc
Jan Gray	S4GA: Super Slow Serial SRAM FPGA	https://github.com/grayresearch/tt02-s4ga
Ryan C	CPU	https://github.com/ryancor/tt02-submission-template
Aidan Good	The McCoy 6-bit Microprocessor	https://github.com/AidanGood/tt02-McCoy
Azdle	binary clock	https://github.com/azdle/binary-clock-asic
Justin Pelan	TinySensor	https://github.com/justinP-wrk/tt02-TinySensor
James Ross	8x8 SRAM	https://github.com/jar/tt02_sram
Jens Schleusner	German Traffic Light State Machine	https://github.com/JensIMS/tt02-trafficlight
Seppe Van Dyck	4-spin Ising Chain Simulation	https://github.com/svd321/tt02-Ising
Tholin	Avalon Semiconductors ‘5401’ 4-bit Microprocessor	https://github.com/89Mods/tt2-AvalonSemi-5401
Rice Shelley	small FFT	https://github.com/RiceShelley/tiny-fft
William Moyes	Stream Integrator	https://github.com/moyesw/tt02-moyesw-StreamIntegrator
Tom Schucker	tiny-fir	https://github.com/Tschucker/tt02-submission-tiny-fir
Greg Steiert	Configurable SR	https://github.com/steieio/tt02-submission-universal-sr
Luis Ardila	LUTRAM	https://github.com/leardilap/tt02-LUTRAM
Emil J Tywoniak	chase the beat	https://github.com/ekliptik/tt02-chase-the-beat
maehw	BCD to 7-segment encoder	https://github.com/maehw/tt02-bcd-7segment-encoder
Ben Everard	A LED Flasher	https://github.com/benevpi/tt02-LED-flasher
Fernando Dominguez Pousa	4-bit Multiplier	https://github.com/kuriousd/tt02-4bit-multiplier
Tholin	Avalon Semiconductors ‘TBB1143’ Programmable Sound Generator	https://github.com/89Mods/tt2-avalonsemi-TBB1143
Tom Keddie	Transmit UART	https://github.com/TomKeddie/tinytapeout-2022-2a
Matt M	RGB LED Matrix Driver	https://github.com/mm21/tinytapeout2-led-matrix
argunda	Tiny Phase/Frequency Detector	https://github.com/argunda/tt02-TinyPFD
Andre & Milosch Meriac	Loading Animation	https://github.com/meriac/loading-animation
yubex	tiny egg timer	https://github.com/yubex/tt02-tiny_egg_timer
Pepper Gray (they/them)	Potato-1 (Brainfuck CPU)	https://github.com/peppergrayxyz/Potato-1
zoe nguyen. taylor	heart zoe mom dad	https://github.com/zoent/tt02-zoe-chip
Nanik Adnani	Tiny Synth	https://github.com/nanikgeorge/tt02-submission-template
Michael Bikovitsky	5-bit Galois LFSR	https://github.com/mbikovitsky/tt02-lfsr
Tom Schucker	prbs15	https://github.com/teaandtechtime/tt02-submission-prbs15
Rolf Widenfelt	4-bit badge ALU	https://github.com/rolfmobile99/tt02-submission-template
James Ross	Illegal Logic	https://github.com/jar/tt02_freespeech
Alan Green	Siren	https://github.com/alanvgreen/tt02-siren
Frans Skarman	YaFPGA	https://github.com/TheZoq2/smolfpga
William Moyes	M0	https://github.com/moyesw/TT02-M0
Jake “ferris” Taylor	bitslam	https://github.com/yupferris/bitslam
Thorsten Knoll	8x8 Bit Pattern Player	https://github.com/ThorKn/tinytapeout02_pattern_player
proppy	XLS: bit population count	https://github.com/proppy/tt02-xls-popcount
Jean THOMAS	RC5 decoder	https://github.com/jeanthom/tt02-rc5-receiver
Maria CHiara Molteni	chiDOM	https://github.com/mmolteni-secpat/tinytapeout02_chiDOM
Milosch Meriac	Super Mario Tune on A Piezo Speaker	https://github.com/meriac/tt02-play-tune
Phase Noise	Tiny rot13	https://github.com/phasenoisepon/tt02-phasenoisepon
13arn	4 bit counter on steamdeck	https://github.com/13arn/tt02_counter_steamdeck
Thorsten Knoll	Shiftregister Challenge 40 Bit	https://github.com/ThorKn/tinytapeout02_shiftregister_challenge
Tholin	TinyTapeout2 4-bit multiplier.	https://github.com/89Mods/tt2-4x4-multiply
Tholin	TinyTapeout2 multiplexed segment display timer.	https://github.com/89Mods/tt2-multiplexed-counter