| commit | a2580c026200b4c87b7913a96a1a267f5a511cd0 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 00:38:59 2023 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 00:38:59 2023 -0800 |
| tree | 9b9a84504a8631764bdd0747bbc7a9d107b458c4 | |
| parent | 0fdb1a78abbdc9a04b33d402df6bdf0aeb66ef96 [diff] |
final gds oasis
| :exclamation: Important Note |
|---|
Ahem! Testing? Testing? Everything seems to be in order...
Todo:
Cell A: TW Amplifier + SET + Integrated Amplifier
Cell B: TW Amplifier + SET
[x] Configuration Register
[ ] Digital lines wiring
[ ] TWG top wiring
[x] cell A top wiring
[ ] cell B
[ ] Opamp (400µA) DUTs
[ ] Opamp (200µA, Gain Boosted) DUTs
[ ] High Isolation 2-1 MUX DUTs
[ ] Standalone SET DUTs
[ ]
