blob: d368db6b70a7bc7765e61ec4ebf0fbbade50d3df [file] [log] [blame]
Step 1: Create new cells for new GPIO default vectors.
Creating new layout file /root/project/mag/gpio_defaults_block_1803.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v
Layout file /root/project/mag/gpio_defaults_block_1803.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_1803.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_0403.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v
Creating new layout file /root/project/mag/gpio_defaults_block_0801.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0801.v
Layout file /root/project/mag/gpio_defaults_block_0403.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_0403.v already exists and does not need to be generated.
Creating new layout file /root/project/mag/gpio_defaults_block_000a.mag
Creating new gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Layout file /root/project/mag/gpio_defaults_block_000a.mag already exists and does not need to be generated.
Gate-level verilog file /root/project/verilog/gl/gpio_defaults_block_000a.v already exists and does not need to be generated.
Step 2: Modify top-level layouts to use the specified defaults.
Done.