blob: 58964bb256f7a9152dc23156baca2aa607dbc217 [file] [log] [blame] [view]
roman3017daa1c222022-12-22 20:56:26 -08001# Simulation tests
roman3017fe616262022-12-20 21:01:25 -08002
3## UART
4
5```sh
roman3017daa1c222022-12-22 20:56:26 -08006iverilog test_uart.v ../verilog-uart/rtl/uart.v ../verilog-uart/rtl/uart_rx.v ../verilog-uart/rtl/uart_tx.v -o test_uart.out
roman3017fe616262022-12-20 21:01:25 -08007
8./test_uart.out
9gtkwave test_uart.vcd
10```
11
12## USB
13
14```sh
roman3017daa1c222022-12-22 20:56:26 -080015cd ../usb_cdc/
roman3017fe616262022-12-20 21:01:25 -080016git apply ../0001-fix-make-targets.patch
17
18cd examples/TinyFPGA-BX/OSS_CAD_Suite/
19make PROJ=soc clean sim
20make PROJ=soc wave
21```
22
roman301779356d92022-12-12 20:49:52 -080023# FPGA tests
24
roman3017fe616262022-12-20 21:01:25 -080025Use TinyFPGA_BX to test.
roman301779356d92022-12-12 20:49:52 -080026
27## USB
28
roman3017dfc4f242022-12-13 01:01:36 -080029See echo of slightly modified input.
30
roman301779356d92022-12-12 20:49:52 -080031```sh
32cd ../usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/
33tinyprog -l
roman3017dfc4f242022-12-13 01:01:36 -080034make PROJ=soc clean all
35make PROJ=soc prog
36tinyprog -b
37
roman301779356d92022-12-12 20:49:52 -080038minicom -D /dev/ttyACM0
39```
40
roman3017fe616262022-12-20 21:01:25 -080041## USB2UART
roman3017dfc4f242022-12-13 01:01:36 -080042
roman3017fe616262022-12-20 21:01:25 -080043Attach another USB2UART to the first three pins on TinyFPGA_BX: GND, 1(RX), and 2(TX). One should see characters being passed between.
roman3017dfc4f242022-12-13 01:01:36 -080044
45```sh
46tinyprog -l
47make clean all
48make prog
49tinyprog -b
50
51minicom -D /dev/ttyACM0
52minicom -D /dev/ttyUSB0
53```