commit fdac191a8302e8be06287deb49f8e1bd07c40974
author roman3017 <rbacik@hotmail.com> Sat Dec 24 21:12:23 2022 -0800
committer roman3017 <rbacik@hotmail.com> Sat Dec 24 21:12:23 2022 -0800
tree d571ef478b7e6b7b91ce3e21a3e2ef18d2832ef1
parent 73c57ec32b3150ef5c6807f44ad0a8295eb36667

fix undeclared user_clk

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index efd4938..9199f31 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -148,7 +148,7 @@
     assign io_out[`MPRJ_IO_PADS-1] = usb_pu;
 
     usb2uart usb2uart (
-        .clk48(user_clk),
+        .clk48(user_clock2),
         .rst(wb_rst_i),
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),