fix undeclared user_clk

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index efd4938..9199f31 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -148,7 +148,7 @@
     assign io_out[`MPRJ_IO_PADS-1] = usb_pu;
 
     usb2uart usb2uart (
-        .clk48(user_clk),
+        .clk48(user_clock2),
         .rst(wb_rst_i),
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),