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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-006 / fdac191a8302e8be06287deb49f8e1bd07c40974
commitfdac191a8302e8be06287deb49f8e1bd07c40974[log] [tgz]
authorroman3017 <rbacik@hotmail.com>Sat Dec 24 21:12:23 2022 -0800
committerroman3017 <rbacik@hotmail.com>Sat Dec 24 21:12:23 2022 -0800
treed571ef478b7e6b7b91ce3e21a3e2ef18d2832ef1
parent73c57ec32b3150ef5c6807f44ad0a8295eb36667 [diff]
fix undeclared user_clk
1 file changed
tree: d571ef478b7e6b7b91ce3e21a3e2ef18d2832ef1
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  14. LICENSE
  15. Makefile
  16. README.md
README.md

MPW shuttle

USB2UART

Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.

See verilog/rtl/fpga folder for FPGA tests.

mkdir -p dependencies
export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
export PDK_ROOT=$(pwd)/dependencies/pdks
export PDK=sky130A
make setup

make user_proj_example
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds

make user_project_wrapper
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds

make verify
make SIM=GL verify
#make extract-parasitics
make create-spef-mapping
#make caravel-sta
rm -rf ~/mpw_precheck/
make precheck
make run-precheck
#make compress

References