fix io_oeb polarity
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 9f05696..68779a7 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -20,8 +20,8 @@
"dir::../../verilog/rtl/verilog-uart/rtl/uart.v"
],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "wb_clk_i,user_clock2",
- "CLOCK_NET": "counter.clk,uart2ttl.clk48",
+ "CLOCK_PORT": "user_clock2 wb_clk_i",
+ "CLOCK_NET": "counter.clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 900 600",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..cb28226 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -2,7 +2,7 @@
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2",
+ "CLOCK_PORT": "user_clock2 wb_clk_i",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
@@ -78,8 +78,6 @@
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
"DIODE_INSERTION_STRATEGY": 0,
- "FP_PDN_CHECK_NODES": 0,
- "MAGIC_WRITE_FULL_LEF": 0,
- "FP_PDN_ENABLE_RAILS": 0
+ "MAGIC_WRITE_FULL_LEF": 0
}
}
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index 74f5459..fe9bcbc 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -85,10 +85,10 @@
`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL
// User GPIO 33 to 37
-`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
-`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_OUTPUT
`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
-`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL
`endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 9199f31..065fed0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -129,23 +129,23 @@
wire usb_pu;
wire usb_tx_en;
- // io_out[33] input uart_rx
+ // io_out[33] output uart_tx
assign io_oeb[`MPRJ_IO_PADS-5] = 1'b0;
- assign uart_rx = io_out[`MPRJ_IO_PADS-5];
- // io_out[34] output uart_tx
+ assign io_out[`MPRJ_IO_PADS-5] = uart_tx;
+ // io_out[34] input uart_rx
assign io_oeb[`MPRJ_IO_PADS-4] = 1'b1;
- assign io_out[`MPRJ_IO_PADS-4] = uart_tx;
- // io_out[35] inout usb_p
- assign io_oeb[`MPRJ_IO_PADS-3] = usb_tx_en;
- assign io_out[`MPRJ_IO_PADS-3] = /* usb_tx_en ? */ usb_p;
- assign usb_p = io_out[`MPRJ_IO_PADS-3];
+ assign uart_rx = io_out[`MPRJ_IO_PADS-4];
+ // io_out[35] output usb_pu
+ assign io_oeb[`MPRJ_IO_PADS-3] = 1'b0;
+ assign io_out[`MPRJ_IO_PADS-3] = usb_pu;
// io_out[36] inout usb_n
- assign io_oeb[`MPRJ_IO_PADS-2] = usb_tx_en;
+ assign io_oeb[`MPRJ_IO_PADS-2] = ~usb_tx_en;
assign io_out[`MPRJ_IO_PADS-2] = /* usb_tx_en ? */ usb_n;
assign usb_n = io_out[`MPRJ_IO_PADS-2];
- // io_out[37] output usb_pu
- assign io_oeb[`MPRJ_IO_PADS-1] = 1'b1;
- assign io_out[`MPRJ_IO_PADS-1] = usb_pu;
+ // io_out[37] inout usb_p
+ assign io_oeb[`MPRJ_IO_PADS-1] = ~usb_tx_en;
+ assign io_out[`MPRJ_IO_PADS-1] = /* usb_tx_en ? */ usb_p;
+ assign usb_p = io_out[`MPRJ_IO_PADS-1];
usb2uart usb2uart (
.clk48(user_clock2),
