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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-006 / ef381df7a13b09115516b76d61af2f3ed9b05649
commitef381df7a13b09115516b76d61af2f3ed9b05649[log] [tgz]
authorroman3017 <rbacik@hotmail.com>Thu Dec 29 12:52:14 2022 -0800
committerroman3017 <rbacik@hotmail.com>Thu Dec 29 12:52:14 2022 -0800
tree96e44e52cb0b7e8f71f621cfe14827c9f94da3c0
parentd466d36595b58dce2df967ae6ca552f9fddb3341 [diff]
fix io_oeb polarity
4 files changed
tree: 96e44e52cb0b7e8f71f621cfe14827c9f94da3c0
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  14. LICENSE
  15. Makefile
  16. README.md
README.md

MPW shuttle

USB2UART

Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.

See verilog/rtl/fpga folder for FPGA tests.

mkdir -p dependencies
export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
export PDK_ROOT=$(pwd)/dependencies/pdks
export PDK=sky130A
make setup

make user_proj_example
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds

make user_project_wrapper
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds

make verify
make SIM=GL verify
#make extract-parasitics
make create-spef-mapping
#make caravel-sta
rm -rf ~/mpw_precheck/
make precheck
make run-precheck
#make compress

References

  • MPW-8 Shuttle projects (project 1758)
  • USB IP taken from ulixxe
  • UART IP taken from alexforencich
  • Harness Harness specification
  • OpenLane OpenLane documentation
  • Board Test board
  • PLL PLL registers calculator
  • QSG Quick start guide
  • README A sample project documentation