update submodules
diff --git a/.gitmodules b/.gitmodules
index 70540c8..0685ae2 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
-[submodule "verilog/rtl/tinyfpga_bx_usbserial"]
- path = verilog/rtl/tinyfpga_bx_usbserial
- url = https://github.com/davidthings/tinyfpga_bx_usbserial.git
+[submodule "verilog/rtl/usb_cdc"]
+ path = verilog/rtl/usb_cdc
+ url = https://github.com/ulixxe/usb_cdc
+[submodule "verilog/rtl/verilog-uart"]
+ path = verilog/rtl/verilog-uart
+ url = https://github.com/alexforencich/verilog-uart
diff --git a/verilog/rtl/tinyfpga_bx_usbserial b/verilog/rtl/tinyfpga_bx_usbserial
deleted file mode 160000
index 00608c2..0000000
--- a/verilog/rtl/tinyfpga_bx_usbserial
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 00608c23488a3e79325df997cc50148b94961861
diff --git a/verilog/rtl/usb_cdc b/verilog/rtl/usb_cdc
new file mode 160000
index 0000000..c20f51b
--- /dev/null
+++ b/verilog/rtl/usb_cdc
@@ -0,0 +1 @@
+Subproject commit c20f51bb6256a9ee6b356e73a1bfcf03d6aafcde
diff --git a/verilog/rtl/verilog-uart b/verilog/rtl/verilog-uart
new file mode 160000
index 0000000..b973f08
--- /dev/null
+++ b/verilog/rtl/verilog-uart
@@ -0,0 +1 @@
+Subproject commit b973f08697b03a17ce56b90783622c7b7a28fa2a
