| commit | d466d36595b58dce2df967ae6ca552f9fddb3341 | [log] [tgz] |
|---|---|---|
| author | roman3017 <rbacik@hotmail.com> | Mon Dec 26 13:05:51 2022 +0000 |
| committer | roman3017 <rbacik@hotmail.com> | Mon Dec 26 13:05:51 2022 +0000 |
| tree | d89d806f0d32fd89e36abac3db176375bcd9c5c8 | |
| parent | f8f0c7c36edd59d4b1ac5ef0da4f36153997a580 [diff] |
action: update build
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress