add usb submodule

.gitmodules

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..70540c8
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "verilog/rtl/tinyfpga_bx_usbserial"]
+	path = verilog/rtl/tinyfpga_bx_usbserial
+	url = https://github.com/davidthings/tinyfpga_bx_usbserial.git

verilog/rtl/tinyfpga_bx_usbserial

diff --git a/verilog/rtl/tinyfpga_bx_usbserial b/verilog/rtl/tinyfpga_bx_usbserial
new file mode 160000
index 0000000..00608c2
--- /dev/null
+++ b/verilog/rtl/tinyfpga_bx_usbserial
@@ -0,0 +1 @@
+Subproject commit 00608c23488a3e79325df997cc50148b94961861