cd verilog/rtl/ iverilog test_uart.v verilog-uart/rtl/uart.v verilog-uart/rtl/uart_rx.v verilog-uart/rtl/uart_tx.v -o test_uart.out ./test_uart.out gtkwave test_uart.vcd
cd verilog/rtl/usb_cdc/ git apply ../0001-fix-make-targets.patch cd examples/TinyFPGA-BX/OSS_CAD_Suite/ make PROJ=soc clean sim make PROJ=soc wave
Use TinyFPGA_BX to test.
See echo of slightly modified input.
cd ../usb_cdc/examples/TinyFPGA-BX/OSS_CAD_Suite/ tinyprog -l make PROJ=soc clean all make PROJ=soc prog tinyprog -b minicom -D /dev/ttyACM0
Attach another USB2UART to the first three pins on TinyFPGA_BX: GND, 1(RX), and 2(TX). One should see characters being passed between.
tinyprog -l make clean all make prog tinyprog -b minicom -D /dev/ttyACM0 minicom -D /dev/ttyUSB0