Google Git
Sign in
foss-eda-tools/third_party/shuttle/sky130/mpw-008/slot-006/889dfb08c510e7b3454c4a196a6f7467142ebd0f/./verilog/rtl
tree: 90c46a79c4686c90bb1c319ca47c42070bc9f702
  1. fpga/
  2. usb_cdc
  3. verilog-uart
  4. 0001-fix-make-targets.patch
  5. defines.v
  6. test_uart.v
  7. uprj_netlists.v
  8. user_defines.v
  9. user_proj_example.v
  10. user_project_wrapper.v
Powered by Gitiles| Privacy| Termstxt json