optimize fpga timing
diff --git a/verilog/rtl/fpga/Makefile b/verilog/rtl/fpga/Makefile
index d71710d..b29bd15 100644
--- a/verilog/rtl/fpga/Makefile
+++ b/verilog/rtl/fpga/Makefile
@@ -53,17 +53,17 @@
.SUFFIXES: .asc .bin .json .v .vcd .rpt
.asc.rpt:
- icetime -d $(FPGA_TYPE)$(FPGA_SIZE) -P $(FPGA_PACK) -mtr $@ $^
+ icetime -d $(FPGA_TYPE)$(FPGA_SIZE) -mtr $@ $<
.v.vcd:
iverilog $^ -o $(@:.vcd=.out)
./$(@:.vcd=.out)
.v.json:
- yosys -p "$(foreach file,$^,read_verilog $(file);)" -p "synth_ice40 -json $@" $^
+ yosys -q -p 'synth_ice40 -top $(NAME) -json $@' $^
.json.asc:
- nextpnr-ice40 --$(FPGA_TYPE)$(FPGA_SIZE) --freq $(CLK_MHZ) --package $(FPGA_PACK) --pcf-allow-unconstrained --pcf $(PIN_DEF) --json $< --asc $@
+ nextpnr-ice40 --$(FPGA_TYPE)$(FPGA_SIZE) --freq $(CLK_MHZ) --opt-timing --package $(FPGA_PACK) --pcf $(PIN_DEF) --json $< --asc $@
.asc.bin:
icepack $< $@
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v
index f0aac5e..e9d61c0 100644
--- a/verilog/rtl/fpga/fpga_top.v
+++ b/verilog/rtl/fpga/fpga_top.v
@@ -68,16 +68,11 @@
usb_cdc #(
.VENDORID(16'h1D50),
- .PRODUCTID(16'h6130),
- .IN_BULK_MAXPACKETSIZE('d8),
- .OUT_BULK_MAXPACKETSIZE('d8),
- .BIT_SAMPLES(BIT_SAMPLES),
- .USE_APP_CLK(0),
- .APP_CLK_RATIO(c_CLKS_PER_BIT)
+ .PRODUCTID(16'h6130)
) u_usb_cdc (
.clk_i(clk_pll), // 48MHz
.rstn_i(rstn),
- .app_clk_i(),
+ .app_clk_i(1'b0),
.out_data_o(out_data),
.out_valid_o(out_valid),
.out_ready_i(out_ready),
