fix CLOCK_PORT and CLOCK_NET syntax error
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 68779a7..69a6e94 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -20,7 +20,7 @@
"dir::../../verilog/rtl/verilog-uart/rtl/uart.v"
],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2 wb_clk_i",
+ "CLOCK_PORT": "user_clock2",
"CLOCK_NET": "counter.clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 900 600",
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index cb28226..152bdf0 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -2,7 +2,7 @@
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
"CLOCK_PERIOD": 10,
- "CLOCK_PORT": "user_clock2 wb_clk_i",
+ "CLOCK_PORT": "user_clock2",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
