commit | 852e8efa322183e4c5ab6f1bf922c185bbd5c265 | [log] [tgz] |
---|---|---|
author | roman3017 <rbacik@hotmail.com> | Thu Dec 29 13:18:18 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Thu Dec 29 13:18:18 2022 -0800 |
tree | 1ae009eef6126b866fccbadd7df0e8847879a0b1 | |
parent | ef381df7a13b09115516b76d61af2f3ed9b05649 [diff] |
fix CLOCK_PORT and CLOCK_NET syntax error
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify make SIM=GL verify #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress