commit | 5c0668248ac2f72c663f6341feaf49f26150c088 | [log] [tgz] |
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author | roman3017 <rbacik@hotmail.com> | Thu Dec 29 22:07:44 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Fri Dec 30 00:05:38 2022 -0800 |
tree | 5a5ac606dd4c0047d2dbf642682e89abafc8100c | |
parent | d1d9a609a6efd18bb33ddbd366e23e1ea3471d39 [diff] |
remove counter
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify-usb2uart-rtl make verify-usb2uart-gl #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress