fix path of uart.v for rtl tests
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 585eae2..92ae852 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -14,4 +14,4 @@
-v $(USER_PROJECT_VERILOG)/rtl/usb_cdc/examples/common/hdl/fifo_if.v
-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_rx.v
-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart_tx.v
--v $(USER_PROJECT_VERILOG)/rtl/verilog/rtl/verilog-uart/rtl/uart.v
+-v $(USER_PROJECT_VERILOG)/rtl/verilog-uart/rtl/uart.v
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 703f4f1..e2dc64e 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -38,5 +38,5 @@
`include "usb_cdc/examples/common/hdl/fifo_if.v",
`include "verilog-uart/rtl/uart_rx.v",
`include "verilog-uart/rtl/uart_tx.v",
- `include "verilog/rtl/verilog-uart/rtl/uart.v"
+ `include "verilog-uart/rtl/uart.v"
`endif
\ No newline at end of file
