remove counter
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index 94e49e7..05068db 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -93,16 +93,8 @@
- name: Harden using Openlane
run: |
- make clean-user_proj_example user_proj_example \
- || make clean-user_proj_example user_proj_example \
- || make clean-user_proj_example user_proj_example \
- || make clean-user_proj_example user_proj_example \
- || make clean-user_proj_example user_proj_example
- make clean-user_project_wrapper user_project_wrapper \
- || clean-user_project_wrapper make user_project_wrapper \
- || clean-user_project_wrapper make user_project_wrapper \
- || clean-user_project_wrapper make user_project_wrapper \
- || clean-user_project_wrapper make user_project_wrapper
+ make clean-user_proj_example user_proj_example
+ make clean-user_project_wrapper user_project_wrapper
- name: run precheck
run: |
@@ -131,11 +123,12 @@
- name: Run DV RTL tests
run: |
- make verify-all-rtl
+ make verify-usb2uart-rtl
- name: Run DV GL tests
+ if: failure()
run: |
- make verify-all-gl
+ make verify-usb2uart-gl
- name: Push gds
if: github.event_name == 'workflow_dispatch'
@@ -226,11 +219,12 @@
- name: Run DV RTL tests
run: |
- make verify-all-rtl
+ make verify-usb2uart-rtl
- name: Run DV GL tests
+ if: failure()
run: |
- make verify-all-gl
+ make verify-usb2uart-gl
tag_repo:
if: github.event_name == 'workflow_dispatch'
diff --git a/README.md b/README.md
index c70cd05..f52a1d9 100644
--- a/README.md
+++ b/README.md
@@ -19,11 +19,13 @@
make user_project_wrapper
klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds
-make verify
-make SIM=GL verify
+make verify-usb2uart-rtl
+make verify-usb2uart-gl
+
#make extract-parasitics
make create-spef-mapping
#make caravel-sta
+
rm -rf ~/mpw_precheck/
make precheck
make run-precheck
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index 69a6e94..c177d05 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -21,7 +21,7 @@
],
"CLOCK_PERIOD": 10,
"CLOCK_PORT": "user_clock2",
- "CLOCK_NET": "counter.clk",
+ "CLOCK_NET": "usb2uart.clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 900 600",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index cc97ad8..ac4cece 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus usb2uart
+PATTERNS = usb2uart
all: ${PATTERNS}
diff --git a/verilog/dv/usb2uart/usb2uart.c b/verilog/dv/usb2uart/usb2uart.c
index 059752a..8cfb5d9 100644
--- a/verilog/dv/usb2uart/usb2uart.c
+++ b/verilog/dv/usb2uart/usb2uart.c
@@ -62,24 +62,22 @@
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
- //User COUNTER
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
- //reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;//mgmt_uart_tx
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// Set UART clock to 64 kbaud (enable before I/O configuration)
// reg_uart_clkdiv = 625;
@@ -89,24 +87,6 @@
//reg_mprj_xfer = 1;
//while (reg_mprj_xfer == 1);
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
- // Configure LA probes [63:32] as outputs from the cpu
- //reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- //reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- //reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- //reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
-
- // Flag start of the test
- //reg_mprj_datal = 0xAB400000;
-
- // Set Counter value to zero through LA probes [63:32]
- //reg_la1_data = 0x00000000;
-
- // Configure LA probes from [63:32] as inputs to disable counter write
- //reg_la1_oenb = reg_la1_iena = 0x00000000;
-
- //reg_mprj_datal = 0xAB410000;
-
//print("Test\n\n");
//print("\n");
//print("\n");
diff --git a/verilog/rtl/usb2uart.v b/verilog/rtl/usb2uart.v
index 6acd066..c9bb686 100644
--- a/verilog/rtl/usb2uart.v
+++ b/verilog/rtl/usb2uart.v
@@ -11,6 +11,8 @@
output usb_tx_en // USB tx enabled
);
+ wire clk;
+
wire in_ready;
wire [7:0] in_data;
wire in_valid;
@@ -18,10 +20,12 @@
wire [7:0] out_data;
wire out_valid;
+ assign clk = clk48;
+
uart # (
.DATA_WIDTH(8)
) u_uart (
- .clk(clk48),
+ .clk(clk),
.rst(rst),
//data input to uart tx
@@ -60,7 +64,7 @@
.VENDORID(16'h1D50),
.PRODUCTID(16'h6130)
) u_usb_cdc (
- .clk_i(clk48),
+ .clk_i(clk),
.rstn_i(~rst),
.app_clk_i(1'b0),
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 671871d..41524a4 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -71,57 +71,9 @@
// IRQ
output [2:0] irq
);
+
wire clk;
wire rst;
-
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out[`MPRJ_IO_PADS-6:0] = {1'b0, count};
- assign io_oeb[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){rst}};
-
- // IRQ
- assign irq = 3'b000; // Unused
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
-
- counter #(
- .BITS(BITS)
- ) counter (
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
-
wire uart_rx;
wire uart_tx;
wire usb_p;
@@ -129,27 +81,48 @@
wire usb_pu;
wire usb_tx_en;
+ // WB
+ assign wbs_dat_o = 32'h00000000;
+ assign wbs_ack_o = 1'b0;
+
+ // LA
+ assign la_data_out = 128'h00000000000000000000000000000000;
+
+ // IO
+ assign io_out[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){1'b0}};
+ assign io_oeb[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){1'b1}};
+
+ // IRQ
+ assign irq = 3'b000;
+
+ assign clk = user_clock2;
+ assign rst = wb_rst_i;
+
// io_out[33] output uart_tx
assign io_oeb[`MPRJ_IO_PADS-5] = 1'b0;
assign io_out[`MPRJ_IO_PADS-5] = uart_tx;
+
// io_out[34] input uart_rx
assign io_oeb[`MPRJ_IO_PADS-4] = 1'b1;
assign uart_rx = io_in[`MPRJ_IO_PADS-4];
+
// io_out[35] output usb_pu
assign io_oeb[`MPRJ_IO_PADS-3] = 1'b0;
assign io_out[`MPRJ_IO_PADS-3] = usb_pu;
+
// io_out[36] inout usb_n
assign io_oeb[`MPRJ_IO_PADS-2] = ~usb_tx_en;
assign io_out[`MPRJ_IO_PADS-2] = /* usb_tx_en ? */ usb_n;
assign usb_n = io_in[`MPRJ_IO_PADS-2];
+
// io_out[37] inout usb_p
assign io_oeb[`MPRJ_IO_PADS-1] = ~usb_tx_en;
assign io_out[`MPRJ_IO_PADS-1] = /* usb_tx_en ? */ usb_p;
assign usb_p = io_in[`MPRJ_IO_PADS-1];
usb2uart usb2uart (
- .clk48(user_clock2),
- .rst(wb_rst_i),
+ .clk48(clk),
+ .rst(rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.usb_p(usb_p),
@@ -160,45 +133,4 @@
endmodule
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
-endmodule
`default_nettype wire
