add usb2uart to user_proj_example
diff --git a/README.md b/README.md index f251249..4dc1b9b 100644 --- a/README.md +++ b/README.md
@@ -1,5 +1,5 @@ # MPW shuttle (WIP) -## USB2TTL +## USB2UART ```sh mkdir -p dependencies @@ -9,10 +9,10 @@ make setup make user_proj_example -klayout -l dependencies/pdks/gf180mcuC/libs.tech/klayout/tech/gf180mcu.lyp gds/user_proj_example.gds +klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper -klayout -l dependencies/pdks/gf180mcuC/libs.tech/klayout/tech/gf180mcu.lyp gds/user_project_wrapper.gds +klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify #make extract-parasitics
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json index 370d74c..9f05696 100644 --- a/openlane/user_proj_example/config.json +++ b/openlane/user_proj_example/config.json
@@ -1,10 +1,27 @@ { "DESIGN_NAME": "user_proj_example", "DESIGN_IS_CORE": 0, - "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"], + "VERILOG_FILES": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/rtl/user_proj_example.v", + "dir::../../verilog/rtl/usb2uart.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/phy_tx.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/phy_rx.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/sie.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/ctrl_endp.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/in_fifo.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/out_fifo.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/bulk_endp.v", + "dir::../../verilog/rtl/usb_cdc/usb_cdc/usb_cdc.v", + "dir::../../verilog/rtl/usb_cdc/examples/common/hdl/prescaler.v", + "dir::../../verilog/rtl/usb_cdc/examples/common/hdl/fifo_if.v", + "dir::../../verilog/rtl/verilog-uart/rtl/uart_rx.v", + "dir::../../verilog/rtl/verilog-uart/rtl/uart_tx.v", + "dir::../../verilog/rtl/verilog-uart/rtl/uart.v" + ], "CLOCK_PERIOD": 10, - "CLOCK_PORT": "wb_clk_i", - "CLOCK_NET": "counter.clk", + "CLOCK_PORT": "wb_clk_i,user_clock2", + "CLOCK_NET": "counter.clk,uart2ttl.clk48", "FP_SIZING": "absolute", "DIE_AREA": "0 0 900 600", "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg index 2fda806..35255bf 100644 --- a/openlane/user_proj_example/pin_order.cfg +++ b/openlane/user_proj_example/pin_order.cfg
@@ -4,6 +4,7 @@ wb_.* wbs_.* la_.* +user_clock2 irq.* #N
diff --git a/verilog/rtl/0001-fix-make-targets.patch b/verilog/rtl/0001-usb_cdc-fix-make-targets.patch similarity index 100% rename from verilog/rtl/0001-fix-make-targets.patch rename to verilog/rtl/0001-usb_cdc-fix-make-targets.patch
diff --git a/verilog/rtl/fpga/Makefile b/verilog/rtl/fpga/Makefile index 7946b02..d3028e5 100644 --- a/verilog/rtl/fpga/Makefile +++ b/verilog/rtl/fpga/Makefile
@@ -6,6 +6,7 @@ NAME = fpga_top DEPS = \ +../usb2uart.v \ ../usb_cdc/usb_cdc/phy_tx.v \ ../usb_cdc/usb_cdc/phy_rx.v \ ../usb_cdc/usb_cdc/sie.v \
diff --git a/verilog/rtl/fpga/README.md b/verilog/rtl/fpga/README.md index 58964bb..e3fbd79 100644 --- a/verilog/rtl/fpga/README.md +++ b/verilog/rtl/fpga/README.md
@@ -13,7 +13,7 @@ ```sh cd ../usb_cdc/ -git apply ../0001-fix-make-targets.patch +git apply ../0001-usb_cdc-fix-make-targets.patch cd examples/TinyFPGA-BX/OSS_CAD_Suite/ make PROJ=soc clean sim
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v index df4e986..72de9c9 100644 --- a/verilog/rtl/fpga/fpga_top.v +++ b/verilog/rtl/fpga/fpga_top.v
@@ -7,11 +7,6 @@ output usb_pu // USB 1.5kOhm Pullup EN ); - localparam BIT_SAMPLES = 4; - localparam c_CLOCK_MHZ = BIT_SAMPLES*12; - localparam c_UART_SPEED = 115200; - localparam c_CLKS_PER_BYTE = (c_CLOCK_MHZ*1000000+c_UART_SPEED*8-1)/(c_UART_SPEED*8); - wire clk_pll; pll pll48( .clock_in(clk), .clock_out(clk_pll) ); @@ -19,73 +14,15 @@ wire rstn = &reset_cnt; always @(posedge clk_pll) reset_cnt <= reset_cnt + !rstn; - wire in_ready; - wire [7:0] in_data; - wire in_valid; - wire out_ready; - wire [7:0] out_data; - wire out_valid; - - uart # ( - .DATA_WIDTH(8) - ) u_uart ( - .clk(clk_pll), + usb2uart usb2uart ( + .clk48(clk_pll), .rst(~rstn), - - //data input to uart tx - .s_axis_tdata(out_data), - .s_axis_tvalid(out_valid), - .s_axis_tready(out_ready), - .txd(uart_tx), - - //data output from uart rx - .m_axis_tdata(in_data), - .m_axis_tvalid(in_valid), - .m_axis_tready(in_ready), - .rxd(uart_rx), - - .prescale(c_CLKS_PER_BYTE) - ); - - wire dp_pu; - wire dp_rx; - wire dn_rx; - wire dp_tx; - wire dn_tx; - wire tx_en; - - assign usb_p = tx_en ? dp_tx : 1'bz; - assign dp_rx = usb_p; - - assign usb_n = tx_en ? dn_tx : 1'bz; - assign dn_rx = usb_n; - - assign usb_pu = dp_pu; - - usb_cdc #( - .VENDORID(16'h1D50), - .PRODUCTID(16'h6130) - ) u_usb_cdc ( - .clk_i(clk_pll), - .rstn_i(rstn), - .app_clk_i(1'b0), - - //data output from usb rx - .out_data_o(out_data), - .out_valid_o(out_valid), - .out_ready_i(out_ready), - - //data input to usb tx - .in_data_i(in_data), - .in_valid_i(in_valid), - .in_ready_o(in_ready), - - .dp_pu_o(dp_pu), - .tx_en_o(tx_en), - .dp_tx_o(dp_tx), - .dn_tx_o(dn_tx), - .dp_rx_i(dp_rx), - .dn_rx_i(dn_rx) + .uart_rx(uart_rx), + .uart_tx(uart_tx), + .usb_p(usb_p), + .usb_n(usb_n), + .usb_pu(usb_pu), + .usb_tx_en() ); endmodule
diff --git a/verilog/rtl/usb2uart.v b/verilog/rtl/usb2uart.v new file mode 100644 index 0000000..6acd066 --- /dev/null +++ b/verilog/rtl/usb2uart.v
@@ -0,0 +1,87 @@ +`default_nettype none + +module usb2uart ( + input clk48, // 48MHz Clock + input rst, // reset + input uart_rx, // uart in + output uart_tx, // uart out + inout usb_p, // USB+ + inout usb_n, // USB- + output usb_pu, // USB 1.5kOhm Pullup EN + output usb_tx_en // USB tx enabled +); + + wire in_ready; + wire [7:0] in_data; + wire in_valid; + wire out_ready; + wire [7:0] out_data; + wire out_valid; + + uart # ( + .DATA_WIDTH(8) + ) u_uart ( + .clk(clk48), + .rst(rst), + + //data input to uart tx + .s_axis_tdata(out_data), + .s_axis_tvalid(out_valid), + .s_axis_tready(out_ready), + .txd(uart_tx), + + //data output from uart rx + .m_axis_tdata(in_data), + .m_axis_tvalid(in_valid), + .m_axis_tready(in_ready), + .rxd(uart_rx), + + //115200 bauds from 48MHz clock + .prescale(((48*1000000)+(115200*8)-1)/(115200*8)) + ); + + wire dp_pu; + wire dp_rx; + wire dn_rx; + wire dp_tx; + wire dn_tx; + wire tx_en; + + assign usb_p = tx_en ? dp_tx : 1'bz; + assign dp_rx = usb_p; + + assign usb_n = tx_en ? dn_tx : 1'bz; + assign dn_rx = usb_n; + + assign usb_pu = dp_pu; + assign usb_tx_en = tx_en; + + usb_cdc #( + .VENDORID(16'h1D50), + .PRODUCTID(16'h6130) + ) u_usb_cdc ( + .clk_i(clk48), + .rstn_i(~rst), + .app_clk_i(1'b0), + + //data output from usb rx + .out_data_o(out_data), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + + //data input to usb tx + .in_data_i(in_data), + .in_valid_i(in_valid), + .in_ready_o(in_ready), + + .dp_pu_o(dp_pu), + .tx_en_o(tx_en), + .dp_tx_o(dp_tx), + .dn_tx_o(dn_tx), + .dp_rx_i(dp_rx), + .dn_rx_i(dn_rx) + ); + +endmodule + +`default_nettype wire \ No newline at end of file
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index 8533e2f..74f5459 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v
@@ -83,10 +83,12 @@ `define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL `define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL -`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_MGMT_STD_INPUT_NOPULL + +// User GPIO 33 to 37 +`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL +`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT `endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 26081e9..efd4938 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -65,6 +65,9 @@ output [`MPRJ_IO_PADS-1:0] io_out, output [`MPRJ_IO_PADS-1:0] io_oeb, + // User clock + input user_clock2, + // IRQ output [2:0] irq ); @@ -90,8 +93,8 @@ assign wdata = wbs_dat_i; // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; + assign io_out[`MPRJ_IO_PADS-6:0] = {1'b0, count}; + assign io_oeb[`MPRJ_IO_PADS-6:0] = {(`MPRJ_IO_PADS-5){rst}}; // IRQ assign irq = 3'b000; // Unused @@ -106,7 +109,7 @@ counter #( .BITS(BITS) - ) counter( + ) counter ( .clk(clk), .reset(rst), .ready(wbs_ack_o), @@ -119,6 +122,42 @@ .count(count) ); + wire uart_rx; + wire uart_tx; + wire usb_p; + wire usb_n; + wire usb_pu; + wire usb_tx_en; + + // io_out[33] input uart_rx + assign io_oeb[`MPRJ_IO_PADS-5] = 1'b0; + assign uart_rx = io_out[`MPRJ_IO_PADS-5]; + // io_out[34] output uart_tx + assign io_oeb[`MPRJ_IO_PADS-4] = 1'b1; + assign io_out[`MPRJ_IO_PADS-4] = uart_tx; + // io_out[35] inout usb_p + assign io_oeb[`MPRJ_IO_PADS-3] = usb_tx_en; + assign io_out[`MPRJ_IO_PADS-3] = /* usb_tx_en ? */ usb_p; + assign usb_p = io_out[`MPRJ_IO_PADS-3]; + // io_out[36] inout usb_n + assign io_oeb[`MPRJ_IO_PADS-2] = usb_tx_en; + assign io_out[`MPRJ_IO_PADS-2] = /* usb_tx_en ? */ usb_n; + assign usb_n = io_out[`MPRJ_IO_PADS-2]; + // io_out[37] output usb_pu + assign io_oeb[`MPRJ_IO_PADS-1] = 1'b1; + assign io_out[`MPRJ_IO_PADS-1] = usb_pu; + + usb2uart usb2uart ( + .clk48(user_clk), + .rst(wb_rst_i), + .uart_rx(uart_rx), + .uart_tx(uart_tx), + .usb_p(usb_p), + .usb_n(usb_n), + .usb_pu(usb_pu), + .usb_tx_en(usb_tx_en) + ); + endmodule module counter #(
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5ee1cee..2bbb1e2 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -114,6 +114,9 @@ .io_out(io_out), .io_oeb(io_oeb), + // User clock + .user_clock2(user_clock2), + // IRQ .irq(user_irq) );