update usb2uart test
- rtl test pass
- gl test fails (todo)
diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index 05068db..7d4ec32 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -126,7 +126,6 @@
make verify-usb2uart-rtl
- name: Run DV GL tests
- if: failure()
run: |
make verify-usb2uart-gl
@@ -222,7 +221,6 @@
make verify-usb2uart-rtl
- name: Run DV GL tests
- if: failure()
run: |
make verify-usb2uart-gl
diff --git a/verilog/dv/usb2uart/usb2uart.c b/verilog/dv/usb2uart/usb2uart.c
index 8cfb5d9..01dd4e5 100644
--- a/verilog/dv/usb2uart/usb2uart.c
+++ b/verilog/dv/usb2uart/usb2uart.c
@@ -23,76 +23,6 @@
void main()
{
- // The upper GPIO pins are configured to be output
- // and accessble to the management SoC.
- // Used to flag the start/end of a test
- // The lower GPIO pins are configured to be output
- // and accessible to the user project. They show
- // the project count value, although this test is
- // designed to read the project count through the
- // logic analyzer probes.
- // I/O 6 is configured for the UART Tx line
-
- // User USB
- reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
- reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
- reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
-
- // User UART
- reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
-
- // MGMT GPIO
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- // reg_uart_clkdiv = 625;
- //reg_uart_enable = 1;
-
- /* Apply configuration */
- //reg_mprj_xfer = 1;
- //while (reg_mprj_xfer == 1);
-
- //print("Test\n\n");
- //print("\n");
- //print("\n");
-
- // Flag end of the test
- //reg_mprj_datal = 0xAB510000;
-
- //TODO: Turn on PLL for clock2
+ //print("test\n");
+ asm("j .");
}
diff --git a/verilog/dv/usb2uart/usb2uart_tb.v b/verilog/dv/usb2uart/usb2uart_tb.v
index 0693bca..44c969f 100644
--- a/verilog/dv/usb2uart/usb2uart_tb.v
+++ b/verilog/dv/usb2uart/usb2uart_tb.v
@@ -44,7 +44,10 @@
/*
wire mgmt_uart_tx;
assign mgmt_uart_tx = mprj_io[6];
+ //assign mprj_io[34] = mprj_io[6];
*/
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
// Signals Assignment
assign mprj_io[34] = user_uart_rx;
@@ -151,20 +154,18 @@
initial begin
$dumpfile("usb2uart.vcd");
$dumpvars(0, usb2uart_tb);
- //$monitor("usb2uart.in_data: 0x%x", uut.mprj.mprj.usb2uart.in_data);
-
+ `ifdef GL
+ $monitor( "io_in[34]: 0x%x", uut.mprj.mprj.io_in[34] );
+ `else
+ $monitor( "usb2uart.in_data: 0x%x", uut.mprj.mprj.usb2uart.in_data );
+ `endif
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (100) begin
+ repeat (50) begin
repeat (1000) @(posedge clock);
end
- $display("%c[1;31m",27);
- `ifdef GL
- $display ("Monitor: Timeout, Test Project USB (GL) Failed");
- `else
- $display ("Monitor: Timeout, Test Project USB (RTL) Failed");
- `endif
- $display("%c[0m",27);
- $finish;
+ $error ("Monitor: Timeout, Test Project USB Failed");
+ //$fatal(1);
+ $finish;
end
// Write a byte to RX pin
@@ -172,8 +173,10 @@
input [7:0] i_Data;
integer ii;
begin
- wait(uut.mprj.mprj.usb2uart.in_ready == 1);
-
+ `ifdef GL
+ `else
+ //wait(uut.mprj.mprj.usb2uart.in_ready == 1);
+ `endif
// Write Start Bit
#(c_BIT_PERIOD) user_uart_rx <= 1'b0;
@@ -186,26 +189,44 @@
// Write Stop Bit
#(c_BIT_PERIOD) user_uart_rx <= 1'b1;
+ `ifdef GL
+ //wait(uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tvalid_reg == 1);
+ `else
//@(posedge uut.mprj.mprj.usb2uart.in_valid);
- wait(uut.mprj.mprj.usb2uart.in_valid == 1);
+ //wait(uut.mprj.mprj.usb2uart.in_valid == 1);
+ `endif
+ #(c_BIT_PERIOD);
end
endtask
initial begin
// Exercise Rx
j=0;
- for (i=0; i<8; i=i+1)
- begin
+ for (i=0; i<8; i=i+1) begin
UART_WRITE_RX_AND_RCV(i);
+ `ifdef GL
+ k[7:0] = {
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[7] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[6] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[5] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[4] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[3] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[2] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[1] ,
+ uut.mprj.mprj.\usb2uart.u_uart.uart_rx_inst.m_axis_tdata_reg[0] };
+ `else
k = uut.mprj.mprj.usb2uart.in_data;
+ `endif
+
if (k == i)
j=j+1;
else
- $display("RX Test Failed - Incorrect Byte Received 0x%x", k);
+ $error("RX Test Failed - Incorrect Byte Received 0x%x", k);
end
if (j == 8)
$display("RX Test Passed - Correct Bytes Received");
-
+ else
+ ;//$fatal(2);
$finish;
end
@@ -276,6 +297,7 @@
.io2(), // not used
.io3() // not used
);
+
/*
// Testbench UART
tbuart tbuart (
