remove unnecessary code from fpga test
diff --git a/verilog/rtl/fpga/fpga_pins.pcf b/verilog/rtl/fpga/fpga_pins.pcf
index e3054f5..16d878e 100644
--- a/verilog/rtl/fpga/fpga_pins.pcf
+++ b/verilog/rtl/fpga/fpga_pins.pcf
@@ -7,5 +7,4 @@
set_io usb_p B4
set_io uart_tx A2
set_io uart_rx A1
-set_io led B3
set_io clk B2
diff --git a/verilog/rtl/fpga/fpga_top.v b/verilog/rtl/fpga/fpga_top.v
index 08a615b..df4e986 100644
--- a/verilog/rtl/fpga/fpga_top.v
+++ b/verilog/rtl/fpga/fpga_top.v
@@ -1,6 +1,5 @@
module fpga_top (
input clk, // 16MHz Clock
- output led, // User LED ON=1, OFF=0
input uart_rx, // uart in
output uart_tx, // uart out
inout usb_p, // USB+
@@ -13,15 +12,12 @@
localparam c_UART_SPEED = 115200;
localparam c_CLKS_PER_BYTE = (c_CLOCK_MHZ*1000000+c_UART_SPEED*8-1)/(c_UART_SPEED*8);
- wire clk_pll;
- wire lock;
+ wire clk_pll;
+ pll pll48( .clock_in(clk), .clock_out(clk_pll) );
- wire dp_pu;
- wire dp_rx;
- wire dn_rx;
- wire dp_tx;
- wire dn_tx;
- wire tx_en;
+ reg [5:0] reset_cnt = 0;
+ wire rstn = &reset_cnt;
+ always @(posedge clk_pll) reset_cnt <= reset_cnt + !rstn;
wire in_ready;
wire [7:0] in_data;
@@ -30,21 +26,6 @@
wire [7:0] out_data;
wire out_valid;
- pll pll48( .clock_in(clk), .clock_out(clk_pll), .locked( lock ) );
-
- assign led = 1'b1;
-
- reg [1:0] rstn_sync;
- wire rstn;
- assign rstn = rstn_sync[0];
- always @(posedge clk_pll or negedge lock) begin
- if (~lock) begin
- rstn_sync <= 2'd0;
- end else begin
- rstn_sync <= {1'b1, rstn_sync[1]};
- end
- end
-
uart # (
.DATA_WIDTH(8)
) u_uart (
@@ -66,6 +47,21 @@
.prescale(c_CLKS_PER_BYTE)
);
+ wire dp_pu;
+ wire dp_rx;
+ wire dn_rx;
+ wire dp_tx;
+ wire dn_tx;
+ wire tx_en;
+
+ assign usb_p = tx_en ? dp_tx : 1'bz;
+ assign dp_rx = usb_p;
+
+ assign usb_n = tx_en ? dn_tx : 1'bz;
+ assign dn_rx = usb_n;
+
+ assign usb_pu = dp_pu;
+
usb_cdc #(
.VENDORID(16'h1D50),
.PRODUCTID(16'h6130)
@@ -84,9 +80,6 @@
.in_valid_i(in_valid),
.in_ready_o(in_ready),
- .frame_o(),
- .configured_o(),
-
.dp_pu_o(dp_pu),
.tx_en_o(tx_en),
.dp_tx_o(dp_tx),
@@ -95,50 +88,4 @@
.dn_rx_i(dn_rx)
);
- SB_IO #(
- .PIN_TYPE(6'b101001),
- .PULLUP(1'b0)
- ) u_usb_p (
- .PACKAGE_PIN(usb_p),
- .OUTPUT_ENABLE(tx_en),
- .D_OUT_0(dp_tx),
- .D_IN_0(dp_rx),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
-
- SB_IO #(
- .PIN_TYPE(6'b101001),
- .PULLUP(1'b0)
- ) u_usb_n (
- .PACKAGE_PIN(usb_n),
- .OUTPUT_ENABLE(tx_en),
- .D_OUT_0(dn_tx),
- .D_IN_0(dn_rx),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
-
- // drive usb_pu to 3.3V or to high impedance
- SB_IO #(
- .PIN_TYPE(6'b101001),
- .PULLUP(1'b0))
- u_usb_pu (
- .PACKAGE_PIN(usb_pu),
- .OUTPUT_ENABLE(dp_pu),
- .D_OUT_0(1'b1),
- .D_IN_0(),
- .D_OUT_1(1'b0),
- .D_IN_1(),
- .CLOCK_ENABLE(1'b0),
- .LATCH_INPUT_VALUE(1'b0),
- .INPUT_CLK(1'b0),
- .OUTPUT_CLK(1'b0));
-
endmodule
