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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-005 / 93c82cc2cdba0275153efeb1b0743a8e287b19ed / . / verilog / dv / user_usb / Makefile
blob: 1684a0d745efebf409efa7c03d1649137495236a [file] [log] [blame]
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]1# SPDX-FileCopyrightText: 2020 Efabless Corporation
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7# http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14#
15# SPDX-License-Identifier: Apache-2.0
16
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]17
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]18# ---- Include Partitioned Makefiles ----
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]19
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]20CONFIG = caravel_user_project
21
22#######################################################################
23## Caravel Verilog for Integration Tests
24#######################################################################
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]25
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]26DESIGNS?=../../..
27
28export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]29## YIFIVE FIRMWARE
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]30YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]31GCC64_PREFIX?=riscv64-unknown-elf
32
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]33
34## Simulation mode: RTL/GL
35SIM?=RTL
36DUMP?=OFF
37RISC_CORE?=0
38
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]39### To Enable IVERILOG FST DUMP
40export IVERILOG_DUMPER = fst
41
42
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]43.SUFFIXES:
44
45PATTERN = user_usb
46
47all: ${PATTERN:=.vcd}
48
49
50vvp: ${PATTERN:=.vvp}
51
52%.vvp: %_tb.v
53ifeq ($(SIM),RTL)
54 ifeq ($(DUMP),OFF)
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]55 iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
56 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]57 $< -o $@
58 else
dineshannayyad8a093b2022-03-26 08:32:19 +0530[diff] [blame]59 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
60 -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]61 $< -o $@
62 endif
63else
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame^]64 ifeq ($(DUMP),OFF)
65 iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
66 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]67 $< -o $@
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame^]68 else
69 iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DGL -I $(PDK_PATH) \
70 -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
71 $< -o $@
72 endif
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]73endif
74
75%.vcd: %.vvp
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame^]76 vvp $< +risc_core_id=$(RISC_CORE)
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]77
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]78
79# ---- Clean ----
80
81clean:
dineshannayya93c82cc2022-04-10 12:40:06 +0530[diff] [blame^]82 rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
dineshannayya00438892022-03-12 22:36:37 +0530[diff] [blame]83
84.PHONY: clean hex all