commit 93c82cc2cdba0275153efeb1b0743a8e287b19ed
author dineshannayya <dinesh.annayya@gmail.com> Sun Apr 10 12:40:06 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Sun Apr 10 12:40:06 2022 +0530
tree 754d563001d5e3c2c15cbcfd49be18de281a819a
parent 498cc8572601cff1bc3e17ac40eccf45cbe8322f

gatesim setup cleanup

verilog/dv/user_usb/Makefile

diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index a25bc69..1684a0d 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile
@@ -61,18 +61,24 @@
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp $< +risc_core_id=$(RISC_CORE)
 
 
 # ---- Clean ----
 
 clean:
-	rm -f *.vvp *.vcd *.log *.fst
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean hex all