icache and dcache bypass added
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 1534993..fe3302c 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -210,6 +210,10 @@ m1_wbd_sel_i\[2\] m1_wbd_sel_i\[1\] m1_wbd_sel_i\[0\] +m1_wbd_bl_i\[2\] +m1_wbd_bl_i\[1\] +m1_wbd_bl_i\[0\] +m1_wbd_bry_i m1_wbd_dat_i\[31\] m1_wbd_dat_i\[30\] m1_wbd_dat_i\[29\]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl index bc48c32..7775090 100644 --- a/openlane/ycr4_iconnect/config.tcl +++ b/openlane/ycr4_iconnect/config.tcl
@@ -60,7 +60,7 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 380 1900" +set ::env(DIE_AREA) "0 0 390 1900" #set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl #set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg index 0a74c77..43a1acb 100644 --- a/openlane/ycr4_iconnect/pin_order.cfg +++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -1563,7 +1563,10 @@ core_dmem_req_ack 0200 0 2 core_dmem_req -core_dmem_cmd +core_dmem_cmd +core_dmem_bl\[2\] +core_dmem_bl\[1\] +core_dmem_bl\[0\] core_dmem_width\[1\] core_dmem_width\[0\] core_dmem_addr\[31\] @@ -1759,3 +1762,5 @@ rtc_clk pwrup_rst_n cpu_intf_rst_n +cfg_bypass_icache +cfg_bypass_dcache
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 3b8f8cd..a482c0e 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -78,7 +78,7 @@ set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.43 -set ::env(CELL_PAD) "2" +set ::env(CELL_PAD) "4" #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} @@ -92,5 +92,5 @@ set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" #Need to cross-check why global timing opimization creating setup vio with hugh hold fix -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1" +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index cc500ad..08ea3db 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -70,6 +70,8 @@ set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.37 +set ::env(FP_IO_VEXTEND) {6} +set ::env(FP_IO_HEXTEND) {6} set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg index 6b93ea3..016df72 100644 --- a/openlane/ycr_intf/pin_order.cfg +++ b/openlane/ycr_intf/pin_order.cfg
@@ -186,6 +186,9 @@ core_dmem_req_ack 0200 0 2 core_dmem_req core_dmem_cmd +core_dmem_bl\[2\] +core_dmem_bl\[1\] +core_dmem_bl\[0\] core_dmem_width\[1\] core_dmem_width\[0\] core_dmem_addr\[31\] @@ -288,6 +291,8 @@ core_dmem_resp\[0\] cfg_dcache_force_flush +cfg_bypass_icache +cfg_bypass_dcache #S icache_mem_clk0 @@ -339,7 +344,7 @@ icache_mem_din0\[30\] icache_mem_din0\[31\] -icache_mem_clk1 100 0 2 +icache_mem_clk1 100 0 4 icache_mem_csb1 icache_mem_addr1\[8\] icache_mem_addr1\[7\] @@ -569,6 +574,10 @@ wbd_dmem_sel_o\[2\] wbd_dmem_sel_o\[1\] wbd_dmem_sel_o\[0\] +wbd_dmem_bl_o\[2\] +wbd_dmem_bl_o\[1\] +wbd_dmem_bl_o\[0\] +wbd_dmem_bry_o wbd_dmem_dat_o\[31\] wbd_dmem_dat_o\[30\] wbd_dmem_dat_o\[29\] @@ -633,6 +642,7 @@ wbd_dmem_dat_i\[2\] wbd_dmem_dat_i\[1\] wbd_dmem_dat_i\[0\] +wbd_dmem_lack_i wbd_dmem_ack_i wbd_dmem_err_i
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES index 16447f5..b08beb4 100644 --- a/signoff/pinmux/PDK_SOURCES +++ b/signoff/pinmux/PDK_SOURCES
@@ -1,3 +1 @@ -skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095 -magic 7d601628e4e05fd17fcb80c3552dacb64e9f6e7b \ No newline at end of file +open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES index 16447f5..b08beb4 100644 --- a/signoff/user_project_wrapper/PDK_SOURCES +++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,3 +1 @@ -skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095 -magic 7d601628e4e05fd17fcb80c3552dacb64e9f6e7b \ No newline at end of file +open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 17cd90d..6809b8a 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec user_cache_bypass user_gpio all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld index 222363d..b2a0030 100644 --- a/verilog/dv/firmware/link.ld +++ b/verilog/dv/firmware/link.ld
@@ -25,7 +25,7 @@ ENTRY(_start) MEMORY { - ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K + ROM (rxx) : ORIGIN = 0x0, LENGTH = 128K RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 64K TCM (rwx) : ORIGIN = 0x0C480000, LENGTH = 2K }
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index fd2adcb..15194cc 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -70,7 +70,7 @@ VECT_IRQ ?= 0 IPIC ?= 0 TCM ?= 0 - SIM_CFG_DEF = YCR1_CFG_$(CFG) + SIM_CFG_DEF = YCR_CFG_$(CFG) endif endif endif
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 8d892af..ceaec71 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -71,7 +71,7 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v"
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 69ee65d..b1e5ba9 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -167,6 +167,10 @@ end +// Hook to pll clock +wire pll_clock = u_top.u_wb_host.u_clkbuf_pll.X; + + initial begin @@ -278,8 +282,8 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2905_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_4000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000); end @@ -387,7 +391,7 @@ task pll_clock_monitor; input [15:0] exp_period; begin - force clock_mon = u_top.u_wb_host.pll_clk_out[0]; + force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X; check_clock_period("PLL CLock",exp_period); release clock_mon; end
diff --git a/verilog/dv/user_cache_bypass/Makefile b/verilog/dv/user_cache_bypass/Makefile new file mode 100644 index 0000000..eb7f108 --- /dev/null +++ b/verilog/dv/user_cache_bypass/Makefile
@@ -0,0 +1,95 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_cache_bypass + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_cache_bypass.c -o user_cache_bypass.o + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC64_PREFIX}-gcc -o user_cache_bypass.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_cache_bypass.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC64_PREFIX}-objcopy -O verilog user_cache_bypass.elf user_cache_bypass.hex + ${GCC64_PREFIX}-objdump -D user_cache_bypass.elf > user_cache_bypass.dump + rm crt.o user_cache_bypass.o +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< +risc_core_id=$(RISC_CORE) + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_cache_bypass/run_iverilog b/verilog/dv/user_cache_bypass/run_iverilog new file mode 100755 index 0000000..f083d6d --- /dev/null +++ b/verilog/dv/user_cache_bypass/run_iverilog
@@ -0,0 +1,42 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o + +riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 + +riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex + +riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump + +rm crt_tcm.o user_risc_boot.o + +#iverilog with waveform dump +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp + + +#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp + +# GLS +#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp + +vvp user_risc_boot_tb.vvp | tee test.log + +\rm -rf user_risc_boot_tb.vvp
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c new file mode 100644 index 0000000..9c99cd9 --- /dev/null +++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -0,0 +1,87 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// +#define SC_SIM_OUTPORT (0xf0000000) +#define uint32_t long +#define uint16_t int + +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) +#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) +#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) +#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) +#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) +#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) +#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) +#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) +#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) +#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) +#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) +#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) +#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) +#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) +#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) +#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) +#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) +#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) +#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) +#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) +#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) +#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) +#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +// ------------------------------------------------------------------------- +// Test copying code into SRAM and running it from there. +// ------------------------------------------------------------------------- + +void test_function() +{ + reg_mprj_globl_reg24 = 0x33445566; // Sig-3 + reg_mprj_globl_reg25 = 0x44556677; // Sig-4 + + return; +} + +void main() +{ + uint16_t func[&main - &test_function]; + uint16_t *src_ptr; + uint16_t *dst_ptr; + + + src_ptr = &test_function; + dst_ptr = func; + + reg_mprj_globl_reg22 = 0x11223344; // Sig-1 + while (src_ptr < &main) { + *(dst_ptr++) = *(src_ptr++); + } + + // Call the routine in SRAM + reg_mprj_globl_reg23 = 0x22334455; // Sig-2 + + ((void(*)())func)(); + + reg_mprj_globl_reg26 = 0x55667788; + reg_mprj_globl_reg27 = 0x66778899; + + // Signal end of test +} +
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v new file mode 100644 index 0000000..d6dfb2e --- /dev/null +++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -0,0 +1,425 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the Riscduino cores project //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core with Risc core executing code from TCM/SRAM. //// +//// with icache and dcache bypass mode //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +module user_cache_bypass_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + integer d_risc_id; + + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(2, user_cache_bypass_tb); + $dumpvars(0, user_cache_bypass_tb.u_top.u_riscv_top); + $dumpvars(0, user_cache_bypass_tb.u_top.u_intercon); + end + `endif + + initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + // Set the icahce and dcache bypass + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0}); + + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + end + + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (30) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + + + $display("Monitor: Reading Back the expected value"); + // User RISC core expect to write these value in global + // register, read back and decide on pass fail + // 0x30000018 = 0x11223344; + // 0x3000001C = 0x22334455; + // 0x30000020 = 0x33445566; + // 0x30000024 = 0x44556677; + // 0x30000028 = 0x55667788; + // 0x3000002C = 0x66778899; + + test_fail = 0; + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + + + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Standalone User Risc Boot (GL) Passed"); + `else + $display("Monitor: Standalone User Risc Boot (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone User Risc Boot (GL) Failed"); + `else + $display("Monitor: Standalone User Risc Boot (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + + wire flash_clk = io_out[24]; + wire flash_csb = io_out[25]; + // Creating Pad Delay + wire #1 io_oeb_29 = io_oeb[29]; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; + + // Quard flash + s25fl256s #(.mem_file_name("user_cache_bypass.hex"), + .otp_file_name("none"), + .TimingModel("S25FL512SAGMFI010_F_30pF")) + u_spi_flash_256mb ( + // Data Inputs/Outputs + .SI (flash_io0), + .SO (flash_io1), + // Controls + .SCK (flash_clk), + .CSNeg (flash_csb), + .WPNeg (flash_io2), + .HOLDNeg (flash_io3), + .RSTNeg (!wb_rst_i) + + ); + + + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`include "s25fl256s.sv" +`default_nettype wire
diff --git a/verilog/dv/user_gpio/.user_timer_tb.v.swp b/verilog/dv/user_gpio/.user_timer_tb.v.swp new file mode 100644 index 0000000..b5202d8 --- /dev/null +++ b/verilog/dv/user_gpio/.user_timer_tb.v.swp Binary files differ
diff --git a/verilog/dv/user_gpio/Makefile b/verilog/dv/user_gpio/Makefile new file mode 100644 index 0000000..6c8a24b --- /dev/null +++ b/verilog/dv/user_gpio/Makefile
@@ -0,0 +1,89 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_gpio + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< + + +# ---- Clean ---- + +clean: + rm -f *.vvp *.vcd *.log *.fst + +.PHONY: clean hex all
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v new file mode 100644 index 0000000..8badada --- /dev/null +++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -0,0 +1,742 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// http://www.opencores.org/cores/yifive/ //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// gpio interfaface through External WB i/F. //// +//// 1.gpio posedge & negedge interrupt generation //// +//// 2.gpio as input and output //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 01 Oct 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns/1 ps + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "is62wvs1288.v" + +`define TB_GLBL user_gpio_tb + +module user_gpio_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + + reg [1:0] spi_chip_no; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + integer test_step; + wire clock_mon; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + + /************* Port-A Mapping ********************************** + * ********************************************************/ + + reg [7:0] port_a_out; + wire [7:0] port_a_in = 8'h0; + + /************* Port-B Mapping ********************************** + * Pin-14 PB0/CLKO/ICP1 digital_io[11] + * Pin-15 PB1/SS[1]OC1A(PWM3) digital_io[12] + * Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] + * Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] + * Pin-18 PB4/MISO digital_io[15] + * Pin-19 PB5/SCK digital_io[16] + * Pin-9 PB6/XTAL1/TOSC1 digital_io[6] + * Pin-10 PB7/XTAL2/TOSC2 digital_io[7] + * ********************************************************/ + + reg [7:0] port_b_out; + wire [7:0] port_b_in = { io_out[7], + io_out[6], + io_out[16], + io_out[15], + io_out[14], + io_out[13], + io_out[12], + io_out[11] + }; + + assign { io_in[7], + io_in[6], + io_in[16], + io_in[15], + io_in[14], + io_in[13], + io_in[12], + io_in[11] + } = port_b_out; + + /************* Port-C Mapping ********************************** + * Pin-1 PC6/RESET* digital_io[0] + * Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] + * Pin-24 PC1/ADC1 digital_io[19]/analog_io[12] + * Pin-25 PC2/ADC2 digital_io[20]/analog_io[13] + * Pin-26 PC3/ADC3 digital_io[21]/analog_io[14] + * Pin-27 PC4/ADC4/SDA digital_io[22]/analog_io[15] + * Pin-28 PC5/ADC5/SCL digital_io[23]/analog_io[16] + * ********************************************************/ + + reg [7:0] port_c_out; + wire [7:0] port_c_in = { 1'b0, + io_out[0], + io_out[23], + io_out[22], + io_out[21], + io_out[20], + io_out[19], + io_out[18] + }; + assign { io_in[0], + io_in[23], + io_in[22], + io_in[21], + io_in[20], + io_in[19], + io_in[18] + } = port_c_out[6:0]; + + + /************* Port-D Mapping ********************************** + * Pin-2 PD0/RXD[0] digital_io[1] + * Pin-3 PD1/TXD[0] digital_io[2] + * Pin-4 PD2/RXD[1]/INT0 digital_io[3] + * Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] + * Pin-6 PD4/TXD[1] digital_io[5] + * Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] + * Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2] + * Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] + * ********************************************************/ + + reg [7:0] port_d_out; + wire [7:0] port_d_in = { io_out[10], + io_out[9], + io_out[8], + io_out[5], + io_out[4], + io_out[3], + io_out[2], + io_out[1] + }; + + assign { io_in[10], + io_in[9], + io_in[8], + io_in[5], + io_in[4], + io_in[3], + io_in[2], + io_in[1] + } = port_d_out; + + + /*****************************/ + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(1, `TB_GLBL); + $dumpvars(0, `TB_GLBL.u_top.u_wb_host); + $dumpvars(0, `TB_GLBL.u_top.u_intercon); + $dumpvars(0, `TB_GLBL.u_top.u_pinmux); + end + `endif + + initial begin + test_fail = 0; + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + + repeat (2) @(posedge clock); + #1; + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + // Disable Multi func + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h000); + + /************* GPIO As Output ******************/ + $display("#####################################"); + $display("Step-1: Testing GPIO As Output "); + // Set the Direction as Output + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'hFFFFFFFF); + // Set the GPIO Output data: 0x55555555 + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h55555555); + cmp_gpio_output(8'h55,8'h55,8'h55,8'h55); + + // Set the GPIO Output data: 0xAAAAAAAA + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hAAAAAAAA); + cmp_gpio_output(8'hAA,8'hAA,8'hAA,8'hAA); + + // Set the GPIO Output data: 0x5A5A5A5A5A5A + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h5A5A5A5A); + cmp_gpio_output(8'h5A,8'h5A,8'h5A,8'h5A); + + // Set the GPIO Output data: 0xA5A5A5A5A5A5 + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hA5A5A5A5); + cmp_gpio_output(8'hA5,8'hA5,8'hA5,8'hA5); + + /************* GPIO As Input ******************/ + $display("#####################################"); + $display("Step-2: Testing GPIO As Input "); + // Set the Direction as Input + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + + cmp_gpio_input(8'h55,8'h55,8'h55,8'h55); + cmp_gpio_input(8'hAA,8'hAA,8'hAA,8'hAA); + cmp_gpio_input(8'h5A,8'h5A,8'h5A,8'h5A); + cmp_gpio_input(8'hA5,8'hA5,8'hA5,8'hA5); + + /************* GPIO As Input & GPIO Pos edge Interrupt ******************/ + $display("#####################################"); + $display("Step-3: Testing GPIO As Posedge Interrupt "); + // Set the Direction as Input + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + // Set GPIO for posedge Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'h00000000); + + // Drive GPIO with 0x55 + cmp_gpio_pos_intr(8'h55,8'h55,8'h55,8'h55); + + // Drive GPIO with 0xAA + cmp_gpio_pos_intr(8'hAA,8'hAA,8'hAA,8'hAA); + + // Drive GPIO with 0x5A + cmp_gpio_pos_intr(8'h5A,8'h5A,8'h5A,8'h5A); + + // Drive GPIO with 0xA5 + cmp_gpio_pos_intr(8'hA5,8'hA5,8'hA5,8'hA5); + + repeat (200) @(posedge clock); + /************* GPIO As Input & GPIO NEG edge Interrupt ******************/ + $display("#####################################"); + $display("Step-3: Testing GPIO As Negedge Interrupt "); + // Set the Direction as Input + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + // Set GPIO for negedge Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'h00000000); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'hFFFFFFFF); + + // Drive GPIO with 0x55 + cmp_gpio_neg_intr(8'h55,8'h55,8'h55,8'h55); + + // Drive GPIO with 0xAA + cmp_gpio_neg_intr(8'hAA,8'hAA,8'hAA,8'hAA); + + // Drive GPIO with 0x5A + cmp_gpio_neg_intr(8'h5A,8'h5A,8'h5A,8'h5A); + + // Drive GPIO with 0xA5 + cmp_gpio_neg_intr(8'hA5,8'hA5,8'hA5,8'hA5); + + repeat (200) @(posedge clock); + + + repeat (100) @(posedge clock); + // $display("+1000 cycles"); + + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: GPIO Mode (GL) Passed"); + `else + $display("Monitor: GPIO Mode (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: GPIO Mode (GL) Failed"); + `else + $display("Monitor: GPIO Mode (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i = 1'b1; + #100; + wb_rst_i = 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + wire flash_io1; + wire flash_clk = io_out[16]; + wire spiram_csb = io_out[13]; + tri #1 flash_io0 = io_out[15]; + assign io_in[14] = flash_io1; + + tri #1 flash_io2 = 1'b1; + tri #1 flash_io3 = 1'b1; + + + is62wvs1288 #(.mem_file_name("flash1.hex")) + u_sfram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); + + +//---------------------------------------------------- +// Task +// -------------------------------------------------- +task test_err; +begin + test_fail = 1; +end +endtask + + +/*************************** +* Check the GPIO Output +* **************************/ + +task cmp_gpio_output; +input [7:0] exp_port_a; +input [7:0] exp_port_b; +input [7:0] exp_port_c; +input [7:0] exp_port_d; +begin + // Wait for some cycle to reg to be written through wbbone host + repeat (20) @(posedge clock); + + if((exp_port_a & 8'h00) != (port_a_in & 8'h00)) + begin + $display("ERROR: PORT A Exp: %x Rxd: %x",exp_port_a & 8'h00,port_a_in & 8'h00); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATYS: PORT A Data: %x Matched ",port_a_in & 8'h00); + end + + if((exp_port_b & 8'hFF) != (port_b_in & 8'hFF)) + begin + $display("ERROR: PORT B Exp: %x Rxd: %x",exp_port_b & 8'hFF,port_b_in & 8'hFF); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATYS: PORT B Data: %x Matched ",port_b_in & 8'hFF); + end + + if((exp_port_c & 8'h7F) != (port_c_in & 8'h7F)) + begin + $display("ERROR: PORT C Exp: %x Rxd: %x",exp_port_c & 8'h7F,port_c_in & 8'h7F); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATYS: PORT C Data: %x Matched ",port_c_in & 8'h7F); + end + + if((exp_port_d & 8'hFF) != (port_d_in & 8'hFF)) + begin + $display("ERROR: PORT D Exp: %x Rxd: %x",exp_port_d & 8'hFF,port_d_in & 8'hFF); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATYS: PORT D Data: %x Matched ",port_d_in & 8'hFF); + end +end +endtask + +/*************************** +* Check the GPIO input +* **************************/ + +task cmp_gpio_input; +input [7:0] port_a; +input [7:0] port_b; +input [7:0] port_c; +input [7:0] port_d; +begin + port_a_out = port_a; + port_b_out = port_b; + port_c_out = port_c; + port_d_out = port_d; + + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); +end +endtask + + +// Check for posedge Interrupt +task cmp_gpio_pos_intr; +input [7:0] port_a; +input [7:0] port_b; +input [7:0] port_c; +input [7:0] port_d; +begin + + // Drive GPIO with zero + cmp_gpio_input(8'h00,8'h00,8'h00,8'h00); + + // Clear Global Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000); + + // Clear all the Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF); + + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + + // Drive Ports + cmp_gpio_input(port_d,port_c,port_b,port_a); + + + // Wait for Edge Detection + repeat (20) @(posedge clock); + + // Drive GPIO with zero + cmp_gpio_input(8'h00,8'h00,8'h00,8'h00); + + // Wait for Edge Detection + repeat (20) @(posedge clock); + + // Check the GPIO Interrupt + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); + + // Check The Global Interrupt + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000); + + // Clear The GPIO Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF); + + // Clear GPIO Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000); + + + // Check Interrupt are cleared + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + +end +endtask + +// Check for negedge Interrupt +task cmp_gpio_neg_intr; +input [7:0] port_a; +input [7:0] port_b; +input [7:0] port_c; +input [7:0] port_d; +begin + + // Drive GPIO with All One's + cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF); + + // Clear Global Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000); + + // Clear all the Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + + // Drive Ports + cmp_gpio_input(port_d,port_c,port_b,port_a); + + // Wait for Edge Detection + repeat (20) @(posedge clock); + + // Drive GPIO with All One's + cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF); + + // Wait for Edge Detection + repeat (20) @(posedge clock); + + // Neg edge interrupt is will compliment of input value + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0}); + + // Check The Global Interrupt + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000); + + // Clear The GPIO Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF); + + // Clear GPIO Interrupt + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000); + + // Check Interrupt are cleared + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); +end +endtask + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + `TB_GLBL.test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; +wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index e02f2cd..552ff6f 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -718,7 +718,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h2905_2022) u_reg_23 ( +gen_32b_reg #(32'h1306_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -731,9 +731,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 4.4 = 0004400 +// Software Reg-3: Poject Revison 4.6 = 0004600 // ---------------------------------------- -gen_32b_reg #(32'h0004_4000) u_reg_24 ( +gen_32b_reg #(32'h0004_6000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 6a9eaf3..469d4c6 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -209,6 +209,8 @@ //// 4.4 May 29 2022, Dinesh A //// //// 1. Digital PLL integrated and clock debug signal add //// //// @digitial io [33] port +//// 4.6 June 13 2022, Dinesh A //// +//// 1. icache and dcache bypass config addded //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -359,8 +361,11 @@ wire wbd_riscv_dmem_we_i ; // write wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i ; // data output wire [3:0] wbd_riscv_dmem_sel_i ; // byte enable +wire [2:0] wbd_riscv_dmem_bl_i ; // byte enable +wire wbd_riscv_dmem_bry_i ; // burst access ready wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o ; // data input wire wbd_riscv_dmem_ack_o ; // acknowlegement +wire wbd_riscv_dmem_lack_o ; // acknowlegement wire wbd_riscv_dmem_err_o ; // error //--------------------------------------------------------------------- @@ -611,6 +616,8 @@ wire [3:0] cfg_riscv_sram_lphase = cfg_riscv_ctrl[3:0]; wire [2:0] cfg_riscv_cache_ctrl = cfg_riscv_ctrl[6:4]; wire [1:0] cfg_riscv_debug_sel = cfg_riscv_ctrl[9:8]; +wire cfg_bypass_icache = cfg_riscv_ctrl[10]; +wire cfg_bypass_dcache = cfg_riscv_ctrl[11]; ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -732,6 +739,8 @@ .core_debug_sel (cfg_riscv_debug_sel ), .cfg_sram_lphase (cfg_riscv_sram_lphase ), .cfg_cache_ctrl (cfg_riscv_cache_ctrl ), + .cfg_bypass_icache (cfg_bypass_icache ), + .cfg_bypass_dcache (cfg_bypass_dcache ), // Clock .core_clk (cpu_clk ), @@ -841,8 +850,11 @@ .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), + .wbd_dmem_bl_o (wbd_riscv_dmem_bl_i ), + .wbd_dmem_bry_o (wbd_riscv_dmem_bry_i ), .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), + .wbd_dmem_lack_i (wbd_riscv_dmem_lack_o ), .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) ); @@ -1049,11 +1061,14 @@ .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), + .m1_wbd_bl_i (wbd_riscv_dmem_bl_i ), + .m1_wbd_bry_i (wbd_riscv_dmem_bry_i ), .m1_wbd_we_i (wbd_riscv_dmem_we_i ), .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), + .m1_wbd_lack_o (wbd_riscv_dmem_lack_o ), .m1_wbd_err_o (wbd_riscv_dmem_err_o ), // Master 2 Interface
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 8ab9487..9fb6344 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -136,6 +136,8 @@ input logic [31:0] m1_wbd_dat_i, input logic [31:0] m1_wbd_adr_i, input logic [3:0] m1_wbd_sel_i, + input logic [2:0] m1_wbd_bl_i, + input logic m1_wbd_bry_i, input logic m1_wbd_we_i, input logic m1_wbd_cyc_i, input logic m1_wbd_stb_i, @@ -363,6 +365,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ), @@ -441,6 +445,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ), @@ -519,6 +525,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv index 87f0d4a..bc70ea2 100644 --- a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv +++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -61,6 +61,8 @@ input logic [31:0] m1_wbd_dat_i, input logic [31:0] m1_wbd_adr_i, input logic [3:0] m1_wbd_sel_i, + input logic [2:0] m1_wbd_bl_i, + input logic m1_wbd_bry_i, input logic m1_wbd_we_i, input logic m1_wbd_cyc_i, input logic m1_wbd_stb_i, @@ -172,8 +174,8 @@ assign m1_wb_wr.wbd_dat = m1_wbd_dat_i; assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00}; assign m1_wb_wr.wbd_sel = m1_wbd_sel_i; -assign m1_wb_wr.wbd_bl = 'h1; -assign m1_wb_wr.wbd_bry = 'b1; +assign m1_wb_wr.wbd_bl = {7'b0,m1_wbd_bl_i}; +assign m1_wb_wr.wbd_bry = m1_wbd_bry_i; assign m1_wb_wr.wbd_we = m1_wbd_we_i; assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i; assign m1_wb_wr.wbd_stb = m1_stb_i;
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c index 724e944..3175d5b 160000 --- a/verilog/rtl/yifive/ycr4c +++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@ -Subproject commit 724e944688a135294783a4e41f82d13e66a401c1 +Subproject commit 3175d5b4a7a7305ea9942723644eabb787e4b0bd