| dineshannayya | e853c36 | 2022-02-22 21:24:03 +0530 | [diff] [blame] | 1 | [submodule "verilog/rtl/yifive/ycr2c"] |
| 2 | path = verilog/rtl/yifive/ycr2c |
| 3 | url = https://github.com/dineshannayya/ycr2c.git |
| dineshannayya | 54cd5f6 | 2022-04-02 17:08:28 +0530 | [diff] [blame] | 4 | [submodule "verilog/rtl/qspim"] |
| 5 | path = verilog/rtl/qspim |
| 6 | url = https://github.com/dineshannayya/qspim.git |
| dineshannayya | acbf15f | 2022-07-04 11:59:41 +0530 | [diff] [blame] | 7 | [submodule "verilog/dv/common/riscduino_board"] |
| 8 | path = verilog/dv/common/riscduino_board |
| 9 | url = https://github.com/dineshannayya/riscduino_board.git |
| dineshannayya | 47fa184 | 2022-11-14 08:22:27 +0530 | [diff] [blame] | 10 | [submodule "verilog/rtl/security_core"] |
| 11 | path = verilog/rtl/security_core |
| 12 | url = https://github.com/dineshannayya/security_core |
| 13 | [submodule "verilog/rtl/fpu"] |
| 14 | path = verilog/rtl/fpu |
| 15 | url = https://github.com/dineshannayya/fpu |
| dineshannayya | ac1171f | 2022-12-10 22:11:59 +0530 | [diff] [blame] | 16 | [submodule "verilog/rtl/rtc"] |
| 17 | path = verilog/rtl/rtc |
| 18 | url = https://github.com/dineshannayya/rtc |
