| commit | ac1171fcdd17d57f16bdadd3cd5a8d35a1fb87d8 | [log] [tgz] |
|---|---|---|
| author | dineshannayya <dinesh.annayya@gmail.com> | Sat Dec 10 22:11:59 2022 +0530 |
| committer | dineshannayya <dinesh.annayya@gmail.com> | Sat Dec 10 22:11:59 2022 +0530 |
| tree | 32b545be06736756ceabdfafadd8d67d7b1f3905 | |
| parent | ee90a108ea3975e443263f1b3ba5ee3937c7c80f [diff] [blame] |
rtc integration
diff --git a/.gitmodules b/.gitmodules index 5426bcd..df1d438 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -13,3 +13,6 @@ [submodule "verilog/rtl/fpu"] path = verilog/rtl/fpu url = https://github.com/dineshannayya/fpu +[submodule "verilog/rtl/rtc"] + path = verilog/rtl/rtc + url = https://github.com/dineshannayya/rtc