final gds oasis
diff --git a/mpw_precheck/logs/gds.info b/mpw_precheck/logs/gds.info
new file mode 100644
index 0000000..3ad222b
--- /dev/null
+++ b/mpw_precheck/logs/gds.info
@@ -0,0 +1 @@
+user_project_wrapper.gds: 6827dd3ff4694632747e41f2c2ffe4f5e28f5dbf
\ No newline at end of file
diff --git a/mpw_precheck/logs/git.info b/mpw_precheck/logs/git.info
new file mode 100644
index 0000000..58fb411
--- /dev/null
+++ b/mpw_precheck/logs/git.info
@@ -0,0 +1,3 @@
+Repository: https://github.com/dineshannayya/riscduino_dcore.git
+Branch: main
+Commit: ddec3fbfabd8cef36812a3f9e833e94adfc47f23
diff --git a/mpw_precheck/logs/klayout_beol_check.log b/mpw_precheck/logs/klayout_beol_check.log
new file mode 100644
index 0000000..c4982f5
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.log
@@ -0,0 +1,1005 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:54: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 1605360 (flat)  968 (hierarchical)
+    Elapsed: 0.270s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:125
+    Polygons (raw): 293536 (flat)  37 (hierarchical)
+    Elapsed: 0.200s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:126
+    Polygons (raw): 750236 (flat)  337 (hierarchical)
+    Elapsed: 0.170s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:127
+    Polygons (raw): 3 (flat)  1 (hierarchical)
+    Elapsed: 0.020s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:128
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:129
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:130
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:131
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:132
+    Polygons (raw): 743584 (flat)  268 (hierarchical)
+    Elapsed: 0.160s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:133
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:135
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:137
+    Polygons (raw): 2663013 (flat)  3005 (hierarchical)
+    Elapsed: 0.190s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:138
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:139
+    Polygons (raw): 1023725 (flat)  389 (hierarchical)
+    Elapsed: 0.160s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:140
+    Polygons (raw): 920152 (flat)  382 (hierarchical)
+    Elapsed: 0.160s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:141
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:142
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:143
+    Polygons (raw): 805756 (flat)  392 (hierarchical)
+    Elapsed: 0.180s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:144
+    Polygons (raw): 8813309 (flat)  9554 (hierarchical)
+    Elapsed: 0.170s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:146
+    Polygons (raw): 6213128 (flat)  485316 (hierarchical)
+    Elapsed: 0.450s  Memory: 1045.00M
+"polygons" in: sky130A_mr.drc:147
+    Polygons (raw): 9197667 (flat)  481860 (hierarchical)
+    Elapsed: 0.430s  Memory: 1056.00M
+"polygons" in: sky130A_mr.drc:149
+    Polygons (raw): 6544380 (flat)  2662817 (hierarchical)
+    Elapsed: 1.770s  Memory: 1122.00M
+"polygons" in: sky130A_mr.drc:150
+    Polygons (raw): 1674104 (flat)  907533 (hierarchical)
+    Elapsed: 0.710s  Memory: 1138.00M
+"polygons" in: sky130A_mr.drc:152
+    Polygons (raw): 2881387 (flat)  1272994 (hierarchical)
+    Elapsed: 0.980s  Memory: 1168.00M
+"polygons" in: sky130A_mr.drc:153
+    Polygons (raw): 363409 (flat)  302120 (hierarchical)
+    Elapsed: 0.380s  Memory: 1172.00M
+"polygons" in: sky130A_mr.drc:155
+    Polygons (raw): 458636 (flat)  313361 (hierarchical)
+    Elapsed: 0.380s  Memory: 1181.00M
+"polygons" in: sky130A_mr.drc:156
+    Polygons (raw): 299110 (flat)  253152 (hierarchical)
+    Elapsed: 0.350s  Memory: 1185.00M
+"polygons" in: sky130A_mr.drc:158
+    Polygons (raw): 73561 (flat)  43869 (hierarchical)
+    Elapsed: 0.220s  Memory: 1186.00M
+"polygons" in: sky130A_mr.drc:159
+    Polygons (raw): 40820 (flat)  40820 (hierarchical)
+    Elapsed: 0.030s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:161
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:163
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:164
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:165
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:166
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:167
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:168
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:169
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:170
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:171
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:172
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:173
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:174
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:175
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:176
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:177
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:178
+    Polygons (raw): 51480 (flat)  4 (hierarchical)
+    Elapsed: 0.020s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:179
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:180
+    Polygons (raw): 790579 (flat)  451 (hierarchical)
+    Elapsed: 0.160s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:181
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:182
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:183
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:184
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:185
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:186
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:187
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:188
+    Polygons (raw): 8 (flat)  7 (hierarchical)
+    Elapsed: 0.140s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:189
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:190
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:191
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:192
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:193
+    Polygons (raw): 46860 (flat)  1 (hierarchical)
+    Elapsed: 0.190s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:194
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:195
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:196
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:197
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:198
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:199
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:200
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:201
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:202
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:203
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:204
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:205
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:206
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:207
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:208
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:209
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:210
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:211
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:212
+    Polygons (raw): 5100 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:213
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:214
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:215
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+DRC section
+BEOL section
+START: 67/20 (li)
+"interacting" in: sky130A_mr.drc:397
+    Polygons (raw): 478755 (flat)  25117 (hierarchical)
+    Elapsed: 49.940s  Memory: 2361.00M
+"not" in: sky130A_mr.drc:397
+    Polygons (raw): 4476408 (flat)  485174 (hierarchical)
+    Elapsed: 4.340s  Memory: 2361.00M
+"width" in: sky130A_mr.drc:398
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 50.990s  Memory: 2413.00M
+"output" in: sky130A_mr.drc:398
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2413.00M
+"edges" in: sky130A_mr.drc:400
+    Edges: 22783125 (flat)  2349295 (hierarchical)
+    Elapsed: 220.200s  Memory: 2605.00M
+"space" in: sky130A_mr.drc:400
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 72.510s  Memory: 3527.00M
+"output" in: sky130A_mr.drc:400
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3527.00M
+"not" in: sky130A_mr.drc:401
+    Polygons (raw): 6843273 (flat)  9433 (hierarchical)
+    Elapsed: 1.320s  Memory: 3527.00M
+"enclosing" in: sky130A_mr.drc:402
+    Edge pairs: 6847363 (flat)  3706403 (hierarchical)
+    Elapsed: 190.930s  Memory: 3783.00M
+"second_edges" in: sky130A_mr.drc:402
+    Edges: 6847363 (flat)  3706403 (hierarchical)
+    Elapsed: 0.220s  Memory: 3783.00M
+"width" in: sky130A_mr.drc:403
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 23.270s  Memory: 4150.00M
+"polygons" in: sky130A_mr.drc:404
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4150.00M
+"interacting" in: sky130A_mr.drc:404
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.950s  Memory: 4150.00M
+"output" in: sky130A_mr.drc:405
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4150.00M
+"with_area" in: sky130A_mr.drc:406
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 1.010s  Memory: 4150.00M
+"output" in: sky130A_mr.drc:406
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4150.00M
+END: 67/20 (li)
+START: 67/44 (mcon)
+"not" in: sky130A_mr.drc:411
+    Polygons (raw): 7929155 (flat)  481777 (hierarchical)
+    Elapsed: 1.860s  Memory: 4150.00M
+"not" in: sky130A_mr.drc:418
+    Polygons (raw): 7929155 (flat)  481777 (hierarchical)
+    Elapsed: 1.810s  Memory: 4150.00M
+"non_rectangles" in: sky130A_mr.drc:419
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 71.870s  Memory: 4501.00M
+"output" in: sky130A_mr.drc:419
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4501.00M
+"drc" in: sky130A_mr.drc:421
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 84.770s  Memory: 4549.00M
+"output" in: sky130A_mr.drc:421
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"drc" in: sky130A_mr.drc:422
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 13.970s  Memory: 4549.00M
+"output" in: sky130A_mr.drc:422
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"space" in: sky130A_mr.drc:423
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 17.160s  Memory: 4549.00M
+"output" in: sky130A_mr.drc:423
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"not" in: sky130A_mr.drc:429
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 79.200s  Memory: 4549.00M
+"output" in: sky130A_mr.drc:429
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+END: 67/44 (mcon)
+START: 68/20 (m1)
+"width" in: sky130A_mr.drc:434
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 51.460s  Memory: 4549.00M
+"output" in: sky130A_mr.drc:434
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"sized" in: sky130A_mr.drc:435
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 14.640s  Memory: 4549.00M
+"sized" in: sky130A_mr.drc:435
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"snap" in: sky130A_mr.drc:435
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.600s  Memory: 4549.00M
+"&" in: sky130A_mr.drc:435
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 4549.00M
+"edges" in: sky130A_mr.drc:436
+    Edges: 17676759 (flat)  10427650 (hierarchical)
+    Elapsed: 172.240s  Memory: 5125.00M
+"-" in: sky130A_mr.drc:436
+    Edges: 17676759 (flat)  10427650 (hierarchical)
+    Elapsed: 0.110s  Memory: 5125.00M
+"edges" in: sky130A_mr.drc:437
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5125.00M
+"merged" in: sky130A_mr.drc:437
+    Polygons (raw): 761911 (flat)  589563 (hierarchical)
+    Elapsed: 0.020s  Memory: 5125.00M
+"outside_part" in: sky130A_mr.drc:437
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 5125.00M
+"space" in: sky130A_mr.drc:439
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 178.270s  Memory: 6706.00M
+"output" in: sky130A_mr.drc:439
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6706.00M
+"separation" in: sky130A_mr.drc:441
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6706.00M
+"space" in: sky130A_mr.drc:441
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6706.00M
+"+" in: sky130A_mr.drc:441
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6706.00M
+"output" in: sky130A_mr.drc:441
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 6706.00M
+"input" in: sky130A_mr.drc:445
+    Polygons (raw): 6544380 (flat)  3095735 (hierarchical)
+    Elapsed: 2.130s  Memory: 6706.00M
+"enclosing" in: sky130A_mr.drc:447
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 129.540s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:447
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"not" in: sky130A_mr.drc:448
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 90.860s  Memory: 6780.00M
+"output" in: sky130A_mr.drc:448
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 6770.00M
+"input" in: sky130A_mr.drc:450
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.280s  Memory: 6770.00M
+"enclosing" in: sky130A_mr.drc:451
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 6770.00M
+"output" in: sky130A_mr.drc:451
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6770.00M
+"not" in: sky130A_mr.drc:453
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6770.00M
+"output" in: sky130A_mr.drc:453
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6770.00M
+"with_area" in: sky130A_mr.drc:455
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 1.000s  Memory: 6770.00M
+"output" in: sky130A_mr.drc:455
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6770.00M
+"holes" in: sky130A_mr.drc:457
+    Polygons (raw): 32 (flat)  32 (hierarchical)
+    Elapsed: 0.410s  Memory: 6770.00M
+"with_area" in: sky130A_mr.drc:457
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.500s  Memory: 6770.00M
+"output" in: sky130A_mr.drc:457
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6770.00M
+"enclosing" in: sky130A_mr.drc:464
+    Edge pairs: 1648587 (flat)  1297290 (hierarchical)
+    Elapsed: 73.830s  Memory: 6642.00M
+"second_edges" in: sky130A_mr.drc:464
+    Edges: 1648587 (flat)  1297290 (hierarchical)
+    Elapsed: 0.090s  Memory: 6642.00M
+"width" in: sky130A_mr.drc:465
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 5.950s  Memory: 6642.00M
+"polygons" in: sky130A_mr.drc:466
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"interacting" in: sky130A_mr.drc:466
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 82.480s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:467
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+END: 68/20 (m1)
+START: 68/44 (via)
+"not" in: sky130A_mr.drc:481
+    Polygons (raw): 1674104 (flat)  1044878 (hierarchical)
+    Elapsed: 0.030s  Memory: 6642.00M
+"non_rectangles" in: sky130A_mr.drc:483
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 8.690s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:483
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"width" in: sky130A_mr.drc:484
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.900s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:484
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"drc" in: sky130A_mr.drc:486
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.920s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:486
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"space" in: sky130A_mr.drc:488
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 12.200s  Memory: 6642.00M
+"output" in: sky130A_mr.drc:488
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 6642.00M
+"edges" in: sky130A_mr.drc:496
+    Edges: 17676759 (flat)  10427650 (hierarchical)
+    Elapsed: 176.050s  Memory: 6834.00M
+"drc" in: sky130A_mr.drc:496
+    Edges: 5223680 (flat)  4311316 (hierarchical)
+    Elapsed: 17.720s  Memory: 6706.00M
+"enclosing" in: sky130A_mr.drc:496
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 142.600s  Memory: 8047.00M
+"output" in: sky130A_mr.drc:496
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8047.00M
+"squares" in: sky130A_mr.drc:497
+    Polygons (raw): 1305920 (flat)  1077829 (hierarchical)
+    Elapsed: 0.610s  Memory: 8047.00M
+"drc" in: sky130A_mr.drc:497
+    Edges: 5223680 (flat)  4311316 (hierarchical)
+    Elapsed: 17.400s  Memory: 8047.00M
+"not" in: sky130A_mr.drc:497
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 46.570s  Memory: 8047.00M
+"output" in: sky130A_mr.drc:497
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8047.00M
+"edges" in: sky130A_mr.drc:499
+    Edges: 17676759 (flat)  10427650 (hierarchical)
+    Elapsed: 171.910s  Memory: 8239.00M
+"drc" in: sky130A_mr.drc:499
+    Edges: 5223680 (flat)  4311316 (hierarchical)
+    Elapsed: 17.750s  Memory: 8047.00M
+"enclosing" in: sky130A_mr.drc:499
+    Edge pairs: 1506331 (flat)  1482719 (hierarchical)
+    Elapsed: 159.150s  Memory: 8566.00M
+"second_edges" in: sky130A_mr.drc:499
+    Edges: 1506331 (flat)  1482719 (hierarchical)
+    Elapsed: 0.100s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:500
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 5.130s  Memory: 8566.00M
+"polygons" in: sky130A_mr.drc:501
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"interacting" in: sky130A_mr.drc:501
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.340s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:502
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 68/44 (via)
+START: 69/20 (m2)
+"width" in: sky130A_mr.drc:509
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 11.840s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:509
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:511
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 8.100s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:511
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"snap" in: sky130A_mr.drc:511
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.150s  Memory: 8566.00M
+"&" in: sky130A_mr.drc:511
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:512
+    Edges: 8731383 (flat)  5764501 (hierarchical)
+    Elapsed: 33.280s  Memory: 8566.00M
+"-" in: sky130A_mr.drc:512
+    Edges: 8731383 (flat)  5764501 (hierarchical)
+    Elapsed: 0.070s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:513
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"merged" in: sky130A_mr.drc:513
+    Polygons (raw): 387789 (flat)  377264 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"outside_part" in: sky130A_mr.drc:513
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:514
+    Polygons (raw): 1065704 (flat)  1044734 (hierarchical)
+    Elapsed: 1.470s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:516
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 72.990s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:516
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"separation" in: sky130A_mr.drc:518
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:518
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"+" in: sky130A_mr.drc:518
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:518
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"with_area" in: sky130A_mr.drc:520
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.730s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:520
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"holes" in: sky130A_mr.drc:521
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 8566.00M
+"with_area" in: sky130A_mr.drc:521
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.470s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:521
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:526
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 10.960s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:526
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:527
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 6.830s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:527
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:528
+    Edge pairs: 1770579 (flat)  1613639 (hierarchical)
+    Elapsed: 22.470s  Memory: 8566.00M
+"second_edges" in: sky130A_mr.drc:528
+    Edges: 1770579 (flat)  1613639 (hierarchical)
+    Elapsed: 0.110s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:529
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 6.310s  Memory: 8566.00M
+"polygons" in: sky130A_mr.drc:530
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"interacting" in: sky130A_mr.drc:530
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.350s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:531
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 69/20 (m2)
+START: 69/44 (via2)
+"not" in: sky130A_mr.drc:546
+    Polygons (raw): 363409 (flat)  346065 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"non_rectangles" in: sky130A_mr.drc:547
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.920s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:547
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:548
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.300s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:548
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:549
+    Edges: 1453636 (flat)  1384260 (hierarchical)
+    Elapsed: 2.310s  Memory: 8566.00M
+"without_length" in: sky130A_mr.drc:549
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.970s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:549
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:550
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.150s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:550
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:558
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.170s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:558
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:559
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.310s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:559
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:561
+    Edge pairs: 216458 (flat)  199064 (hierarchical)
+    Elapsed: 4.060s  Memory: 8566.00M
+"second_edges" in: sky130A_mr.drc:561
+    Edges: 216458 (flat)  199064 (hierarchical)
+    Elapsed: 0.030s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:562
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.270s  Memory: 8566.00M
+"polygons" in: sky130A_mr.drc:563
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"interacting" in: sky130A_mr.drc:563
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:564
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 69/44 (via2)
+START: 70/20 (m3)
+"width" in: sky130A_mr.drc:570
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.990s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:570
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:572
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 1.630s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:572
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"snap" in: sky130A_mr.drc:572
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 8566.00M
+"&" in: sky130A_mr.drc:572
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:573
+    Edges: 1231325 (flat)  1157255 (hierarchical)
+    Elapsed: 11.340s  Memory: 8566.00M
+"-" in: sky130A_mr.drc:573
+    Edges: 1231325 (flat)  1157255 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:574
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"merged" in: sky130A_mr.drc:574
+    Polygons (raw): 82416 (flat)  78036 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"outside_part" in: sky130A_mr.drc:574
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:576
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 8.640s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:576
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"separation" in: sky130A_mr.drc:578
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:578
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"+" in: sky130A_mr.drc:578
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:578
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:583
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.930s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:583
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:584
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.050s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:584
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 70/20 (m3)
+START: 70/44 (via3)
+"not" in: sky130A_mr.drc:598
+    Polygons (raw): 299110 (flat)  287616 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"non_rectangles" in: sky130A_mr.drc:599
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.500s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:599
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:600
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.250s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:600
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:601
+    Edges: 1196440 (flat)  1150464 (hierarchical)
+    Elapsed: 1.920s  Memory: 8566.00M
+"without_length" in: sky130A_mr.drc:601
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.320s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:601
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:603
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.530s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:603
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:604
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.280s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:604
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:605
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 1.410s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:605
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:607
+    Edge pairs: 574186 (flat)  572970 (hierarchical)
+    Elapsed: 6.060s  Memory: 8566.00M
+"second_edges" in: sky130A_mr.drc:607
+    Edges: 574186 (flat)  572970 (hierarchical)
+    Elapsed: 0.050s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:608
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.470s  Memory: 8566.00M
+"polygons" in: sky130A_mr.drc:609
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"interacting" in: sky130A_mr.drc:609
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.260s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:610
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 70/44 (via3)
+START: 71/20 (m4)
+"width" in: sky130A_mr.drc:616
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.800s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:616
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:618
+    Polygons (raw): 600 (flat)  600 (hierarchical)
+    Elapsed: 0.360s  Memory: 8566.00M
+"sized" in: sky130A_mr.drc:618
+    Polygons (raw): 600 (flat)  600 (hierarchical)
+    Elapsed: 0.150s  Memory: 8566.00M
+"snap" in: sky130A_mr.drc:618
+    Polygons (raw): 600 (flat)  600 (hierarchical)
+    Elapsed: 0.530s  Memory: 8566.00M
+"&" in: sky130A_mr.drc:618
+    Polygons (raw): 600 (flat)  600 (hierarchical)
+    Elapsed: 0.130s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:619
+    Edges: 251924 (flat)  212916 (hierarchical)
+    Elapsed: 1.670s  Memory: 8566.00M
+"-" in: sky130A_mr.drc:619
+    Edges: 247042 (flat)  208034 (hierarchical)
+    Elapsed: 0.580s  Memory: 8566.00M
+"edges" in: sky130A_mr.drc:620
+    Edges: 2400 (flat)  2400 (hierarchical)
+    Elapsed: 0.090s  Memory: 8566.00M
+"merged" in: sky130A_mr.drc:620
+    Polygons (raw): 20037 (flat)  16485 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"outside_part" in: sky130A_mr.drc:620
+    Edges: 2400 (flat)  2400 (hierarchical)
+    Elapsed: 0.130s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:622
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.120s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:622
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"with_area" in: sky130A_mr.drc:624
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.170s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:624
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"separation" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.460s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"+" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:626
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:631
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.840s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:631
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:632
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 1.400s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:632
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 71/20 (m4)
+START: 71/44 (via4)
+"not" in: sky130A_mr.drc:645
+    Polygons (raw): 40820 (flat)  40820 (hierarchical)
+    Elapsed: 0.020s  Memory: 8566.00M
+"non_rectangles" in: sky130A_mr.drc:646
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.620s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:646
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"width" in: sky130A_mr.drc:647
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.650s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:647
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"drc" in: sky130A_mr.drc:648
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.150s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:648
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:650
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 8566.00M
+"polygons" in: sky130A_mr.drc:650
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:650
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:658
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.990s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:658
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:659
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.690s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:659
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 71/44 (via4)
+START: 72/20 (m5)
+"width" in: sky130A_mr.drc:664
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.320s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:664
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"space" in: sky130A_mr.drc:666
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:666
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 8566.00M
+"enclosing" in: sky130A_mr.drc:668
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.310s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:668
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"not" in: sky130A_mr.drc:669
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.120s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:669
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+"with_area" in: sky130A_mr.drc:673
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.140s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:673
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 72/20 (m5)
+START: 76/20 (pad)
+"space" in: sky130A_mr.drc:678
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.330s  Memory: 8566.00M
+"output" in: sky130A_mr.drc:678
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 8566.00M
+END: 76/20 (pad)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 2797.980s  Memory: 8302.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_beol_check.total b/mpw_precheck/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_feol_check.log b/mpw_precheck/logs/klayout_feol_check.log
new file mode 100644
index 0000000..1e65754
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.log
@@ -0,0 +1,817 @@
+/opt/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 1605360 (flat)  968 (hierarchical)
+    Elapsed: 0.260s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:125
+    Polygons (raw): 293536 (flat)  37 (hierarchical)
+    Elapsed: 0.200s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:126
+    Polygons (raw): 750236 (flat)  337 (hierarchical)
+    Elapsed: 0.160s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:127
+    Polygons (raw): 3 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:128
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:129
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:130
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:131
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:132
+    Polygons (raw): 743584 (flat)  268 (hierarchical)
+    Elapsed: 0.160s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:133
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:135
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:137
+    Polygons (raw): 2663013 (flat)  3005 (hierarchical)
+    Elapsed: 0.190s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:138
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:139
+    Polygons (raw): 1023725 (flat)  389 (hierarchical)
+    Elapsed: 0.160s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:140
+    Polygons (raw): 920152 (flat)  382 (hierarchical)
+    Elapsed: 0.170s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:141
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:142
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:143
+    Polygons (raw): 805756 (flat)  392 (hierarchical)
+    Elapsed: 0.170s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:144
+    Polygons (raw): 8813309 (flat)  9554 (hierarchical)
+    Elapsed: 0.170s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:146
+    Polygons (raw): 6213128 (flat)  485316 (hierarchical)
+    Elapsed: 0.450s  Memory: 1045.00M
+"polygons" in: sky130A_mr.drc:147
+    Polygons (raw): 9197667 (flat)  481860 (hierarchical)
+    Elapsed: 0.420s  Memory: 1056.00M
+"polygons" in: sky130A_mr.drc:149
+    Polygons (raw): 6544380 (flat)  2662817 (hierarchical)
+    Elapsed: 1.770s  Memory: 1122.00M
+"polygons" in: sky130A_mr.drc:150
+    Polygons (raw): 1674104 (flat)  907533 (hierarchical)
+    Elapsed: 0.700s  Memory: 1138.00M
+"polygons" in: sky130A_mr.drc:152
+    Polygons (raw): 2881387 (flat)  1272994 (hierarchical)
+    Elapsed: 0.970s  Memory: 1168.00M
+"polygons" in: sky130A_mr.drc:153
+    Polygons (raw): 363409 (flat)  302120 (hierarchical)
+    Elapsed: 0.370s  Memory: 1172.00M
+"polygons" in: sky130A_mr.drc:155
+    Polygons (raw): 458636 (flat)  313361 (hierarchical)
+    Elapsed: 0.370s  Memory: 1181.00M
+"polygons" in: sky130A_mr.drc:156
+    Polygons (raw): 299110 (flat)  253152 (hierarchical)
+    Elapsed: 0.330s  Memory: 1185.00M
+"polygons" in: sky130A_mr.drc:158
+    Polygons (raw): 73561 (flat)  43869 (hierarchical)
+    Elapsed: 0.220s  Memory: 1186.00M
+"polygons" in: sky130A_mr.drc:159
+    Polygons (raw): 40820 (flat)  40820 (hierarchical)
+    Elapsed: 0.030s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:161
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:163
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:164
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:165
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:166
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:167
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:168
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:169
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:170
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:171
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:172
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:173
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:174
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:175
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:176
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:177
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:178
+    Polygons (raw): 51480 (flat)  4 (hierarchical)
+    Elapsed: 0.020s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:179
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:180
+    Polygons (raw): 790579 (flat)  451 (hierarchical)
+    Elapsed: 0.160s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:181
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:182
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:183
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:184
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:185
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:186
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:187
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:188
+    Polygons (raw): 8 (flat)  7 (hierarchical)
+    Elapsed: 0.140s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:189
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:190
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:191
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:192
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:193
+    Polygons (raw): 46860 (flat)  1 (hierarchical)
+    Elapsed: 0.190s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:194
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:195
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:196
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:197
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:198
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:199
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:200
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:201
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:202
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:203
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:204
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:205
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:206
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:207
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:208
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:209
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:210
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:211
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:212
+    Polygons (raw): 5100 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:213
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:214
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:215
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+DRC section
+FEOL section
+START: 64/18 (dnwell)
+"width" in: sky130A_mr.drc:241
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1195.00M
+"output" in: sky130A_mr.drc:241
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1195.00M
+END: 64/18 (dnwell)
+"input" in: sky130A_mr.drc:245
+    Polygons (raw): 742460 (flat)  283 (hierarchical)
+    Elapsed: 0.260s  Memory: 1217.00M
+"input" in: sky130A_mr.drc:246
+    Polygons (raw): 741523 (flat)  287 (hierarchical)
+    Elapsed: 0.160s  Memory: 1217.00M
+"input" in: sky130A_mr.drc:247
+    Polygons (raw): 672683 (flat)  264 (hierarchical)
+    Elapsed: 0.170s  Memory: 1217.00M
+"input" in: sky130A_mr.drc:252
+    Polygons (raw): 750236 (flat)  337 (hierarchical)
+    Elapsed: 0.160s  Memory: 1217.00M
+START: 64/20 (nwell)
+"width" in: sky130A_mr.drc:256
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 11.620s  Memory: 1394.00M
+"output" in: sky130A_mr.drc:256
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1394.00M
+"space" in: sky130A_mr.drc:257
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.170s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:257
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"and" in: sky130A_mr.drc:258
+    Polygons (raw): 672683 (flat)  264 (hierarchical)
+    Elapsed: 25.590s  Memory: 2000.00M
+"merge" in: sky130A_mr.drc:258
+    Polygons (raw): 2446 (flat)  1514 (hierarchical)
+    Elapsed: 10.950s  Memory: 2000.00M
+"holes" in: sky130A_mr.drc:259
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 2000.00M
+"enclosing" in: sky130A_mr.drc:259
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:259
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 64/20 (nwell)
+START: 78/44 (hvtp)
+"width" in: sky130A_mr.drc:264
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 10.740s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:264
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:265
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.160s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:265
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 78/44 (hvtp)
+START: 18/20 (htvr)
+"width" in: sky130A_mr.drc:270
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.230s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:270
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"separation" in: sky130A_mr.drc:271
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:271
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"and" in: sky130A_mr.drc:272
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:272
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 18/20 (htvr)
+START: 25/44 (lvtn)
+"width" in: sky130A_mr.drc:277
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:277
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:278
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:278
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 25/44 (lvtn)
+START: 92/44 (ncm)
+"width" in: sky130A_mr.drc:283
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:283
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:284
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:284
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 92/44 (ncm)
+START: 65/20 (diff)
+"or" in: sky130A_mr.drc:289
+    Polygons (raw): 1394302 (flat)  3208 (hierarchical)
+    Elapsed: 3.030s  Memory: 1936.00M
+"rectangles" in: sky130A_mr.drc:290
+    Polygons (raw): 975440 (flat)  701 (hierarchical)
+    Elapsed: 2.460s  Memory: 1936.00M
+"width" in: sky130A_mr.drc:290
+    Edge pairs: 49926 (flat)  2 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"polygons" in: sky130A_mr.drc:290
+    Polygons (raw): 49926 (flat)  2 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"edges" in: sky130A_mr.drc:291
+    Edges: 199704 (flat)  8 (hierarchical)
+    Elapsed: 0.140s  Memory: 1936.00M
+"outside_part" in: sky130A_mr.drc:291
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.180s  Memory: 1936.00M
+"outside" in: sky130A_mr.drc:291
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.530s  Memory: 1936.00M
+"edges" in: sky130A_mr.drc:291
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1936.00M
+"not" in: sky130A_mr.drc:291
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:292
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"outside" in: sky130A_mr.drc:293
+    Polygons (raw): 1155216 (flat)  920 (hierarchical)
+    Elapsed: 1.130s  Memory: 1936.00M
+"width" in: sky130A_mr.drc:293
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.740s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:293
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 65/20 (diff)
+START: 65/44 (tap)
+"rectangles" in: sky130A_mr.drc:297
+    Polygons (raw): 239467 (flat)  19055 (hierarchical)
+    Elapsed: 0.660s  Memory: 1936.00M
+"width" in: sky130A_mr.drc:297
+    Edge pairs: 49926 (flat)  2 (hierarchical)
+    Elapsed: 0.020s  Memory: 1936.00M
+"polygons" in: sky130A_mr.drc:297
+    Polygons (raw): 49926 (flat)  2 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"edges" in: sky130A_mr.drc:298
+    Edges: 199704 (flat)  8 (hierarchical)
+    Elapsed: 0.140s  Memory: 1936.00M
+"outside_part" in: sky130A_mr.drc:298
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.160s  Memory: 1936.00M
+"outside" in: sky130A_mr.drc:298
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 1936.00M
+"edges" in: sky130A_mr.drc:298
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"not" in: sky130A_mr.drc:298
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:299
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1936.00M
+"not" in: sky130A_mr.drc:300
+    Polygons (raw): 142210 (flat)  29 (hierarchical)
+    Elapsed: 0.630s  Memory: 1936.00M
+"width" in: sky130A_mr.drc:300
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.360s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:300
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 65/44 (tap)
+"space" in: sky130A_mr.drc:303
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.020s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:303
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+START: 80/20 (tunm)
+"width" in: sky130A_mr.drc:307
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:307
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:308
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:308
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 80/20 (tunm)
+START: 66/20 (poly)
+"width" in: sky130A_mr.drc:313
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.810s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:313
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"not" in: sky130A_mr.drc:314
+    Polygons (raw): 1836359 (flat)  2935 (hierarchical)
+    Elapsed: 1.130s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:314
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.660s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:314
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+START: 86/20 (rpm)
+"width" in: sky130A_mr.drc:319
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:319
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:320
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:320
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 86/20 (rpm)
+START: 79/20 (urpm)
+"width" in: sky130A_mr.drc:325
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:325
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:326
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:326
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 79/20 (urpm)
+START: 95/20 (npc)
+"width" in: sky130A_mr.drc:331
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 7.610s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:331
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+"space" in: sky130A_mr.drc:332
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.620s  Memory: 1936.00M
+"output" in: sky130A_mr.drc:332
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1936.00M
+END: 95/20 (npc)
+START: 93/44 (nsdm)
+"outside" in: sky130A_mr.drc:337
+    Polygons (raw): 69931 (flat)  1538 (hierarchical)
+    Elapsed: 11.940s  Memory: 1945.00M
+"width" in: sky130A_mr.drc:337
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.710s  Memory: 1945.00M
+"output" in: sky130A_mr.drc:337
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1945.00M
+"not" in: sky130A_mr.drc:338
+    Polygons (raw): 741436 (flat)  279 (hierarchical)
+    Elapsed: 1.190s  Memory: 1945.00M
+"space" in: sky130A_mr.drc:338
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 12.730s  Memory: 1946.00M
+"output" in: sky130A_mr.drc:338
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1946.00M
+END: 93/44 (nsdm)
+START: 94/20 (psdm)
+"outside" in: sky130A_mr.drc:343
+    Polygons (raw): 68903 (flat)  1529 (hierarchical)
+    Elapsed: 14.210s  Memory: 1946.00M
+"width" in: sky130A_mr.drc:343
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.850s  Memory: 1946.00M
+"output" in: sky130A_mr.drc:343
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1946.00M
+"not" in: sky130A_mr.drc:344
+    Polygons (raw): 739987 (flat)  281 (hierarchical)
+    Elapsed: 1.100s  Memory: 1946.00M
+"space" in: sky130A_mr.drc:344
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 15.170s  Memory: 1952.00M
+"output" in: sky130A_mr.drc:344
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1952.00M
+END: 94/20 (psdm)
+START: 66/44 (licon)
+"not" in: sky130A_mr.drc:355
+    Polygons (raw): 4449380 (flat)  160290 (hierarchical)
+    Elapsed: 5.900s  Memory: 1952.00M
+"and" in: sky130A_mr.drc:356
+    Polygons (raw): 5934858 (flat)  8015 (hierarchical)
+    Elapsed: 11.830s  Memory: 1952.00M
+"interacting" in: sky130A_mr.drc:356
+    Polygons (raw): 5803983 (flat)  51545 (hierarchical)
+    Elapsed: 8.290s  Memory: 1952.00M
+"not" in: sky130A_mr.drc:357
+    Polygons (raw): 5074245 (flat)  9584 (hierarchical)
+    Elapsed: 1.720s  Memory: 1952.00M
+"non_rectangles" in: sky130A_mr.drc:358
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1952.00M
+"output" in: sky130A_mr.drc:358
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1952.00M
+"or" in: sky130A_mr.drc:359
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1952.00M
+"not" in: sky130A_mr.drc:359
+    Polygons (raw): 8813309 (flat)  9554 (hierarchical)
+    Elapsed: 0.010s  Memory: 1952.00M
+"edges" in: sky130A_mr.drc:359
+    Edges: 33521340 (flat)  38050 (hierarchical)
+    Elapsed: 4.320s  Memory: 1952.00M
+"without_length" in: sky130A_mr.drc:359
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 4.830s  Memory: 1954.00M
+"output" in: sky130A_mr.drc:359
+    Edges: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1954.00M
+"separation" in: sky130A_mr.drc:360
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 5.930s  Memory: 1957.00M
+"output" in: sky130A_mr.drc:360
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1957.00M
+"and" in: sky130A_mr.drc:361
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 3.470s  Memory: 1957.00M
+"output" in: sky130A_mr.drc:361
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1957.00M
+"interacting" in: sky130A_mr.drc:362
+    Polygons (raw): 1993809 (flat)  10435 (hierarchical)
+    Elapsed: 4.320s  Memory: 1957.00M
+"interacting" in: sky130A_mr.drc:362
+    Polygons (raw): 5803983 (flat)  51545 (hierarchical)
+    Elapsed: 7.780s  Memory: 1957.00M
+"and" in: sky130A_mr.drc:362
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 3.740s  Memory: 1957.00M
+"output" in: sky130A_mr.drc:362
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1957.00M
+END: 66/44 (licon)
+START: 89/44 (capm)
+"width" in: sky130A_mr.drc:367
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.250s  Memory: 1957.00M
+"output" in: sky130A_mr.drc:367
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1957.00M
+"space" in: sky130A_mr.drc:368
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1957.00M
+"output" in: sky130A_mr.drc:368
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1957.00M
+"interacting" in: sky130A_mr.drc:369
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 2.600s  Memory: 1976.00M
+"isolated" in: sky130A_mr.drc:369
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:369
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"interacting" in: sky130A_mr.drc:370
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.200s  Memory: 1976.00M
+"isolated" in: sky130A_mr.drc:370
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:370
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"and" in: sky130A_mr.drc:371
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:371
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:371
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:372
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.200s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:372
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:373
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:373
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"separation" in: sky130A_mr.drc:374
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:374
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"not_interacting" in: sky130A_mr.drc:375
+    Polygons (raw): 82416 (flat)  65866 (hierarchical)
+    Elapsed: 0.650s  Memory: 1976.00M
+"separation" in: sky130A_mr.drc:375
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.580s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:375
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+END: 89/44 (capm)
+START: 97/44 (cap2m)
+"width" in: sky130A_mr.drc:380
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:380
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"space" in: sky130A_mr.drc:381
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:381
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1976.00M
+"interacting" in: sky130A_mr.drc:382
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.810s  Memory: 1976.00M
+"isolated" in: sky130A_mr.drc:382
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:382
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"interacting" in: sky130A_mr.drc:383
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.180s  Memory: 1976.00M
+"isolated" in: sky130A_mr.drc:383
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:383
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"and" in: sky130A_mr.drc:384
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:384
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.180s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:385
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"enclosing" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:386
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"separation" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:387
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"not_interacting" in: sky130A_mr.drc:388
+    Polygons (raw): 20037 (flat)  13526 (hierarchical)
+    Elapsed: 0.410s  Memory: 1976.00M
+"separation" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.670s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:388
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
+"not" in: sky130A_mr.drc:688
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"width" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:689
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"space" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:690
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+END: 75/20 (hvi)
+START: 125/20 (hvntm)
+"not" in: sky130A_mr.drc:695
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"width" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:696
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"space" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+"output" in: sky130A_mr.drc:697
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1976.00M
+END: 125/20 (hvntm)
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 268.000s  Memory: 1936.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_feol_check.total b/mpw_precheck/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.log b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..1035300
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
+"polygons" in: met_min_ca_density.lydrc:35
+    Polygons (raw): 7864908 (flat)  487604 (hierarchical)
+    Elapsed: 0.540s  Memory: 1040.00M
+"polygons" in: met_min_ca_density.lydrc:36
+    Polygons (raw): 9197667 (flat)  481860 (hierarchical)
+    Elapsed: 0.430s  Memory: 1051.00M
+"polygons" in: met_min_ca_density.lydrc:38
+    Polygons (raw): 8214904 (flat)  2663370 (hierarchical)
+    Elapsed: 1.750s  Memory: 1118.00M
+"polygons" in: met_min_ca_density.lydrc:39
+    Polygons (raw): 1674104 (flat)  907533 (hierarchical)
+    Elapsed: 0.710s  Memory: 1134.00M
+"polygons" in: met_min_ca_density.lydrc:41
+    Polygons (raw): 3088123 (flat)  1273047 (hierarchical)
+    Elapsed: 0.980s  Memory: 1164.00M
+"polygons" in: met_min_ca_density.lydrc:42
+    Polygons (raw): 363409 (flat)  302120 (hierarchical)
+    Elapsed: 0.370s  Memory: 1168.00M
+"polygons" in: met_min_ca_density.lydrc:44
+    Polygons (raw): 458637 (flat)  313362 (hierarchical)
+    Elapsed: 0.390s  Memory: 1176.00M
+"polygons" in: met_min_ca_density.lydrc:45
+    Polygons (raw): 299110 (flat)  253152 (hierarchical)
+    Elapsed: 0.350s  Memory: 1181.00M
+"polygons" in: met_min_ca_density.lydrc:47
+    Polygons (raw): 73573 (flat)  43881 (hierarchical)
+    Elapsed: 0.230s  Memory: 1182.00M
+"polygons" in: met_min_ca_density.lydrc:48
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1182.00M
+"polygons" in: met_min_ca_density.lydrc:49
+    Polygons (raw): 40820 (flat)  40820 (hierarchical)
+    Elapsed: 0.030s  Memory: 1184.00M
+"polygons" in: met_min_ca_density.lydrc:51
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1184.00M
+"input" in: met_min_ca_density.lydrc:53
+    Polygons (raw): 172748 (flat)  213 (hierarchical)
+    Elapsed: 0.210s  Memory: 1184.00M
+"area" in: met_min_ca_density.lydrc:55
+    Elapsed: 3.740s  Memory: 1201.00M
+"polygons" in: met_min_ca_density.lydrc:59
+    Polygons (raw): 7864908 (flat)  487604 (hierarchical)
+    Elapsed: 0.460s  Memory: 1205.00M
+"area" in: met_min_ca_density.lydrc:59
+    Elapsed: 48.910s  Memory: 1825.00M
+li1_ca_density is 0.7315589107837795
+"polygons" in: met_min_ca_density.lydrc:69
+    Polygons (raw): 8214904 (flat)  2663370 (hierarchical)
+    Elapsed: 1.800s  Memory: 1825.00M
+"area" in: met_min_ca_density.lydrc:69
+    Elapsed: 49.780s  Memory: 1825.00M
+m1_ca_density is 0.8335813509422673
+"polygons" in: met_min_ca_density.lydrc:79
+    Polygons (raw): 3088123 (flat)  1273047 (hierarchical)
+    Elapsed: 1.010s  Memory: 1825.00M
+"area" in: met_min_ca_density.lydrc:79
+    Elapsed: 9.640s  Memory: 1903.00M
+m2_ca_density is 0.9041730878784636
+"polygons" in: met_min_ca_density.lydrc:89
+    Polygons (raw): 458637 (flat)  313362 (hierarchical)
+    Elapsed: 0.410s  Memory: 1903.00M
+"area" in: met_min_ca_density.lydrc:89
+    Elapsed: 2.670s  Memory: 1903.00M
+m3_ca_density is 0.955298445098459
+"polygons" in: met_min_ca_density.lydrc:99
+    Polygons (raw): 73573 (flat)  43881 (hierarchical)
+    Elapsed: 0.240s  Memory: 1903.00M
+"area" in: met_min_ca_density.lydrc:99
+    Elapsed: 0.740s  Memory: 1903.00M
+m4_ca_density is 0.7447811334789461
+"polygons" in: met_min_ca_density.lydrc:109
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1903.00M
+"area" in: met_min_ca_density.lydrc:109
+    Elapsed: 0.330s  Memory: 1903.00M
+m5_ca_density is 0.668242188667497
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 133.600s  Memory: 1785.00M
diff --git a/mpw_precheck/logs/klayout_met_min_ca_density_check.total b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_offgrid_check.log b/mpw_precheck/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..b985bd0
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.log
@@ -0,0 +1,765 @@
+/opt/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::FEOL
+/opt/checks/tech-files/sky130A_mr.drc:40: warning: previous definition of FEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::BEOL
+/opt/checks/tech-files/sky130A_mr.drc:41: warning: previous definition of BEOL was here
+/opt/checks/tech-files/sky130A_mr.drc:60: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/opt/checks/tech-files/sky130A_mr.drc:42: warning: previous definition of OFFGRID was here
+/opt/checks/tech-files/sky130A_mr.drc:68: warning: already initialized constant DRC::DRCEngine::SEAL
+/opt/checks/tech-files/sky130A_mr.drc:43: warning: previous definition of SEAL was here
+/opt/checks/tech-files/sky130A_mr.drc:74: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/opt/checks/tech-files/sky130A_mr.drc:44: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:124
+    Polygons (raw): 1605360 (flat)  968 (hierarchical)
+    Elapsed: 0.270s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:125
+    Polygons (raw): 293536 (flat)  37 (hierarchical)
+    Elapsed: 0.210s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:126
+    Polygons (raw): 750236 (flat)  337 (hierarchical)
+    Elapsed: 0.170s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:127
+    Polygons (raw): 3 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:128
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:129
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:130
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:131
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:132
+    Polygons (raw): 743584 (flat)  268 (hierarchical)
+    Elapsed: 0.160s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:133
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:135
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:137
+    Polygons (raw): 2663013 (flat)  3005 (hierarchical)
+    Elapsed: 0.190s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:138
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1032.00M
+"polygons" in: sky130A_mr.drc:139
+    Polygons (raw): 1023725 (flat)  389 (hierarchical)
+    Elapsed: 0.160s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:140
+    Polygons (raw): 920152 (flat)  382 (hierarchical)
+    Elapsed: 0.160s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:141
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:142
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:143
+    Polygons (raw): 805756 (flat)  392 (hierarchical)
+    Elapsed: 0.180s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:144
+    Polygons (raw): 8813309 (flat)  9554 (hierarchical)
+    Elapsed: 0.170s  Memory: 1033.00M
+"polygons" in: sky130A_mr.drc:146
+    Polygons (raw): 6213128 (flat)  485316 (hierarchical)
+    Elapsed: 0.440s  Memory: 1045.00M
+"polygons" in: sky130A_mr.drc:147
+    Polygons (raw): 9197667 (flat)  481860 (hierarchical)
+    Elapsed: 0.420s  Memory: 1056.00M
+"polygons" in: sky130A_mr.drc:149
+    Polygons (raw): 6544380 (flat)  2662817 (hierarchical)
+    Elapsed: 1.770s  Memory: 1122.00M
+"polygons" in: sky130A_mr.drc:150
+    Polygons (raw): 1674104 (flat)  907533 (hierarchical)
+    Elapsed: 0.710s  Memory: 1138.00M
+"polygons" in: sky130A_mr.drc:152
+    Polygons (raw): 2881387 (flat)  1272994 (hierarchical)
+    Elapsed: 0.980s  Memory: 1168.00M
+"polygons" in: sky130A_mr.drc:153
+    Polygons (raw): 363409 (flat)  302120 (hierarchical)
+    Elapsed: 0.380s  Memory: 1172.00M
+"polygons" in: sky130A_mr.drc:155
+    Polygons (raw): 458636 (flat)  313361 (hierarchical)
+    Elapsed: 0.380s  Memory: 1181.00M
+"polygons" in: sky130A_mr.drc:156
+    Polygons (raw): 299110 (flat)  253152 (hierarchical)
+    Elapsed: 0.340s  Memory: 1185.00M
+"polygons" in: sky130A_mr.drc:158
+    Polygons (raw): 73561 (flat)  43869 (hierarchical)
+    Elapsed: 0.220s  Memory: 1186.00M
+"polygons" in: sky130A_mr.drc:159
+    Polygons (raw): 40820 (flat)  40820 (hierarchical)
+    Elapsed: 0.030s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:161
+    Polygons (raw): 191 (flat)  191 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:163
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:164
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:165
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:166
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:167
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:168
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:169
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:170
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:171
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:172
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:173
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:174
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:175
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:176
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:177
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:178
+    Polygons (raw): 51480 (flat)  4 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:179
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1188.00M
+"polygons" in: sky130A_mr.drc:180
+    Polygons (raw): 790579 (flat)  451 (hierarchical)
+    Elapsed: 0.160s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:181
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:182
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:183
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:184
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:185
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:186
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:187
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:188
+    Polygons (raw): 8 (flat)  7 (hierarchical)
+    Elapsed: 0.150s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:189
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:190
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:191
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:192
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:193
+    Polygons (raw): 46860 (flat)  1 (hierarchical)
+    Elapsed: 0.190s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:194
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:195
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:196
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:197
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:198
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:199
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:200
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:201
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:202
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:203
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:204
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:205
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:206
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:207
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:208
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:209
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:210
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:211
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:212
+    Polygons (raw): 5100 (flat)  5 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:213
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:214
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+"polygons" in: sky130A_mr.drc:215
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1189.00M
+DRC section
+OFFGRID-ANGLES section
+"ongrid" in: sky130A_mr.drc:706
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.410s  Memory: 1195.00M
+"output" in: sky130A_mr.drc:706
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1195.00M
+"with_angle" in: sky130A_mr.drc:707
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1195.00M
+"output" in: sky130A_mr.drc:707
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1195.00M
+"ongrid" in: sky130A_mr.drc:708
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 12.100s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:708
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:709
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:709
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:710
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:710
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:711
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:711
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:712
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:712
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:713
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:713
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:714
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 11.130s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:714
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:715
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:715
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:716
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.430s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:716
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:717
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:717
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:718
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:718
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:719
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:719
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:720
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.420s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:720
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:721
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:721
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:722
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.820s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:722
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:723
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 1.030s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:723
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:724
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"not" in: sky130A_mr.drc:724
+    Polygons (raw): 1605360 (flat)  968 (hierarchical)
+    Elapsed: 0.020s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:724
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:724
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:725
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:725
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:725
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.250s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:725
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:726
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"not" in: sky130A_mr.drc:726
+    Polygons (raw): 293536 (flat)  37 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:726
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:726
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:727
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"and" in: sky130A_mr.drc:727
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:727
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:727
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:728
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.430s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:728
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:729
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:729
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:730
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.550s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:730
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:731
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.050s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:731
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:732
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.430s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:732
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:733
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:733
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:734
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 7.380s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:734
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"with_angle" in: sky130A_mr.drc:735
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.270s  Memory: 1367.00M
+"output" in: sky130A_mr.drc:735
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1367.00M
+"ongrid" in: sky130A_mr.drc:736
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 12.730s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:736
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"with_angle" in: sky130A_mr.drc:737
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:737
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"ongrid" in: sky130A_mr.drc:738
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 13.940s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:738
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"with_angle" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.100s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:739
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"ongrid" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.400s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:740
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"with_angle" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.070s  Memory: 1388.00M
+"output" in: sky130A_mr.drc:741
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1388.00M
+"ongrid" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 49.230s  Memory: 1839.00M
+"output" in: sky130A_mr.drc:742
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1839.00M
+"with_angle" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 1839.00M
+"output" in: sky130A_mr.drc:743
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1839.00M
+"ongrid" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 75.850s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:744
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.270s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:745
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:746
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:747
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 50.980s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:748
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.680s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:749
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 8.610s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:750
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.840s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:751
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 10.370s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:752
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.460s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:753
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 3.170s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:754
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.280s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:755
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.920s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:756
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.080s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:757
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 2.740s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:758
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.240s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:759
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:760
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:761
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.890s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:762
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.030s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:763
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.820s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:764
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.040s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:765
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.450s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:766
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:767
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:768
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:769
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:770
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:771
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:772
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:773
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:774
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:775
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:776
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:777
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.440s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:778
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:779
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.430s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:780
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"with_angle" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:781
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+"ongrid" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.450s  Memory: 3246.00M
+"output" in: sky130A_mr.drc:782
+    Edge pairs: 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 3246.00M
+Writing report database: /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 323.710s  Memory: 2593.00M
+ 
+Cell exclusion list:
+   rule    | cell
+   nwell.6 | sky130_fd_io__gpiov2_amux, sky130_fd_io__simple_pad_and_busses, sram
+   nsd.1   | sram
+   nsd.2   | sram
+   psd.1   | sram
+   psd.2   | sram
+ 
+release 2022.6.30_01.07
diff --git a/mpw_precheck/logs/klayout_offgrid_check.total b/mpw_precheck/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..9ecaebe
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/root/riscduino-dcore_d4_/gds/user_project_wrapper.gds, topcell=user_project_wrapper, output to /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+  deep:true tiled:false threads:8
+--- #err|description, table for cell: user_project_wrapper
+NO-Check ----        pwell:64/44/EMP   122/16/dat    64/59/EMP    44/16/EMP     44/5/EMP
+         ----        nwell:64/20/dat    64/16/dat     64/5/EMP
+         ----         diff:65/20/dat    65/16/EMP     65/6/EMP
+         ----          tap:65/44/dat    65/48/EMP     65/5/EMP
+         ----         poly:66/20/dat    66/16/EMP     66/5/EMP
+         ----       licon1:66/44/dat    66/58/EMP
+         ----          li1:67/20/dat    67/16/dat     67/5/dat
+         ----         mcon:67/44/dat    67/48/EMP
+         ----         met1:68/20/dat    68/16/dat     68/5/dat
+         ----          via:68/44/dat    68/58/EMP
+         ----         met2:69/20/dat    69/16/dat     69/5/dat
+         ----         via2:69/44/dat    69/58/EMP
+         ----         met3:70/20/dat    70/16/dat     70/5/dat
+         ----         via3:70/44/dat    70/48/EMP
+         ----         met4:71/20/dat    71/16/dat     71/5/dat
+         ----         via4:71/44/dat    71/48/EMP
+         ----         met5:72/20/dat    72/16/EMP     72/5/dat
+         ----          pad:76/20/EMP     76/5/EMP    76/16/EMP
+         ----          pnp:82/44/EMP    82/59/EMP
+         ----          npn:82/20/EMP     82/5/EMP
+         ----          rdl:74/20/EMP    74/16/EMP     74/5/EMP
+         ----     inductor:82/24/EMP    82/25/EMP
+       0 total error(s) among 0 error type(s), 33 checks, cell: user_project_wrapper
+Writing report...
+VmPeak:	 2687840 kB
+VmHWM:	 1528132 kB
diff --git a/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.log b/mpw_precheck/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..aab8c14
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.log
@@ -0,0 +1,6 @@
+writing to /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper_no_zero_areas.gds
+0 zero-area shapes
+0 zero-length paths,  0 zero-length paths deleted.
+0 total zero-area objects,  0 total objects deleted.
+VmPeak:	 2134952 kB
+VmHWM:	 1759048 kB
diff --git a/mpw_precheck/logs/klayout_zeroarea_check.total b/mpw_precheck/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/magic_drc_check.log b/mpw_precheck/logs/magic_drc_check.log
new file mode 100644
index 0000000..962e6c8
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.log
@@ -0,0 +1,621 @@
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Error parsing "/opt/checks/tech-files/sky130A.magicrc": can't read "::env(PDK_PATH)": no such variable
+Bad local startup file "/opt/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/opt/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Detected an SRAM module
+Pre-loading a maglef of the SRAM block: sky130_sram_2kbyte_1rw1r_32x512_8
+Cell sky130_sram_2kbyte_1rw1r_32x512_8 has technology "sky130A", but current technology is "minimum"
+Loading technology sky130A
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Cell path is now "$CAD_ROOT/magic/sys/current $CAD_ROOT/magic/tutorial /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_io/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_pr/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hd/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_fd_sc_hvl/maglef /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_ml_xx_hd/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/mag /opt/pdks/volare/sky130/versions/0059588eebfc704681dc2368bd1d33d96281d10f/sky130A/libs.ref/sky130_sram_macros/maglef"
+Scaled magic input cell sky130_sram_2kbyte_1rw1r_32x512_8 geometry by factor of 2
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "ycr2_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__o32ai_2".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "aes_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182721350): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182722054): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182723014): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183215260): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183219036): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183223228): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183228028): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183230076): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183409518): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183413294): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183417486): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183423950): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183426126): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183666576): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183670352): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183674544): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183681008): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183683184): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+Warning:  cell sky130_sram_2kbyte_1rw1r_32x512_8 already existed before reading GDS!
+Using pre-existing cell definition
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "fpu_wrapper".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__dlclkp_2".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__dlxtn_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "user_project_wrapper".
+[INFO]: Loading user_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/mpw_precheck/logs/magic_drc_check.total b/mpw_precheck/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/logs/pdks.info b/mpw_precheck/logs/pdks.info
new file mode 100644
index 0000000..f65aecb
--- /dev/null
+++ b/mpw_precheck/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs 0059588eebfc704681dc2368bd1d33d96281d10f
+SKY130A PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/mpw_precheck/logs/precheck.log b/mpw_precheck/logs/precheck.log
new file mode 100644
index 0000000..aeb0bb1
--- /dev/null
+++ b/mpw_precheck/logs/precheck.log
@@ -0,0 +1,78 @@
+2022-12-03 15:29:55 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_dcore.git | Branch: main | Commit: ddec3fbfabd8cef36812a3f9e833e94adfc47f23
+2022-12-03 15:29:55 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-dcore_d4_
+2022-12-03 15:29:58 - [INFO] - {{Project Type Info}} digital
+2022-12-03 15:29:59 - [INFO] - {{Project GDS Info}} user_project_wrapper: 6827dd3ff4694632747e41f2c2ffe4f5e28f5dbf
+2022-12-03 15:29:59 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
+2022-12-03 15:29:59 - [INFO] - {{PDKs Info}} SKY130A: f70d8ca46961ff92719d8870a18a076370b85f6c | Open PDKs: 0059588eebfc704681dc2368bd1d33d96281d10f
+2022-12-03 15:29:59 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs'
+2022-12-03 15:29:59 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-12-03 15:29:59 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
+2022-12-03 15:30:00 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d4_.
+2022-12-03 15:30:00 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-12-03 15:30:01 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dcore_d4_.
+2022-12-03 15:30:01 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-12-03 15:30:01 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
+2022-12-03 15:30:01 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dcore_d4_/verilog/dv/common/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
+2022-12-03 15:30:01 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 422 non-compliant file(s) with the SPDX Standard.
+2022-12-03 15:30:01 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-dcore_d4_/run_regress', 'riscduino-dcore_d4_/deps/timing-scripts/timing.mk', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/common.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/f.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/s.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/env/t.tcl', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/compare_reports.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/generate_spef_mapping.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/get_macros.py', 'riscduino-dcore_d4_/deps/timing-scripts/scripts/pdk_helpers.py']
+2022-12-03 15:30:01 - [INFO] - For the full SPDX compliance report check: riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/spdx_compliance_report.log
+2022-12-03 15:30:01 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Makefile
+2022-12-03 15:30:01 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-12-03 15:30:01 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Default
+2022-12-03 15:30:01 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-12-03 15:30:02 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-12-03 15:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Documentation
+2022-12-03 15:30:02 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-12-03 15:30:02 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Consistency
+2022-12-03 15:30:11 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
+2022-12-03 15:30:11 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
+2022-12-03 15:30:11 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
+2022-12-03 15:30:11 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (16 instances). 
+2022-12-03 15:30:11 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
+2022-12-03 15:30:11 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
+2022-12-03 15:30:11 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
+2022-12-03 15:30:11 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
+2022-12-03 15:30:11 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
+2022-12-03 15:30:11 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-12-03 15:30:11 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: GPIO-Defines
+2022-12-03 15:30:11 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'riscduino-dcore_d4_/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
+2022-12-03 15:30:13 - [INFO] - GPIO-DEFINES report path: riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/gpio_defines.report
+2022-12-03 15:30:13 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
+2022-12-03 15:30:13 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
+2022-12-03 15:34:16 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper.xor.gds
+2022-12-03 15:34:16 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
+2022-12-03 15:34:16 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
+2022-12-03 16:12:51 - [INFO] - 0 DRC violations
+2022-12-03 16:12:51 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:12:51 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
+2022-12-03 16:12:51 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:12:51 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_feol_check.xml -rd feol=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_feol_check.log
+2022-12-03 16:16:24 - [INFO] - No DRC Violations found
+2022-12-03 16:16:24 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:16:24 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
+2022-12-03 16:16:24 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:16:24 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_beol_check.xml -rd beol=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_beol_check.log
+2022-12-03 16:44:17 - [INFO] - No DRC Violations found
+2022-12-03 16:44:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:44:17 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
+2022-12-03 16:44:17 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:44:17 - [INFO] - run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_offgrid_check.log
+2022-12-03 16:49:42 - [INFO] - No DRC Violations found
+2022-12-03 16:49:42 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:49:42 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
+2022-12-03 16:49:42 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:49:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_met_min_ca_density_check.xml >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_met_min_ca_density_check.log
+2022-12-03 16:51:57 - [INFO] - No DRC Violations found
+2022-12-03 16:51:57 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:51:57 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
+2022-12-03 16:51:57 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:51:58 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd top_cell_name=user_project_wrapper >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
+2022-12-03 16:52:42 - [INFO] - No DRC Violations found
+2022-12-03 16:52:42 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:52:42 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
+2022-12-03 16:52:42 - [INFO] - in CUSTOM klayout_gds_drc_check
+2022-12-03 16:52:42 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=riscduino-dcore_d4_/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/reports/klayout_zeroarea_check.xml -rd cleaned_output=riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper_no_zero_areas.gds >& riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs/klayout_zeroarea_check.log
+2022-12-03 16:53:08 - [INFO] - No DRC Violations found
+2022-12-03 16:53:08 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
+2022-12-03 16:53:08 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/logs'
+2022-12-03 16:53:08 - [INFO] - {{SUCCESS}} All Checks Passed !!!
diff --git a/mpw_precheck/logs/spdx_compliance_report.log b/mpw_precheck/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..6d18fad
--- /dev/null
+++ b/mpw_precheck/logs/spdx_compliance_report.log
@@ -0,0 +1,422 @@
+/root/riscduino-dcore_d4_/run_regress
+/root/riscduino-dcore_d4_/deps/timing-scripts/timing.mk
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2-calibre.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw2.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw5-calibre.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping-mpw7.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/caravel_spef_mapping.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/common.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/f.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/s.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/env/t.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/compare_reports.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/generate_spef_mapping.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/get_macros.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/pdk_helpers.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/report.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/summarize_report.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/timing_path.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/verilog_parser.py
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/openroad/rcx.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/openroad/sdf.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/openroad/sta-gpio_control_block.tcl
+/root/riscduino-dcore_d4_/deps/timing-scripts/scripts/openroad/timing_top.tcl
+/root/riscduino-dcore_d4_/hacks/patch/pdngen.patch
+/root/riscduino-dcore_d4_/hacks/patch/resizer.patch
+/root/riscduino-dcore_d4_/hacks/src/OpenROAD/PdnGen.tcl
+/root/riscduino-dcore_d4_/hacks/src/OpenROAD/Resizer.cc
+/root/riscduino-dcore_d4_/hacks/src/OpenSTA/network/ConcreteNetwork.cc
+/root/riscduino-dcore_d4_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl
+/root/riscduino-dcore_d4_/hacks/src/OpenSTA/tcl/Sta.tcl
+/root/riscduino-dcore_d4_/hacks/src/openlane/io_place.py
+/root/riscduino-dcore_d4_/hacks/src/openlane/synth.tcl
+/root/riscduino-dcore_d4_/hacks/src/openlane/synth_top.tcl
+/root/riscduino-dcore_d4_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-dcore_d4_/openlane/dg_pll/base.sdc
+/root/riscduino-dcore_d4_/openlane/dg_pll/interactive.tcl
+/root/riscduino-dcore_d4_/openlane/pinmux_top/base.sdc
+/root/riscduino-dcore_d4_/openlane/qspim_top/base.sdc
+/root/riscduino-dcore_d4_/openlane/sar_adc/pdn.tcl
+/root/riscduino-dcore_d4_/openlane/uart_i2c_usb_spi_top/base.sdc
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/base.sdc
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/interactive.tcl
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/pdn.tcl
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/pdn_cfg.tcl
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl
+/root/riscduino-dcore_d4_/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl
+/root/riscduino-dcore_d4_/openlane/wb_host/base.sdc
+/root/riscduino-dcore_d4_/openlane/wb_interconnect/base.sdc
+/root/riscduino-dcore_d4_/openlane/ycr2_iconnect/base.sdc
+/root/riscduino-dcore_d4_/openlane/ycr2_iconnect/drc_exclude.cells
+/root/riscduino-dcore_d4_/openlane/ycr_core_top/base.sdc
+/root/riscduino-dcore_d4_/openlane/ycr_intf/base.sdc
+/root/riscduino-dcore_d4_/sta/base.sdc
+/root/riscduino-dcore_d4_/sta/run_sta
+/root/riscduino-dcore_d4_/sta/scripts/caravel_timing.tcl
+/root/riscduino-dcore_d4_/sta/scripts/or_write_verilog.tcl
+/root/riscduino-dcore_d4_/sta/scripts/qspim_timing.tcl
+/root/riscduino-dcore_d4_/sta/scripts/riscdunio.tcl
+/root/riscduino-dcore_d4_/sta/scripts/statistic.tcl
+/root/riscduino-dcore_d4_/sta/scripts/uart_i2c_usb_spi_timing.tcl
+/root/riscduino-dcore_d4_/sta/scripts/ycr2_iconnect_timing.tcl
+/root/riscduino-dcore_d4_/sta/scripts/ycr_core_timing.tcl
+/root/riscduino-dcore_d4_/sta/sdc/caravel.sdc
+/root/riscduino-dcore_d4_/sta/sdc/qspim_top.sdc
+/root/riscduino-dcore_d4_/sta/sdc/uart_i2c_usb_spi_top.sdc
+/root/riscduino-dcore_d4_/sta/sdc/ycr2_iconnect.sdc
+/root/riscduino-dcore_d4_/sta/sdc/ycr_core_top.sdc
+/root/riscduino-dcore_d4_/verilog/dv/arduino_arrays/arduino_arrays.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_hello_world/arduino_hello_world.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_hello_world/arduino_hello_world.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_string/arduino_string.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_string/arduino_string.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/arduino_ws281x/arduino_ws281x.ino
+/root/riscduino-dcore_d4_/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/agents/caravel_task.sv
+/root/riscduino-dcore_d4_/verilog/dv/common/agents/test_control.v
+/root/riscduino-dcore_d4_/verilog/dv/common/agents/uart_master_tasks.sv
+/root/riscduino-dcore_d4_/verilog/dv/common/agents/usb_agents.v
+/root/riscduino-dcore_d4_/verilog/dv/common/agents/user_tasks.sv
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/bfm_ad5205.sv
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/bfm_spim.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/bfm_ws281x.sv
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb1d_defines.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usbd_files.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_core.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_crc16.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_crc5.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_fifo2.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_generic_dpram.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_generic_fifo.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_idma.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_pa.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_pd.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_pe.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_pl.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_rom1.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_sync_fifo.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/core/usb1d_utmi_if.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/phy/usb1d_phy.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/phy/usb1d_rx_phy.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/phy/usb1d_tx_phy.v
+/root/riscduino-dcore_d4_/verilog/dv/common/bfm/usb_device/top/usb1d_top.v
+/root/riscduino-dcore_d4_/verilog/dv/common/firmware/common_bthread.c
+/root/riscduino-dcore_d4_/verilog/dv/common/firmware/common_bthread.h
+/root/riscduino-dcore_d4_/verilog/dv/common/firmware/common_misc.h
+/root/riscduino-dcore_d4_/verilog/dv/common/firmware/ext_reg_map.h
+/root/riscduino-dcore_d4_/verilog/dv/common/firmware/int_reg_map.h
+/root/riscduino-dcore_d4_/verilog/dv/common/model/is62wvs1288.v
+/root/riscduino-dcore_d4_/verilog/dv/common/model/spiram.v
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/package_riscduino_index.json
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/CHANGELOG
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/installed.json
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Arduino.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/HardwareSerial.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Printable.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WCharacter.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/abi.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/binary.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/entry.S
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/hooks.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/init.S
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/itoa.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/itoa.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/main.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/malloc.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/new.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/sbrk.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/start.S
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_analog.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_analog.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_constants.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_digital.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_digital.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_private.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_pulse.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_pulse.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_shift.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/wiring_shift.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/avr/pgmspace.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/drivers/fe300prci/fe300prci_driver.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/drivers/fe300prci/fe300prci_driver.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/drivers/plic/plic_driver.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/drivers/plic/plic_driver.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/SPI/library.properties
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/SPI/src/SPI.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/SPI/src/SPI.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/WS281X/library.properties
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/WS281X/example/wx281x_exp1/wx281x_exp1.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/WS281X/src/WS281X.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/WS281X/src/WS281X.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/library.properties
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/master_reader/master_reader.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/master_wr_rd/master_wr_rd.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/master_writer/master_writer.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/slave_receiver/slave_receiver.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/examples/slave_sender/slave_sender.ino
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/src/Wire.cpp
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/src/Wire.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/src/utility/twi.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/libraries/Wire/src/utility/twi.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/drivers/fe300prci/fe300prci_driver.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/drivers/fe300prci/fe300prci_driver.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/drivers/plic/plic_driver.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/drivers/plic/plic_driver.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/common.mk
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/encoding.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/entry.S
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/riscduino.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/start.S
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/riscduino_score/init.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/riscduino_score/link.lds
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/env/riscduino_score/platform.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/bits.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/const.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/sections.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/aon.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/clint.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/glbl.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/gpio.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/otp.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/plic.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/prci.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/pwm.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/spi.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/timer.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/uart.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/wire.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/include/riscduino/devices/ws281x.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/libwrap.mk
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/misc/write_hex.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/stdlib/malloc.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/_exit.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/close.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/execve.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/fork.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/fstat.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/getpid.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/isatty.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/kill.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/link.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/lseek.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/open.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/openat.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/read.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/sbrk.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/stat.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/stub.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/times.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/unlink.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/wait.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/libwrap/sys/write.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/bsp/tools/openocd_upload.sh
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/coremark/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/coremark/core_portme.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/coremark/core_portme.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/demo_gpio/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/demo_gpio/demo_gpio.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_1.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_2.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_printf.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/dhrystone/dhry_stubs.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/double_tap_dontboot/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/double_tap_dontboot/double_tap_dontboot.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/hello/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/hello/hello.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/led_fade/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/sdk/software/led_fade/led_fade.c
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/_fpmath.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/_limits.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/_types.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/asm.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/atomic.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/endian.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/riscv/io.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/system/include/sys/isr.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/variants/standard/pins_arduino.h
+/root/riscduino-dcore_d4_/verilog/dv/common/riscduino_board/custom_board/riscduino/variants/standard/variant.h
+/root/riscduino-dcore_d4_/verilog/dv/common/vpi/system/system.c
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/riscv_runtests.sv
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/run_iverilog
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/hello/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/hello/hello.c
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/isr_sample/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/isr_sample/timer.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_isa/Makefile
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc
+/root/riscduino-dcore_d4_/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h
+/root/riscduino-dcore_d4_/verilog/dv/user_aes/aes.c
+/root/riscduino-dcore_d4_/verilog/dv/user_aes/aes.h
+/root/riscduino-dcore_d4_/verilog/dv/user_sspi/sspi_task.v
+/root/riscduino-dcore_d4_/verilog/dv/user_usb/tests/usb_test1.v
+/root/riscduino-dcore_d4_/verilog/dv/user_usb/tests/usb_test2.v
+/root/riscduino-dcore_d4_/verilog/dv/user_usb/tests/usb_test3.v
+/root/riscduino-dcore_d4_/verilog/includes/includes.gl.caravel_user_project
+/root/riscduino-dcore_d4_/verilog/includes/includes.gl.lib
+/root/riscduino-dcore_d4_/verilog/includes/includes.rtl.caravel_user_project
+/root/riscduino-dcore_d4_/verilog/includes/includes.rtl.lib
+/root/riscduino-dcore_d4_/verilog/rtl/user_params.svh
+/root/riscduino-dcore_d4_/verilog/rtl/user_reg_map.v
+/root/riscduino-dcore_d4_/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
+/root/riscduino-dcore_d4_/verilog/rtl/dac/src/dac_top.v
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/openlane/fpu_sp_top/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/openlane/fpu_top/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/synth/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/synth/scripts/libtrim.pl
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/filelist_gate.f
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/filelist_rtl.f
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/fpu_sp.c
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/fpu_sp_tc.c
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/tb_top.sv
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/dv/test_fpu_sp.sv
+/root/riscduino-dcore_d4_/verilog/rtl/fpu/verilog/rtl/fpu_parms.v
+/root/riscduino-dcore_d4_/verilog/rtl/gpio/src/gpio_intr.sv
+/root/riscduino-dcore_d4_/verilog/rtl/lib/ctech_cells.sv
+/root/riscduino-dcore_d4_/verilog/rtl/lib/pulse_gen_type1.sv
+/root/riscduino-dcore_d4_/verilog/rtl/lib/pulse_gen_type2.sv
+/root/riscduino-dcore_d4_/verilog/rtl/mbist/run_iverilog
+/root/riscduino-dcore_d4_/verilog/rtl/mbist/run_verilator
+/root/riscduino-dcore_d4_/verilog/rtl/pwm/src/pwm.sv
+/root/riscduino-dcore_d4_/verilog/rtl/pwm/src/pwm_cfg_dglitch.sv
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/lib/ctech_cells.sv
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/model/cy15b104qs.v
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/model/s25fl256s.sv
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/model/spiram.v
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/openlane/qspim_top/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/openlane/qspim_top/interactive.tcl
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/sdc/qspim_top.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/qspim/tb/run_iverilog
+/root/riscduino-dcore_d4_/verilog/rtl/sar_adc/ACMP.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sar_adc/ACMP_HVL.v
+/root/riscduino-dcore_d4_/verilog/rtl/sar_adc/DAC_8BIT.v
+/root/riscduino-dcore_d4_/verilog/rtl/sar_adc/SAR.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sar_adc/sar_adc.sv
+/root/riscduino-dcore_d4_/verilog/rtl/security_core/openlane/aes_top/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/security_core/openlane/aes_top/interactive.tcl
+/root/riscduino-dcore_d4_/verilog/rtl/security_core/verilog/dv/user_aes/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/security_core/verilog/includes/includes.rtl
+/root/riscduino-dcore_d4_/verilog/rtl/security_core/verilog/rtl/lib/ctech_cells.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-dcore_d4_/verilog/rtl/sspim/src/filelist_spi.f
+/root/riscduino-dcore_d4_/verilog/rtl/sspim/src/sspim_cfg.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sspim/src/sspim_clkgen.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sspim/src/sspim_ctl.sv
+/root/riscduino-dcore_d4_/verilog/rtl/sspim/src/sspim_if.sv
+/root/riscduino-dcore_d4_/verilog/rtl/timer/src/timer.sv
+/root/riscduino-dcore_d4_/verilog/rtl/uart2wb/src/run_verilog
+/root/riscduino-dcore_d4_/verilog/rtl/uart2wb/src/uart_auto_det.sv
+/root/riscduino-dcore_d4_/verilog/rtl/uart2wb/src/uart_msg_handler.v
+/root/riscduino-dcore_d4_/verilog/rtl/usb1_host/src/filelist.f
+/root/riscduino-dcore_d4_/verilog/rtl/ws281x/src/ws281x_driver.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/run_iverilog
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/openlane/ycr2_core/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/openlane/ycr2_intf/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/openlane/ycr2c/base.sdc
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/iverilog_vpi/system.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/coremark/core_portme.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_1.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/benchmarks/dhrystone21/dhry_2.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/hello/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/hello/hello.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/isr_sample.S
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/isr_sample/timer.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/aw_test_macros.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_io.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/compliance_test.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/riscv_test_macros.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_compliance/test_macros.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/Makefile
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/riscv_test.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/rv32_tests.inc
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/tests/riscv_isa/test_macros.h
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_ahb_wrapper.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_axi_wrapper.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/sim/verilator_wrap/ycr_wb_wrapper.c
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/core.files
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/wb_top.files
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/cache/src/core/ycr_cache_defs.svh
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/includes/ycr_cache_defs.svh
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ahb_tb.files
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/axi_tb.files
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/uprj_netlists.v
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/wb_tb.files
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_ahb.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_axi.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_wb.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_ahb.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_axi.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_runtests.sv
+/root/riscduino-dcore_d4_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_wb.sv
diff --git a/mpw_precheck/logs/tools.info b/mpw_precheck/logs/tools.info
new file mode 100644
index 0000000..4056146
--- /dev/null
+++ b/mpw_precheck/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.12
+Magic: 8.3.340
\ No newline at end of file
diff --git a/mpw_precheck/logs/xor_check.log b/mpw_precheck/logs/xor_check.log
new file mode 100644
index 0000000..7fe2549
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.log
@@ -0,0 +1,768 @@
+Reading file /root/riscduino-dcore_d4_/gds/user_project_wrapper.gds for cell user_project_wrapper
+dbu=0.001
+cell user_project_wrapper dbu-bbox(ll;ur)=(-43630,-38270;2963250,3557950)
+cell user_project_wrapper dbu-bbox(left,bottom,right,top)=(-43630,-38270,2963250,3557950)
+cell user_project_wrapper dbu-size(width,height)=(3006880,3596220)
+cell user_project_wrapper micron-bbox(left,bottom,right,top)=(-43.63,-38.27,2963.25,3557.9500000000003)
+cell user_project_wrapper micron-size(width,height)=(3006.88,3596.2200000000003)
+Done.
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "sky130_fd_sc_hd__o311ai_4".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__o22a_2".
+Reading "sky130_fd_sc_hd__xor2_4".
+Reading "sky130_fd_sc_hd__a21o_2".
+Reading "sky130_fd_sc_hd__and3_2".
+Reading "sky130_fd_sc_hd__o31ai_4".
+Reading "sky130_fd_sc_hd__o22ai_2".
+Reading "sky130_fd_sc_hd__o31a_2".
+Reading "sky130_fd_sc_hd__o22ai_1".
+Reading "sky130_fd_sc_hd__nor3_4".
+Reading "sky130_fd_sc_hd__o21ai_4".
+Reading "sky130_fd_sc_hd__nor4_1".
+Reading "sky130_fd_sc_hd__a211o_2".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__o211a_2".
+Reading "sky130_fd_sc_hd__a31oi_4".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__a211oi_4".
+Reading "sky130_fd_sc_hd__nand4_4".
+Reading "sky130_fd_sc_hd__xnor2_4".
+Reading "sky130_fd_sc_hd__nor4_2".
+Reading "sky130_fd_sc_hd__a22oi_4".
+Reading "sky130_fd_sc_hd__or4bb_1".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__o21ba_2".
+Reading "sky130_fd_sc_hd__a22oi_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a22o_2".
+Reading "sky130_fd_sc_hd__nand3b_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__nand4_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__nand3_2".
+Reading "sky130_fd_sc_hd__nor3b_1".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__a211oi_2".
+Reading "sky130_fd_sc_hd__and4b_1".
+Reading "sky130_fd_sc_hd__nand3b_1".
+Reading "sky130_fd_sc_hd__o211ai_2".
+Reading "sky130_fd_sc_hd__o21bai_2".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__nand4b_2".
+Reading "sky130_fd_sc_hd__o31ai_2".
+Reading "sky130_fd_sc_hd__a211oi_1".
+Reading "sky130_fd_sc_hd__and4b_2".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__o211ai_1".
+Reading "sky130_fd_sc_hd__a22oi_2".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a31oi_2".
+Reading "sky130_fd_sc_hd__and4bb_1".
+Reading "sky130_fd_sc_hd__dfstp_1".
+Reading "sky130_fd_sc_hd__and4bb_2".
+Reading "sky130_fd_sc_hd__and3b_2".
+Reading "sky130_fd_sc_hd__a311o_1".
+Reading "sky130_fd_sc_hd__or2b_2".
+Reading "sky130_fd_sc_hd__or3_2".
+Reading "sky130_fd_sc_hd__mux2_4".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__a221oi_2".
+Reading "sky130_fd_sc_hd__a221o_2".
+Reading "sky130_fd_sc_hd__nor3_2".
+Reading "sky130_fd_sc_hd__or4_2".
+Reading "sky130_fd_sc_hd__nor3b_2".
+Reading "sky130_fd_sc_hd__xor2_2".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__or4bb_2".
+Reading "sky130_fd_sc_hd__a2111o_1".
+Reading "sky130_fd_sc_hd__o21bai_1".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__o21ba_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__o2111a_1".
+Reading "sky130_fd_sc_hd__nor3_1".
+Reading "sky130_fd_sc_hd__o221a_1".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__dfrtp_4".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__or3b_1".
+Reading "sky130_fd_sc_hd__a21boi_2".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__o21ai_2".
+Reading "sky130_fd_sc_hd__nand3_1".
+Reading "sky130_fd_sc_hd__or4b_4".
+Reading "sky130_fd_sc_hd__o41a_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__or4_1".
+Reading "sky130_fd_sc_hd__or4b_1".
+Reading "sky130_fd_sc_hd__a2bb2o_1".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__o22a_1".
+Reading "sky130_fd_sc_hd__or4b_2".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__clkinv_2".
+Reading "sky130_fd_sc_hd__o311a_1".
+Reading "sky130_fd_sc_hd__a21oi_2".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "sky130_fd_sc_hd__or3_1".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__or2b_1".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_ef_sc_hd__decap_12".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__dfrtp_2".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__dfrtp_1".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__decap_8".
+Reading "sky130_fd_sc_hd__decap_6".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__decap_4".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__dlymetal6s2s_1".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__o221a_2".
+Reading "sky130_fd_sc_hd__o311a_2".
+Reading "sky130_fd_sc_hd__a2111oi_1".
+CIF file read warning: CIF style sky130(vendor): units rescaled by factor of 5 / 1
+CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
+Reading "sky130_fd_sc_hd__o41a_2".
+Reading "sky130_fd_sc_hd__mux4_1".
+Reading "sky130_fd_sc_hd__o21a_2".
+Reading "sky130_fd_sc_hd__mux4_2".
+Reading "sky130_fd_sc_hd__a21bo_2".
+Reading "sky130_fd_sc_hd__a32o_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__and3_4".
+Reading "sky130_fd_sc_hd__or4_4".
+Reading "sky130_fd_sc_hd__a221o_4".
+Reading "sky130_fd_sc_hd__a211o_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nor4b_2".
+Reading "sky130_fd_sc_hd__o22a_4".
+Reading "sky130_fd_sc_hd__a221oi_1".
+Reading "sky130_fd_sc_hd__o22ai_4".
+Reading "sky130_fd_sc_hd__nor4b_1".
+Reading "sky130_fd_sc_hd__nand2_4".
+Reading "sky130_fd_sc_hd__mux2_2".
+Reading "sky130_fd_sc_hd__o32a_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a311o_2".
+Reading "sky130_fd_sc_hd__a2111oi_2".
+Reading "sky130_fd_sc_hd__or2_4".
+Reading "sky130_fd_sc_hd__a22o_4".
+Reading "sky130_fd_sc_hd__nor4_4".
+Reading "sky130_fd_sc_hd__a2bb2o_4".
+Reading "sky130_fd_sc_hd__a21o_4".
+Reading "sky130_fd_sc_hd__a2111o_2".
+Reading "sky130_fd_sc_hd__a2111oi_4".
+Reading "sky130_fd_sc_hd__a311oi_4".
+Reading "sky130_fd_sc_hd__or4bb_4".
+Reading "sky130_fd_sc_hd__o21bai_4".
+Reading "sky130_fd_sc_hd__dfstp_2".
+Reading "sky130_fd_sc_hd__a21bo_4".
+Reading "sky130_fd_sc_hd__o2111a_2".
+Reading "sky130_fd_sc_hd__o2111ai_4".
+Reading "ycr_core_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "sky130_fd_sc_hd__a2bb2oi_1".
+Reading "sky130_fd_sc_hd__o221ai_4".
+Reading "sky130_fd_sc_hd__o221ai_2".
+Reading "sky130_fd_sc_hd__o21a_4".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__o21ba_4".
+Reading "sky130_fd_sc_hd__a221oi_4".
+Reading "sky130_fd_sc_hd__o221a_4".
+Reading "sky130_fd_sc_hd__a2bb2o_2".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__mux2_8".
+Reading "ycr2_iconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nor4b_4".
+Reading "sky130_fd_sc_hd__dlygate4sd1_1".
+Reading "sky130_fd_sc_hd__o221ai_1".
+Reading "sky130_fd_sc_hd__and2b_4".
+Reading "sky130_fd_sc_hd__clkinv_4".
+Reading "sky130_fd_sc_hd__o32ai_2".
+Reading "sky130_fd_sc_hd__o41ai_4".
+Reading "sky130_fd_sc_hd__o31a_4".
+Reading "sky130_fd_sc_hd__and4b_4".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "aes_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+    75000 uses
+    80000 uses
+    85000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_39".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_38".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_33".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_32".
+Reading "sky130_fd_bd_sram__openram_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wmask_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_addr_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_data_dff".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_29".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_28".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_360_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sli_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w1_120_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w0_740_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m7_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m7_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m24_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_14".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m8_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_13".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m3_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_12".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_11".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_delay_chain".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m18_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_16".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w0_740_sactive_dactive".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m22_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand3".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m42_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_10".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m15_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m5_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m2_w1_260_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m2_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_7".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_rw".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_5".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dff_buf_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m41_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m14_w2_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_19".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m5_w1_680_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_18".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_6".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_control_logic_r".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_cr_4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_20".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_17".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_15".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w7_000_sli_dli_da_p".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec_0".
+Reading "sky130_fd_bd_sram__openram_dp_nand2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_wordline_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv_dec".
+Reading "sky130_fd_bd_sram__openram_dp_nand3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and3_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode3x8".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_and2_dec".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_predecode2x4".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_hierarchical_decoder".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_address".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_27".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_26".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_25".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_24".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_nmos_m1_w2_880_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array_0".
+Reading "sky130_fd_bd_sram__openram_sense_amp".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_sense_amp_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_23".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_21".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_22".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pmos_m1_w0_550_sli_dli".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_1".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_column_mux_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pinv".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pdriver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pnand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_pand2".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_mask_and_array".
+Reading "sky130_fd_bd_sram__openram_write_driver".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_write_driver_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_precharge_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_port_data".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_9".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_contact_8".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_row".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182721350): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182722054): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_cap_row" (byte position 182723014): Unknown layer/datatype in boundary, layer=22 type=21
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_row_cap_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_cap_col".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_col_cap_array_0".
+Reading "sky130_fd_bd_sram__openram_dp_cell_dummy".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183215260): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183219036): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183223228): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183228028): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_dummy" (byte position 183230076): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_dummy_array".
+Reading "sky130_fd_bd_sram__openram_dp_cell_replica".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183409518): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183413294): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183417486): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183423950): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell_replica" (byte position 183426126): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column_0".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_column".
+Reading "sky130_fd_bd_sram__openram_dp_cell".
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183666576): Unknown layer/datatype in boundary, layer=33 type=42
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183670352): Unknown layer/datatype in boundary, layer=33 type=43
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183674544): Unknown layer/datatype in boundary, layer=22 type=21
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183681008): Unknown layer/datatype in boundary, layer=22 type=22
+Error while reading cell "sky130_fd_bd_sram__openram_dp_cell" (byte position 183683184): Unknown layer/datatype in boundary, layer=235 type=0
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bitcell_array".
+    5000 uses
+    10000 uses
+    15000 uses
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_replica_bitcell_array".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8_bank".
+Reading "sky130_sram_2kbyte_1rw1r_32x512_8".
+    5000 uses
+Reading "sky130_fd_sc_hd__a21boi_4".
+Reading "sky130_fd_sc_hd__o41ai_1".
+Reading "sky130_fd_sc_hd__o2bb2ai_1".
+Reading "sky130_fd_sc_hd__a311o_4".
+Reading "sky130_fd_sc_hd__o2bb2a_2".
+Reading "sky130_fd_sc_hd__a2111o_4".
+Reading "sky130_fd_sc_hd__nor2b_2".
+Reading "sky130_fd_sc_hd__o311ai_2".
+Reading "sky130_fd_sc_hd__a311oi_1".
+Reading "fpu_wrapper".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+Reading "sky130_fd_sc_hd__o2111ai_1".
+Reading "sky130_fd_sc_hd__nand4b_1".
+Reading "sky130_fd_sc_hd__and4bb_4".
+Reading "sky130_fd_sc_hd__nand4b_4".
+Reading "sky130_fd_sc_hd__dfstp_4".
+Reading "sky130_fd_sc_hd__o32a_4".
+Reading "sky130_fd_sc_hd__inv_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__o211a_4".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "ycr_intf".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__nand2b_2".
+Reading "sky130_fd_sc_hd__clkdlybuf4s50_1".
+Reading "sky130_fd_sc_hd__clkdlybuf4s25_1".
+Reading "sky130_fd_sc_hd__or2b_4".
+Reading "qspim_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "wb_interconnect".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+Reading "switchn".
+Reading "resistor".
+Reading "resistor_3xh".
+Reading "switch2".
+Reading "switch2n".
+Reading "2bit_DAC".
+Reading "resistor_h".
+Reading "3bit_DAC".
+Reading "4bit_DAC".
+Reading "5bit_DAC".
+Reading "6bit_DAC".
+Reading "7bit_DAC".
+Reading "8bit_DAC".
+Reading "2x8bit_DAC".
+Reading "4x8bit_DAC".
+Reading "dac_top".
+Reading "sky130_fd_sc_hd__einvn_8".
+Reading "sky130_fd_sc_hd__clkinv_1".
+Reading "sky130_fd_sc_hd__einvp_2".
+Reading "sky130_fd_sc_hd__einvn_2".
+Reading "sky130_fd_sc_hd__clkinv_8".
+Reading "sky130_fd_sc_hd__einvp_1".
+Reading "dg_pll".
+Reading "sky130_fd_sc_hd__dlclkp_2".
+Reading "sky130_fd_sc_hd__dlclkp_1".
+Reading "sky130_fd_sc_hd__nor3b_4".
+Reading "sky130_fd_sc_hd__nor2b_1".
+Reading "wb_host".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+Reading "sky130_fd_sc_hd__nand2b_4".
+Reading "sky130_fd_sc_hd__o32ai_1".
+Reading "sky130_fd_sc_hd__o2111ai_2".
+Reading "uart_i2c_usb_spi_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+Reading "sky130_fd_sc_hd__a311oi_2".
+Reading "sky130_fd_sc_hd__a32oi_1".
+Reading "sky130_fd_sc_hd__dlxtn_1".
+Reading "sky130_fd_sc_hd__dlxtn_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__dlxtn_2".
+Reading "sky130_fd_sc_hd__a32oi_4".
+Reading "sky130_fd_sc_hd__o2bb2ai_4".
+Reading "pinmux_top".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
+    40000 uses
+    45000 uses
+    50000 uses
+    55000 uses
+    60000 uses
+    65000 uses
+    70000 uses
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+
+Magic 8.3 revision 340 - Compiled on Thu Nov 17 13:45:26 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/opt/checks/xor_check/erase_box.tcl" from command line.
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_project_wrapper
+Reading "user_project_wrapper".
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.880 x 3520.000  (-42.880,  0.000), ( 0.000,  3520.000)  150937.594
+lambda:   4288.00 x 352000.00  (-4288.00,  0.00 ), (  0.00,  352000.00)  1509376000.00
+internal:   8576 x 704000  ( -8576,  0    ), (     0,  704000)  6037504000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  42.500 x 3520.000  ( 2920.000,  0.000), ( 2962.500,  3520.000)  149600.000
+lambda:   4250.00 x 352000.00  ( 292000.00,  0.00 ), ( 296250.00,  352000.00)  1496000000.00
+internal:   8500 x 704000  ( 584000,  0    ), ( 592500,  704000)  5984000000
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.530  (-42.880, -37.530), ( 2962.500,  0.000)  112791.906
+lambda:   300538.00 x 3753.00  (-4288.00, -3753.00), ( 296250.00,  0.00 )  1127919104.00
+internal: 601076 x 7506    ( -8576, -7506 ), ( 592500,  0    )  4511676456
+Root cell box:
+           width x height  (   llx,  lly  ), (   urx,  ury  )  area (units^2)
+
+microns:  3005.380 x 37.210  (-42.880,  3520.000), ( 2962.500,  3557.210)  111830.188
+lambda:   300538.00 x 3721.00  (-4288.00,  352000.00), ( 296250.00,  355721.00)  1118301952.00
+internal: 601076 x 7442    ( -8576,  704000), ( 592500,  711442)  4473207592
+   Generating output for cell xor_target
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper_erased.gds ..
+Reading /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper_empty_erased.gds ..
+--- Running XOR for 69/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 530 (flat)  530 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.020s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 70/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 107 (flat)  107 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 71/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 71/44 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 116 (flat)  116 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+--- Running XOR for 72/20 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 16 (flat)  16 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+--- Running XOR for 81/14 ---
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+"input" in: xor.rb.drc:39
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+"^" in: xor.rb.drc:39
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 524.00M
+XOR differences: 0
+"output" in: xor.rb.drc:43
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 524.00M
+Writing layout file: /mnt/uffs/user/u5295_dinesha/design/riscduino-dcore_d4_/jobs/mpw_precheck/0f94d654-b64a-4591-9bc7-aa2e58125b09/outputs/user_project_wrapper.xor.gds ..
+Total elapsed: 0.190s  Memory: 524.00M
diff --git a/mpw_precheck/logs/xor_check.total b/mpw_precheck/logs/xor_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/mpw_precheck/logs/xor_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/mpw_precheck/outputs/reports/gpio_defines.report b/mpw_precheck/outputs/reports/gpio_defines.report
new file mode 100644
index 0000000..a5b0eaf
--- /dev/null
+++ b/mpw_precheck/outputs/reports/gpio_defines.report
@@ -0,0 +1,33 @@
+USER_CONFIG_GPIO_5_INIT    13'h1800
+USER_CONFIG_GPIO_6_INIT    13'h1800
+USER_CONFIG_GPIO_7_INIT    13'h1800
+USER_CONFIG_GPIO_8_INIT    13'h1800
+USER_CONFIG_GPIO_9_INIT    13'h1800
+USER_CONFIG_GPIO_10_INIT   13'h1800
+USER_CONFIG_GPIO_11_INIT   13'h1800
+USER_CONFIG_GPIO_12_INIT   13'h1800
+USER_CONFIG_GPIO_13_INIT   13'h1800
+USER_CONFIG_GPIO_14_INIT   13'h1800
+USER_CONFIG_GPIO_15_INIT   13'h1800
+USER_CONFIG_GPIO_16_INIT   13'h1800
+USER_CONFIG_GPIO_17_INIT   13'h1800
+USER_CONFIG_GPIO_18_INIT   13'h1800
+USER_CONFIG_GPIO_19_INIT   13'h1800
+USER_CONFIG_GPIO_20_INIT   13'h1800
+USER_CONFIG_GPIO_21_INIT   13'h1800
+USER_CONFIG_GPIO_22_INIT   13'h1800
+USER_CONFIG_GPIO_23_INIT   13'h1800
+USER_CONFIG_GPIO_24_INIT   13'h1800
+USER_CONFIG_GPIO_25_INIT   13'h1800
+USER_CONFIG_GPIO_26_INIT   13'h1800
+USER_CONFIG_GPIO_27_INIT   13'h1800
+USER_CONFIG_GPIO_28_INIT   13'h1800
+USER_CONFIG_GPIO_29_INIT   13'h1800
+USER_CONFIG_GPIO_30_INIT   13'h1800
+USER_CONFIG_GPIO_31_INIT   13'h1800
+USER_CONFIG_GPIO_32_INIT   13'h1800
+USER_CONFIG_GPIO_33_INIT   13'h1800
+USER_CONFIG_GPIO_34_INIT   13'h1800
+USER_CONFIG_GPIO_35_INIT   13'h1800
+USER_CONFIG_GPIO_36_INIT   13'h1800
+USER_CONFIG_GPIO_37_INIT   13'h1800
diff --git a/mpw_precheck/outputs/reports/klayout_beol_check.xml b/mpw_precheck/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..5ffd971
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1: non-ring mcon should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_a</name>
+   <description>ct.1_a : minimum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1_b</name>
+   <description>ct.1_b : maximum length of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>791_m1.4</name>
+   <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : mcon periphery must be enclosed by m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a_a</name>
+   <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : via outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_a</name>
+   <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a_b</name>
+   <description>via.1a_b : maximum length of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a_a</name>
+   <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.5a</name>
+   <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4_a</name>
+   <description>m2.4_a : via in periphery must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_a</name>
+   <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a_b</name>
+   <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4_a</name>
+   <description>via2.4_a : via must be enclosed by met2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3cd</name>
+   <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4_a</name>
+   <description>m3.4_a : via2 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1</name>
+   <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_a</name>
+   <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1_b</name>
+   <description>via3.1_b : maximum length of via3 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4_a</name>
+   <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4a</name>
+   <description>m4.4a : min. m4 area : 0.240um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3_a</name>
+   <description>m4.3_a : via3 must be enclosed by met4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1</name>
+   <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_a</name>
+   <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1_b</name>
+   <description>via4.1_b : maximum length of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4_a</name>
+   <description>via4.4_a : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3_a</name>
+   <description>m5.3_a : via must be enclosed by m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.4</name>
+   <description>m5.4 : min. m5 area : 4.0um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_feol_check.xml b/mpw_precheck/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..71b30a8
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,375 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell.2</name>
+   <description>dnwell.2 : min. dnwell width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.1</name>
+   <description>nwell.1 : min. nwell width : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.2a</name>
+   <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell.6</name>
+   <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.1</name>
+   <description>hvtp.1 : min. hvtp width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp.2</name>
+   <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.1</name>
+   <description>hvtr.1 : min. hvtr width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2</name>
+   <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr.2_a</name>
+   <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.1a</name>
+   <description>lvtn.1a : min. lvtn width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn.2</name>
+   <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.1</name>
+   <description>ncm.1 : min. ncm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm.2a</name>
+   <description>ncm.2a : min. ncm spacing : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1</name>
+   <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_a</name>
+   <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_b</name>
+   <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.1_c</name>
+   <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>difftap.3</name>
+   <description>difftap.3 : min. difftap spacing : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.1</name>
+   <description>tunm.1 : min. tunm width : 0.41um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm.2</name>
+   <description>tunm.2 : min. tunm spacing : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.1a</name>
+   <description>poly.1a : min. poly width : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly.2</name>
+   <description>poly.2 : min. poly spacing : 0.21um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.1a</name>
+   <description>rpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm.2</name>
+   <description>rpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.1a</name>
+   <description>urpm.1a : min. rpm width : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>urpm.2</name>
+   <description>urpm.2 : min. rpm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.1</name>
+   <description>npc.1 : min. npc width : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc.2</name>
+   <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.1</name>
+   <description>nsd.1 : min. nsdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsd.2</name>
+   <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.1</name>
+   <description>psd.1 : min. psdm width : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psd.2</name>
+   <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1</name>
+   <description>licon.1 : licon should be rectangle</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.1_a/b</name>
+   <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13</name>
+   <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.13_a</name>
+   <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon.17</name>
+   <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.1</name>
+   <description>capm.1 : min. capm width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2a</name>
+   <description>capm.2a : min. capm spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b</name>
+   <description>capm.2b : min. capm spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.2b_a</name>
+   <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3</name>
+   <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.3_a</name>
+   <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.4</name>
+   <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.5</name>
+   <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>capm.11</name>
+   <description>capm.11 : Min spacing of capm and met3 not overlapping capm : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.1</name>
+   <description>cap2m.1 : min. cap2m width : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2a</name>
+   <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b</name>
+   <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.2b_a</name>
+   <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3</name>
+   <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.3_a</name>
+   <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.4</name>
+   <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.5</name>
+   <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>cap2m.11</name>
+   <description>cap2m.11 : Min spacing of cap2m and met4 not overlapping cap2m : 0.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.1</name>
+   <description>hvi.1 : min. hvi width : 0.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi.2a</name>
+   <description>hvi.2a : min. hvi spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.1</name>
+   <description>hvntm.1 : min. hvntm width : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm.2</name>
+   <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..698a39a
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_offgrid_check.xml b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..95ebbc9
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2 : non 90 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2 : non 90 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..fdacb7c
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/root/riscduino-dcore_d4_/gds/user_project_wrapper.gds, topcell=user_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..7f95f69
--- /dev/null
+++ b/mpw_precheck/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/opt/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+  <cell>
+   <name>user_project_wrapper</name>
+   <variant/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.drc.report b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..46ca7f3
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.rdb b/mpw_precheck/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..ac5b3c4
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_project_wrapper
+ 100
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tcl b/mpw_precheck/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tcl
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.tr b/mpw_precheck/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.tr
diff --git a/mpw_precheck/outputs/reports/magic_drc_check.xml b/mpw_precheck/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..0eff265
--- /dev/null
+++ b/mpw_precheck/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+    <categories/>
+    <cells>
+        <cell>
+            <name>user_project_wrapper</name>
+        </cell>
+    </cells>
+    <items/>
+</report-database>
diff --git a/mpw_precheck/outputs/user_project_wrapper.filtered.v b/mpw_precheck/outputs/user_project_wrapper.filtered.v
new file mode 100644
index 0000000..e9611ca
--- /dev/null
+++ b/mpw_precheck/outputs/user_project_wrapper.filtered.v
@@ -0,0 +1,8356 @@
+module user_project_wrapper (user_clock2,
+    wb_clk_i,
+    wb_rst_i,
+    wbs_ack_o,
+    wbs_cyc_i,
+    wbs_stb_i,
+    wbs_we_i,
+    vssa2,
+    vdda2,
+    vssa1,
+    vdda1,
+    vssd2,
+    vccd2,
+    vssd1,
+    vccd1,
+    analog_io,
+    io_in,
+    io_oeb,
+    io_out,
+    la_data_in,
+    la_data_out,
+    la_oenb,
+    user_irq,
+    wbs_adr_i,
+    wbs_dat_i,
+    wbs_dat_o,
+    wbs_sel_i);
+ input user_clock2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ input vssa2;
+ input vdda2;
+ input vssa1;
+ input vdda1;
+ input vssd2;
+ input vccd2;
+ input vssd1;
+ input vccd1;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
+
+ wire \cfg_ccska_aes_rp[0] ;
+ wire \cfg_ccska_aes_rp[1] ;
+ wire \cfg_ccska_aes_rp[2] ;
+ wire \cfg_ccska_aes_rp[3] ;
+ wire \cfg_ccska_fpu_rp[0] ;
+ wire \cfg_ccska_fpu_rp[1] ;
+ wire \cfg_ccska_fpu_rp[2] ;
+ wire \cfg_ccska_fpu_rp[3] ;
+ wire \cfg_ccska_riscv_core2_rp[0] ;
+ wire \cfg_ccska_riscv_core2_rp[1] ;
+ wire \cfg_ccska_riscv_core2_rp[2] ;
+ wire \cfg_ccska_riscv_core2_rp[3] ;
+ wire \cfg_ccska_riscv_core3_rp[0] ;
+ wire \cfg_ccska_riscv_core3_rp[1] ;
+ wire \cfg_ccska_riscv_core3_rp[2] ;
+ wire \cfg_ccska_riscv_core3_rp[3] ;
+ wire \cfg_clk_skew_ctrl1[0] ;
+ wire \cfg_clk_skew_ctrl1[10] ;
+ wire \cfg_clk_skew_ctrl1[11] ;
+ wire \cfg_clk_skew_ctrl1[12] ;
+ wire \cfg_clk_skew_ctrl1[13] ;
+ wire \cfg_clk_skew_ctrl1[14] ;
+ wire \cfg_clk_skew_ctrl1[15] ;
+ wire \cfg_clk_skew_ctrl1[16] ;
+ wire \cfg_clk_skew_ctrl1[17] ;
+ wire \cfg_clk_skew_ctrl1[18] ;
+ wire \cfg_clk_skew_ctrl1[19] ;
+ wire \cfg_clk_skew_ctrl1[1] ;
+ wire \cfg_clk_skew_ctrl1[20] ;
+ wire \cfg_clk_skew_ctrl1[21] ;
+ wire \cfg_clk_skew_ctrl1[22] ;
+ wire \cfg_clk_skew_ctrl1[23] ;
+ wire \cfg_clk_skew_ctrl1[24] ;
+ wire \cfg_clk_skew_ctrl1[25] ;
+ wire \cfg_clk_skew_ctrl1[26] ;
+ wire \cfg_clk_skew_ctrl1[27] ;
+ wire \cfg_clk_skew_ctrl1[28] ;
+ wire \cfg_clk_skew_ctrl1[29] ;
+ wire \cfg_clk_skew_ctrl1[2] ;
+ wire \cfg_clk_skew_ctrl1[30] ;
+ wire \cfg_clk_skew_ctrl1[31] ;
+ wire \cfg_clk_skew_ctrl1[3] ;
+ wire \cfg_clk_skew_ctrl1[4] ;
+ wire \cfg_clk_skew_ctrl1[5] ;
+ wire \cfg_clk_skew_ctrl1[6] ;
+ wire \cfg_clk_skew_ctrl1[7] ;
+ wire \cfg_clk_skew_ctrl1[8] ;
+ wire \cfg_clk_skew_ctrl1[9] ;
+ wire \cfg_clk_skew_ctrl2[0] ;
+ wire \cfg_clk_skew_ctrl2[10] ;
+ wire \cfg_clk_skew_ctrl2[11] ;
+ wire \cfg_clk_skew_ctrl2[12] ;
+ wire \cfg_clk_skew_ctrl2[13] ;
+ wire \cfg_clk_skew_ctrl2[14] ;
+ wire \cfg_clk_skew_ctrl2[15] ;
+ wire \cfg_clk_skew_ctrl2[16] ;
+ wire \cfg_clk_skew_ctrl2[17] ;
+ wire \cfg_clk_skew_ctrl2[18] ;
+ wire \cfg_clk_skew_ctrl2[19] ;
+ wire \cfg_clk_skew_ctrl2[1] ;
+ wire \cfg_clk_skew_ctrl2[20] ;
+ wire \cfg_clk_skew_ctrl2[21] ;
+ wire \cfg_clk_skew_ctrl2[22] ;
+ wire \cfg_clk_skew_ctrl2[23] ;
+ wire \cfg_clk_skew_ctrl2[24] ;
+ wire \cfg_clk_skew_ctrl2[25] ;
+ wire \cfg_clk_skew_ctrl2[26] ;
+ wire \cfg_clk_skew_ctrl2[27] ;
+ wire \cfg_clk_skew_ctrl2[28] ;
+ wire \cfg_clk_skew_ctrl2[29] ;
+ wire \cfg_clk_skew_ctrl2[2] ;
+ wire \cfg_clk_skew_ctrl2[30] ;
+ wire \cfg_clk_skew_ctrl2[31] ;
+ wire \cfg_clk_skew_ctrl2[3] ;
+ wire \cfg_clk_skew_ctrl2[4] ;
+ wire \cfg_clk_skew_ctrl2[5] ;
+ wire \cfg_clk_skew_ctrl2[6] ;
+ wire \cfg_clk_skew_ctrl2[7] ;
+ wire \cfg_clk_skew_ctrl2[8] ;
+ wire \cfg_clk_skew_ctrl2[9] ;
+ wire \cfg_dac0_mux_sel[0] ;
+ wire \cfg_dac0_mux_sel[1] ;
+ wire \cfg_dac0_mux_sel[2] ;
+ wire \cfg_dac0_mux_sel[3] ;
+ wire \cfg_dac0_mux_sel[4] ;
+ wire \cfg_dac0_mux_sel[5] ;
+ wire \cfg_dac0_mux_sel[6] ;
+ wire \cfg_dac0_mux_sel[7] ;
+ wire \cfg_dac1_mux_sel[0] ;
+ wire \cfg_dac1_mux_sel[1] ;
+ wire \cfg_dac1_mux_sel[2] ;
+ wire \cfg_dac1_mux_sel[3] ;
+ wire \cfg_dac1_mux_sel[4] ;
+ wire \cfg_dac1_mux_sel[5] ;
+ wire \cfg_dac1_mux_sel[6] ;
+ wire \cfg_dac1_mux_sel[7] ;
+ wire \cfg_dac2_mux_sel[0] ;
+ wire \cfg_dac2_mux_sel[1] ;
+ wire \cfg_dac2_mux_sel[2] ;
+ wire \cfg_dac2_mux_sel[3] ;
+ wire \cfg_dac2_mux_sel[4] ;
+ wire \cfg_dac2_mux_sel[5] ;
+ wire \cfg_dac2_mux_sel[6] ;
+ wire \cfg_dac2_mux_sel[7] ;
+ wire \cfg_dac3_mux_sel[0] ;
+ wire \cfg_dac3_mux_sel[1] ;
+ wire \cfg_dac3_mux_sel[2] ;
+ wire \cfg_dac3_mux_sel[3] ;
+ wire \cfg_dac3_mux_sel[4] ;
+ wire \cfg_dac3_mux_sel[5] ;
+ wire \cfg_dac3_mux_sel[6] ;
+ wire \cfg_dac3_mux_sel[7] ;
+ wire \cfg_dc_trim[0] ;
+ wire \cfg_dc_trim[10] ;
+ wire \cfg_dc_trim[11] ;
+ wire \cfg_dc_trim[12] ;
+ wire \cfg_dc_trim[13] ;
+ wire \cfg_dc_trim[14] ;
+ wire \cfg_dc_trim[15] ;
+ wire \cfg_dc_trim[16] ;
+ wire \cfg_dc_trim[17] ;
+ wire \cfg_dc_trim[18] ;
+ wire \cfg_dc_trim[19] ;
+ wire \cfg_dc_trim[1] ;
+ wire \cfg_dc_trim[20] ;
+ wire \cfg_dc_trim[21] ;
+ wire \cfg_dc_trim[22] ;
+ wire \cfg_dc_trim[23] ;
+ wire \cfg_dc_trim[24] ;
+ wire \cfg_dc_trim[25] ;
+ wire \cfg_dc_trim[2] ;
+ wire \cfg_dc_trim[3] ;
+ wire \cfg_dc_trim[4] ;
+ wire \cfg_dc_trim[5] ;
+ wire \cfg_dc_trim[6] ;
+ wire \cfg_dc_trim[7] ;
+ wire \cfg_dc_trim[8] ;
+ wire \cfg_dc_trim[9] ;
+ wire cfg_dco_mode;
+ wire cfg_pll_enb;
+ wire \cfg_pll_fed_div[0] ;
+ wire \cfg_pll_fed_div[1] ;
+ wire \cfg_pll_fed_div[2] ;
+ wire \cfg_pll_fed_div[3] ;
+ wire \cfg_pll_fed_div[4] ;
+ wire \cfg_riscv_ctrl[0] ;
+ wire \cfg_riscv_ctrl[10] ;
+ wire \cfg_riscv_ctrl[11] ;
+ wire \cfg_riscv_ctrl[12] ;
+ wire \cfg_riscv_ctrl[13] ;
+ wire \cfg_riscv_ctrl[14] ;
+ wire \cfg_riscv_ctrl[15] ;
+ wire \cfg_riscv_ctrl[1] ;
+ wire \cfg_riscv_ctrl[2] ;
+ wire \cfg_riscv_ctrl[3] ;
+ wire \cfg_riscv_ctrl[4] ;
+ wire \cfg_riscv_ctrl[5] ;
+ wire \cfg_riscv_ctrl[6] ;
+ wire \cfg_riscv_ctrl[7] ;
+ wire \cfg_riscv_ctrl[8] ;
+ wire \cfg_riscv_ctrl[9] ;
+ wire cfg_strap_pad_ctrl;
+ wire cfg_strap_pad_ctrl_rp;
+ wire \cfg_wcska_pinmux_rp[0] ;
+ wire \cfg_wcska_pinmux_rp[1] ;
+ wire \cfg_wcska_pinmux_rp[2] ;
+ wire \cfg_wcska_pinmux_rp[3] ;
+ wire \cfg_wcska_qspi_co_rp[0] ;
+ wire \cfg_wcska_qspi_co_rp[1] ;
+ wire \cfg_wcska_qspi_co_rp[2] ;
+ wire \cfg_wcska_qspi_co_rp[3] ;
+ wire \cfg_wcska_qspi_rp[0] ;
+ wire \cfg_wcska_qspi_rp[1] ;
+ wire \cfg_wcska_qspi_rp[2] ;
+ wire \cfg_wcska_qspi_rp[3] ;
+ wire \cfg_wcska_uart_rp[0] ;
+ wire \cfg_wcska_uart_rp[1] ;
+ wire \cfg_wcska_uart_rp[2] ;
+ wire \cfg_wcska_uart_rp[3] ;
+ wire cpu_clk;
+ wire cpu_clk_aes;
+ wire cpu_clk_fpu;
+ wire \cpu_clk_rp[6] ;
+ wire \cpu_clk_rp[7] ;
+ wire \cpu_clk_rp[8] ;
+ wire \cpu_clk_rp[9] ;
+ wire \cpu_core_rst_n[0] ;
+ wire \cpu_core_rst_n[1] ;
+ wire \cpu_core_rst_n[2] ;
+ wire \cpu_core_rst_n[3] ;
+ wire e_reset_n;
+ wire e_reset_n_rp;
+ wire i2c_rst_n;
+ wire i2cm_clk_i;
+ wire i2cm_clk_o;
+ wire i2cm_clk_oen;
+ wire i2cm_data_i;
+ wire i2cm_data_o;
+ wire i2cm_data_oen;
+ wire i2cm_intr_o;
+ wire \irq_lines[0] ;
+ wire \irq_lines[10] ;
+ wire \irq_lines[11] ;
+ wire \irq_lines[12] ;
+ wire \irq_lines[13] ;
+ wire \irq_lines[14] ;
+ wire \irq_lines[15] ;
+ wire \irq_lines[16] ;
+ wire \irq_lines[17] ;
+ wire \irq_lines[18] ;
+ wire \irq_lines[19] ;
+ wire \irq_lines[1] ;
+ wire \irq_lines[20] ;
+ wire \irq_lines[21] ;
+ wire \irq_lines[22] ;
+ wire \irq_lines[23] ;
+ wire \irq_lines[24] ;
+ wire \irq_lines[25] ;
+ wire \irq_lines[26] ;
+ wire \irq_lines[27] ;
+ wire \irq_lines[28] ;
+ wire \irq_lines[29] ;
+ wire \irq_lines[2] ;
+ wire \irq_lines[30] ;
+ wire \irq_lines[31] ;
+ wire \irq_lines[3] ;
+ wire \irq_lines[4] ;
+ wire \irq_lines[5] ;
+ wire \irq_lines[6] ;
+ wire \irq_lines[7] ;
+ wire \irq_lines[8] ;
+ wire \irq_lines[9] ;
+ wire p_reset_n;
+ wire p_reset_n_rp;
+ wire \pll_clk_out[0] ;
+ wire \pll_clk_out[1] ;
+ wire pll_ref_clk;
+ wire pulse1m_mclk;
+ wire qspim_rst_n;
+ wire s_reset_n;
+ wire \sflash_di[0] ;
+ wire \sflash_di[1] ;
+ wire \sflash_di[2] ;
+ wire \sflash_di[3] ;
+ wire \sflash_do[0] ;
+ wire \sflash_do[1] ;
+ wire \sflash_do[2] ;
+ wire \sflash_do[3] ;
+ wire \sflash_oen[0] ;
+ wire \sflash_oen[1] ;
+ wire \sflash_oen[2] ;
+ wire \sflash_oen[3] ;
+ wire sflash_sck;
+ wire soft_irq;
+ wire \spi_csn[0] ;
+ wire \spi_csn[1] ;
+ wire \spi_csn[2] ;
+ wire \spi_csn[3] ;
+ wire sspim_rst_n;
+ wire sspim_sck;
+ wire sspim_si;
+ wire sspim_so;
+ wire \sspim_ssn[0] ;
+ wire \sspim_ssn[1] ;
+ wire \sspim_ssn[2] ;
+ wire \sspim_ssn[3] ;
+ wire sspis_sck;
+ wire sspis_si;
+ wire sspis_so;
+ wire sspis_ssn;
+ wire \strap_sticky[0] ;
+ wire \strap_sticky[10] ;
+ wire \strap_sticky[11] ;
+ wire \strap_sticky[12] ;
+ wire \strap_sticky[13] ;
+ wire \strap_sticky[14] ;
+ wire \strap_sticky[15] ;
+ wire \strap_sticky[16] ;
+ wire \strap_sticky[17] ;
+ wire \strap_sticky[18] ;
+ wire \strap_sticky[19] ;
+ wire \strap_sticky[1] ;
+ wire \strap_sticky[20] ;
+ wire \strap_sticky[21] ;
+ wire \strap_sticky[22] ;
+ wire \strap_sticky[23] ;
+ wire \strap_sticky[24] ;
+ wire \strap_sticky[25] ;
+ wire \strap_sticky[26] ;
+ wire \strap_sticky[27] ;
+ wire \strap_sticky[28] ;
+ wire \strap_sticky[29] ;
+ wire \strap_sticky[2] ;
+ wire \strap_sticky[30] ;
+ wire \strap_sticky[31] ;
+ wire \strap_sticky[3] ;
+ wire \strap_sticky[4] ;
+ wire \strap_sticky[5] ;
+ wire \strap_sticky[6] ;
+ wire \strap_sticky[7] ;
+ wire \strap_sticky[8] ;
+ wire \strap_sticky[9] ;
+ wire \strap_sticky_rp[0] ;
+ wire \strap_sticky_rp[10] ;
+ wire \strap_sticky_rp[11] ;
+ wire \strap_sticky_rp[12] ;
+ wire \strap_sticky_rp[13] ;
+ wire \strap_sticky_rp[14] ;
+ wire \strap_sticky_rp[15] ;
+ wire \strap_sticky_rp[16] ;
+ wire \strap_sticky_rp[17] ;
+ wire \strap_sticky_rp[18] ;
+ wire \strap_sticky_rp[19] ;
+ wire \strap_sticky_rp[1] ;
+ wire \strap_sticky_rp[20] ;
+ wire \strap_sticky_rp[21] ;
+ wire \strap_sticky_rp[22] ;
+ wire \strap_sticky_rp[23] ;
+ wire \strap_sticky_rp[24] ;
+ wire \strap_sticky_rp[25] ;
+ wire \strap_sticky_rp[26] ;
+ wire \strap_sticky_rp[27] ;
+ wire \strap_sticky_rp[28] ;
+ wire \strap_sticky_rp[29] ;
+ wire \strap_sticky_rp[2] ;
+ wire \strap_sticky_rp[30] ;
+ wire \strap_sticky_rp[31] ;
+ wire \strap_sticky_rp[3] ;
+ wire \strap_sticky_rp[4] ;
+ wire \strap_sticky_rp[5] ;
+ wire \strap_sticky_rp[6] ;
+ wire \strap_sticky_rp[7] ;
+ wire \strap_sticky_rp[8] ;
+ wire \strap_sticky_rp[9] ;
+ wire \strap_uartm[0] ;
+ wire \strap_uartm[1] ;
+ wire \strap_uartm_rp[0] ;
+ wire \strap_uartm_rp[1] ;
+ wire \system_strap[0] ;
+ wire \system_strap[10] ;
+ wire \system_strap[11] ;
+ wire \system_strap[12] ;
+ wire \system_strap[13] ;
+ wire \system_strap[14] ;
+ wire \system_strap[15] ;
+ wire \system_strap[16] ;
+ wire \system_strap[17] ;
+ wire \system_strap[18] ;
+ wire \system_strap[19] ;
+ wire \system_strap[1] ;
+ wire \system_strap[20] ;
+ wire \system_strap[21] ;
+ wire \system_strap[22] ;
+ wire \system_strap[23] ;
+ wire \system_strap[24] ;
+ wire \system_strap[25] ;
+ wire \system_strap[26] ;
+ wire \system_strap[27] ;
+ wire \system_strap[28] ;
+ wire \system_strap[29] ;
+ wire \system_strap[2] ;
+ wire \system_strap[30] ;
+ wire \system_strap[31] ;
+ wire \system_strap[3] ;
+ wire \system_strap[4] ;
+ wire \system_strap[5] ;
+ wire \system_strap[6] ;
+ wire \system_strap[7] ;
+ wire \system_strap[8] ;
+ wire \system_strap[9] ;
+ wire \system_strap_rp[0] ;
+ wire \system_strap_rp[10] ;
+ wire \system_strap_rp[11] ;
+ wire \system_strap_rp[12] ;
+ wire \system_strap_rp[13] ;
+ wire \system_strap_rp[14] ;
+ wire \system_strap_rp[15] ;
+ wire \system_strap_rp[16] ;
+ wire \system_strap_rp[17] ;
+ wire \system_strap_rp[18] ;
+ wire \system_strap_rp[19] ;
+ wire \system_strap_rp[1] ;
+ wire \system_strap_rp[20] ;
+ wire \system_strap_rp[21] ;
+ wire \system_strap_rp[22] ;
+ wire \system_strap_rp[23] ;
+ wire \system_strap_rp[24] ;
+ wire \system_strap_rp[25] ;
+ wire \system_strap_rp[26] ;
+ wire \system_strap_rp[27] ;
+ wire \system_strap_rp[28] ;
+ wire \system_strap_rp[29] ;
+ wire \system_strap_rp[2] ;
+ wire \system_strap_rp[30] ;
+ wire \system_strap_rp[31] ;
+ wire \system_strap_rp[3] ;
+ wire \system_strap_rp[4] ;
+ wire \system_strap_rp[5] ;
+ wire \system_strap_rp[6] ;
+ wire \system_strap_rp[7] ;
+ wire \system_strap_rp[8] ;
+ wire \system_strap_rp[9] ;
+ wire \u_riscv_top.aes_dmem_addr[0] ;
+ wire \u_riscv_top.aes_dmem_addr[1] ;
+ wire \u_riscv_top.aes_dmem_addr[2] ;
+ wire \u_riscv_top.aes_dmem_addr[3] ;
+ wire \u_riscv_top.aes_dmem_addr[4] ;
+ wire \u_riscv_top.aes_dmem_addr[5] ;
+ wire \u_riscv_top.aes_dmem_addr[6] ;
+ wire \u_riscv_top.aes_dmem_cmd ;
+ wire \u_riscv_top.aes_dmem_rdata[0] ;
+ wire \u_riscv_top.aes_dmem_rdata[10] ;
+ wire \u_riscv_top.aes_dmem_rdata[11] ;
+ wire \u_riscv_top.aes_dmem_rdata[12] ;
+ wire \u_riscv_top.aes_dmem_rdata[13] ;
+ wire \u_riscv_top.aes_dmem_rdata[14] ;
+ wire \u_riscv_top.aes_dmem_rdata[15] ;
+ wire \u_riscv_top.aes_dmem_rdata[16] ;
+ wire \u_riscv_top.aes_dmem_rdata[17] ;
+ wire \u_riscv_top.aes_dmem_rdata[18] ;
+ wire \u_riscv_top.aes_dmem_rdata[19] ;
+ wire \u_riscv_top.aes_dmem_rdata[1] ;
+ wire \u_riscv_top.aes_dmem_rdata[20] ;
+ wire \u_riscv_top.aes_dmem_rdata[21] ;
+ wire \u_riscv_top.aes_dmem_rdata[22] ;
+ wire \u_riscv_top.aes_dmem_rdata[23] ;
+ wire \u_riscv_top.aes_dmem_rdata[24] ;
+ wire \u_riscv_top.aes_dmem_rdata[25] ;
+ wire \u_riscv_top.aes_dmem_rdata[26] ;
+ wire \u_riscv_top.aes_dmem_rdata[27] ;
+ wire \u_riscv_top.aes_dmem_rdata[28] ;
+ wire \u_riscv_top.aes_dmem_rdata[29] ;
+ wire \u_riscv_top.aes_dmem_rdata[2] ;
+ wire \u_riscv_top.aes_dmem_rdata[30] ;
+ wire \u_riscv_top.aes_dmem_rdata[31] ;
+ wire \u_riscv_top.aes_dmem_rdata[3] ;
+ wire \u_riscv_top.aes_dmem_rdata[4] ;
+ wire \u_riscv_top.aes_dmem_rdata[5] ;
+ wire \u_riscv_top.aes_dmem_rdata[6] ;
+ wire \u_riscv_top.aes_dmem_rdata[7] ;
+ wire \u_riscv_top.aes_dmem_rdata[8] ;
+ wire \u_riscv_top.aes_dmem_rdata[9] ;
+ wire \u_riscv_top.aes_dmem_req ;
+ wire \u_riscv_top.aes_dmem_req_ack ;
+ wire \u_riscv_top.aes_dmem_resp[0] ;
+ wire \u_riscv_top.aes_dmem_resp[1] ;
+ wire \u_riscv_top.aes_dmem_wdata[0] ;
+ wire \u_riscv_top.aes_dmem_wdata[10] ;
+ wire \u_riscv_top.aes_dmem_wdata[11] ;
+ wire \u_riscv_top.aes_dmem_wdata[12] ;
+ wire \u_riscv_top.aes_dmem_wdata[13] ;
+ wire \u_riscv_top.aes_dmem_wdata[14] ;
+ wire \u_riscv_top.aes_dmem_wdata[15] ;
+ wire \u_riscv_top.aes_dmem_wdata[16] ;
+ wire \u_riscv_top.aes_dmem_wdata[17] ;
+ wire \u_riscv_top.aes_dmem_wdata[18] ;
+ wire \u_riscv_top.aes_dmem_wdata[19] ;
+ wire \u_riscv_top.aes_dmem_wdata[1] ;
+ wire \u_riscv_top.aes_dmem_wdata[20] ;
+ wire \u_riscv_top.aes_dmem_wdata[21] ;
+ wire \u_riscv_top.aes_dmem_wdata[22] ;
+ wire \u_riscv_top.aes_dmem_wdata[23] ;
+ wire \u_riscv_top.aes_dmem_wdata[24] ;
+ wire \u_riscv_top.aes_dmem_wdata[25] ;
+ wire \u_riscv_top.aes_dmem_wdata[26] ;
+ wire \u_riscv_top.aes_dmem_wdata[27] ;
+ wire \u_riscv_top.aes_dmem_wdata[28] ;
+ wire \u_riscv_top.aes_dmem_wdata[29] ;
+ wire \u_riscv_top.aes_dmem_wdata[2] ;
+ wire \u_riscv_top.aes_dmem_wdata[30] ;
+ wire \u_riscv_top.aes_dmem_wdata[31] ;
+ wire \u_riscv_top.aes_dmem_wdata[3] ;
+ wire \u_riscv_top.aes_dmem_wdata[4] ;
+ wire \u_riscv_top.aes_dmem_wdata[5] ;
+ wire \u_riscv_top.aes_dmem_wdata[6] ;
+ wire \u_riscv_top.aes_dmem_wdata[7] ;
+ wire \u_riscv_top.aes_dmem_wdata[8] ;
+ wire \u_riscv_top.aes_dmem_wdata[9] ;
+ wire \u_riscv_top.aes_dmem_width[0] ;
+ wire \u_riscv_top.aes_dmem_width[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core0[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_core1[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_icon[3] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_ccska_riscv_intf[3] ;
+ wire \u_riscv_top.cfg_dcache_force_flush ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[0] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[1] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[2] ;
+ wire \u_riscv_top.cfg_wcska_riscv_intf[3] ;
+ wire \u_riscv_top.core0_debug[0] ;
+ wire \u_riscv_top.core0_debug[10] ;
+ wire \u_riscv_top.core0_debug[11] ;
+ wire \u_riscv_top.core0_debug[12] ;
+ wire \u_riscv_top.core0_debug[13] ;
+ wire \u_riscv_top.core0_debug[14] ;
+ wire \u_riscv_top.core0_debug[15] ;
+ wire \u_riscv_top.core0_debug[16] ;
+ wire \u_riscv_top.core0_debug[17] ;
+ wire \u_riscv_top.core0_debug[18] ;
+ wire \u_riscv_top.core0_debug[19] ;
+ wire \u_riscv_top.core0_debug[1] ;
+ wire \u_riscv_top.core0_debug[20] ;
+ wire \u_riscv_top.core0_debug[21] ;
+ wire \u_riscv_top.core0_debug[22] ;
+ wire \u_riscv_top.core0_debug[23] ;
+ wire \u_riscv_top.core0_debug[24] ;
+ wire \u_riscv_top.core0_debug[25] ;
+ wire \u_riscv_top.core0_debug[26] ;
+ wire \u_riscv_top.core0_debug[27] ;
+ wire \u_riscv_top.core0_debug[28] ;
+ wire \u_riscv_top.core0_debug[29] ;
+ wire \u_riscv_top.core0_debug[2] ;
+ wire \u_riscv_top.core0_debug[30] ;
+ wire \u_riscv_top.core0_debug[31] ;
+ wire \u_riscv_top.core0_debug[32] ;
+ wire \u_riscv_top.core0_debug[33] ;
+ wire \u_riscv_top.core0_debug[34] ;
+ wire \u_riscv_top.core0_debug[35] ;
+ wire \u_riscv_top.core0_debug[36] ;
+ wire \u_riscv_top.core0_debug[37] ;
+ wire \u_riscv_top.core0_debug[38] ;
+ wire \u_riscv_top.core0_debug[39] ;
+ wire \u_riscv_top.core0_debug[3] ;
+ wire \u_riscv_top.core0_debug[40] ;
+ wire \u_riscv_top.core0_debug[41] ;
+ wire \u_riscv_top.core0_debug[42] ;
+ wire \u_riscv_top.core0_debug[43] ;
+ wire \u_riscv_top.core0_debug[44] ;
+ wire \u_riscv_top.core0_debug[45] ;
+ wire \u_riscv_top.core0_debug[46] ;
+ wire \u_riscv_top.core0_debug[47] ;
+ wire \u_riscv_top.core0_debug[48] ;
+ wire \u_riscv_top.core0_debug[4] ;
+ wire \u_riscv_top.core0_debug[5] ;
+ wire \u_riscv_top.core0_debug[6] ;
+ wire \u_riscv_top.core0_debug[7] ;
+ wire \u_riscv_top.core0_debug[8] ;
+ wire \u_riscv_top.core0_debug[9] ;
+ wire \u_riscv_top.core0_dmem_addr[0] ;
+ wire \u_riscv_top.core0_dmem_addr[10] ;
+ wire \u_riscv_top.core0_dmem_addr[11] ;
+ wire \u_riscv_top.core0_dmem_addr[12] ;
+ wire \u_riscv_top.core0_dmem_addr[13] ;
+ wire \u_riscv_top.core0_dmem_addr[14] ;
+ wire \u_riscv_top.core0_dmem_addr[15] ;
+ wire \u_riscv_top.core0_dmem_addr[16] ;
+ wire \u_riscv_top.core0_dmem_addr[17] ;
+ wire \u_riscv_top.core0_dmem_addr[18] ;
+ wire \u_riscv_top.core0_dmem_addr[19] ;
+ wire \u_riscv_top.core0_dmem_addr[1] ;
+ wire \u_riscv_top.core0_dmem_addr[20] ;
+ wire \u_riscv_top.core0_dmem_addr[21] ;
+ wire \u_riscv_top.core0_dmem_addr[22] ;
+ wire \u_riscv_top.core0_dmem_addr[23] ;
+ wire \u_riscv_top.core0_dmem_addr[24] ;
+ wire \u_riscv_top.core0_dmem_addr[25] ;
+ wire \u_riscv_top.core0_dmem_addr[26] ;
+ wire \u_riscv_top.core0_dmem_addr[27] ;
+ wire \u_riscv_top.core0_dmem_addr[28] ;
+ wire \u_riscv_top.core0_dmem_addr[29] ;
+ wire \u_riscv_top.core0_dmem_addr[2] ;
+ wire \u_riscv_top.core0_dmem_addr[30] ;
+ wire \u_riscv_top.core0_dmem_addr[31] ;
+ wire \u_riscv_top.core0_dmem_addr[3] ;
+ wire \u_riscv_top.core0_dmem_addr[4] ;
+ wire \u_riscv_top.core0_dmem_addr[5] ;
+ wire \u_riscv_top.core0_dmem_addr[6] ;
+ wire \u_riscv_top.core0_dmem_addr[7] ;
+ wire \u_riscv_top.core0_dmem_addr[8] ;
+ wire \u_riscv_top.core0_dmem_addr[9] ;
+ wire \u_riscv_top.core0_dmem_cmd ;
+ wire \u_riscv_top.core0_dmem_rdata[0] ;
+ wire \u_riscv_top.core0_dmem_rdata[10] ;
+ wire \u_riscv_top.core0_dmem_rdata[11] ;
+ wire \u_riscv_top.core0_dmem_rdata[12] ;
+ wire \u_riscv_top.core0_dmem_rdata[13] ;
+ wire \u_riscv_top.core0_dmem_rdata[14] ;
+ wire \u_riscv_top.core0_dmem_rdata[15] ;
+ wire \u_riscv_top.core0_dmem_rdata[16] ;
+ wire \u_riscv_top.core0_dmem_rdata[17] ;
+ wire \u_riscv_top.core0_dmem_rdata[18] ;
+ wire \u_riscv_top.core0_dmem_rdata[19] ;
+ wire \u_riscv_top.core0_dmem_rdata[1] ;
+ wire \u_riscv_top.core0_dmem_rdata[20] ;
+ wire \u_riscv_top.core0_dmem_rdata[21] ;
+ wire \u_riscv_top.core0_dmem_rdata[22] ;
+ wire \u_riscv_top.core0_dmem_rdata[23] ;
+ wire \u_riscv_top.core0_dmem_rdata[24] ;
+ wire \u_riscv_top.core0_dmem_rdata[25] ;
+ wire \u_riscv_top.core0_dmem_rdata[26] ;
+ wire \u_riscv_top.core0_dmem_rdata[27] ;
+ wire \u_riscv_top.core0_dmem_rdata[28] ;
+ wire \u_riscv_top.core0_dmem_rdata[29] ;
+ wire \u_riscv_top.core0_dmem_rdata[2] ;
+ wire \u_riscv_top.core0_dmem_rdata[30] ;
+ wire \u_riscv_top.core0_dmem_rdata[31] ;
+ wire \u_riscv_top.core0_dmem_rdata[3] ;
+ wire \u_riscv_top.core0_dmem_rdata[4] ;
+ wire \u_riscv_top.core0_dmem_rdata[5] ;
+ wire \u_riscv_top.core0_dmem_rdata[6] ;
+ wire \u_riscv_top.core0_dmem_rdata[7] ;
+ wire \u_riscv_top.core0_dmem_rdata[8] ;
+ wire \u_riscv_top.core0_dmem_rdata[9] ;
+ wire \u_riscv_top.core0_dmem_req ;
+ wire \u_riscv_top.core0_dmem_req_ack ;
+ wire \u_riscv_top.core0_dmem_resp[0] ;
+ wire \u_riscv_top.core0_dmem_resp[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[0] ;
+ wire \u_riscv_top.core0_dmem_wdata[10] ;
+ wire \u_riscv_top.core0_dmem_wdata[11] ;
+ wire \u_riscv_top.core0_dmem_wdata[12] ;
+ wire \u_riscv_top.core0_dmem_wdata[13] ;
+ wire \u_riscv_top.core0_dmem_wdata[14] ;
+ wire \u_riscv_top.core0_dmem_wdata[15] ;
+ wire \u_riscv_top.core0_dmem_wdata[16] ;
+ wire \u_riscv_top.core0_dmem_wdata[17] ;
+ wire \u_riscv_top.core0_dmem_wdata[18] ;
+ wire \u_riscv_top.core0_dmem_wdata[19] ;
+ wire \u_riscv_top.core0_dmem_wdata[1] ;
+ wire \u_riscv_top.core0_dmem_wdata[20] ;
+ wire \u_riscv_top.core0_dmem_wdata[21] ;
+ wire \u_riscv_top.core0_dmem_wdata[22] ;
+ wire \u_riscv_top.core0_dmem_wdata[23] ;
+ wire \u_riscv_top.core0_dmem_wdata[24] ;
+ wire \u_riscv_top.core0_dmem_wdata[25] ;
+ wire \u_riscv_top.core0_dmem_wdata[26] ;
+ wire \u_riscv_top.core0_dmem_wdata[27] ;
+ wire \u_riscv_top.core0_dmem_wdata[28] ;
+ wire \u_riscv_top.core0_dmem_wdata[29] ;
+ wire \u_riscv_top.core0_dmem_wdata[2] ;
+ wire \u_riscv_top.core0_dmem_wdata[30] ;
+ wire \u_riscv_top.core0_dmem_wdata[31] ;
+ wire \u_riscv_top.core0_dmem_wdata[3] ;
+ wire \u_riscv_top.core0_dmem_wdata[4] ;
+ wire \u_riscv_top.core0_dmem_wdata[5] ;
+ wire \u_riscv_top.core0_dmem_wdata[6] ;
+ wire \u_riscv_top.core0_dmem_wdata[7] ;
+ wire \u_riscv_top.core0_dmem_wdata[8] ;
+ wire \u_riscv_top.core0_dmem_wdata[9] ;
+ wire \u_riscv_top.core0_dmem_width[0] ;
+ wire \u_riscv_top.core0_dmem_width[1] ;
+ wire \u_riscv_top.core0_imem_addr[0] ;
+ wire \u_riscv_top.core0_imem_addr[10] ;
+ wire \u_riscv_top.core0_imem_addr[11] ;
+ wire \u_riscv_top.core0_imem_addr[12] ;
+ wire \u_riscv_top.core0_imem_addr[13] ;
+ wire \u_riscv_top.core0_imem_addr[14] ;
+ wire \u_riscv_top.core0_imem_addr[15] ;
+ wire \u_riscv_top.core0_imem_addr[16] ;
+ wire \u_riscv_top.core0_imem_addr[17] ;
+ wire \u_riscv_top.core0_imem_addr[18] ;
+ wire \u_riscv_top.core0_imem_addr[19] ;
+ wire \u_riscv_top.core0_imem_addr[1] ;
+ wire \u_riscv_top.core0_imem_addr[20] ;
+ wire \u_riscv_top.core0_imem_addr[21] ;
+ wire \u_riscv_top.core0_imem_addr[22] ;
+ wire \u_riscv_top.core0_imem_addr[23] ;
+ wire \u_riscv_top.core0_imem_addr[24] ;
+ wire \u_riscv_top.core0_imem_addr[25] ;
+ wire \u_riscv_top.core0_imem_addr[26] ;
+ wire \u_riscv_top.core0_imem_addr[27] ;
+ wire \u_riscv_top.core0_imem_addr[28] ;
+ wire \u_riscv_top.core0_imem_addr[29] ;
+ wire \u_riscv_top.core0_imem_addr[2] ;
+ wire \u_riscv_top.core0_imem_addr[30] ;
+ wire \u_riscv_top.core0_imem_addr[31] ;
+ wire \u_riscv_top.core0_imem_addr[3] ;
+ wire \u_riscv_top.core0_imem_addr[4] ;
+ wire \u_riscv_top.core0_imem_addr[5] ;
+ wire \u_riscv_top.core0_imem_addr[6] ;
+ wire \u_riscv_top.core0_imem_addr[7] ;
+ wire \u_riscv_top.core0_imem_addr[8] ;
+ wire \u_riscv_top.core0_imem_addr[9] ;
+ wire \u_riscv_top.core0_imem_bl[0] ;
+ wire \u_riscv_top.core0_imem_bl[1] ;
+ wire \u_riscv_top.core0_imem_bl[2] ;
+ wire \u_riscv_top.core0_imem_cmd ;
+ wire \u_riscv_top.core0_imem_rdata[0] ;
+ wire \u_riscv_top.core0_imem_rdata[10] ;
+ wire \u_riscv_top.core0_imem_rdata[11] ;
+ wire \u_riscv_top.core0_imem_rdata[12] ;
+ wire \u_riscv_top.core0_imem_rdata[13] ;
+ wire \u_riscv_top.core0_imem_rdata[14] ;
+ wire \u_riscv_top.core0_imem_rdata[15] ;
+ wire \u_riscv_top.core0_imem_rdata[16] ;
+ wire \u_riscv_top.core0_imem_rdata[17] ;
+ wire \u_riscv_top.core0_imem_rdata[18] ;
+ wire \u_riscv_top.core0_imem_rdata[19] ;
+ wire \u_riscv_top.core0_imem_rdata[1] ;
+ wire \u_riscv_top.core0_imem_rdata[20] ;
+ wire \u_riscv_top.core0_imem_rdata[21] ;
+ wire \u_riscv_top.core0_imem_rdata[22] ;
+ wire \u_riscv_top.core0_imem_rdata[23] ;
+ wire \u_riscv_top.core0_imem_rdata[24] ;
+ wire \u_riscv_top.core0_imem_rdata[25] ;
+ wire \u_riscv_top.core0_imem_rdata[26] ;
+ wire \u_riscv_top.core0_imem_rdata[27] ;
+ wire \u_riscv_top.core0_imem_rdata[28] ;
+ wire \u_riscv_top.core0_imem_rdata[29] ;
+ wire \u_riscv_top.core0_imem_rdata[2] ;
+ wire \u_riscv_top.core0_imem_rdata[30] ;
+ wire \u_riscv_top.core0_imem_rdata[31] ;
+ wire \u_riscv_top.core0_imem_rdata[3] ;
+ wire \u_riscv_top.core0_imem_rdata[4] ;
+ wire \u_riscv_top.core0_imem_rdata[5] ;
+ wire \u_riscv_top.core0_imem_rdata[6] ;
+ wire \u_riscv_top.core0_imem_rdata[7] ;
+ wire \u_riscv_top.core0_imem_rdata[8] ;
+ wire \u_riscv_top.core0_imem_rdata[9] ;
+ wire \u_riscv_top.core0_imem_req ;
+ wire \u_riscv_top.core0_imem_req_ack ;
+ wire \u_riscv_top.core0_imem_resp[0] ;
+ wire \u_riscv_top.core0_imem_resp[1] ;
+ wire \u_riscv_top.core0_irq_lines[0] ;
+ wire \u_riscv_top.core0_irq_lines[10] ;
+ wire \u_riscv_top.core0_irq_lines[11] ;
+ wire \u_riscv_top.core0_irq_lines[12] ;
+ wire \u_riscv_top.core0_irq_lines[13] ;
+ wire \u_riscv_top.core0_irq_lines[14] ;
+ wire \u_riscv_top.core0_irq_lines[15] ;
+ wire \u_riscv_top.core0_irq_lines[16] ;
+ wire \u_riscv_top.core0_irq_lines[17] ;
+ wire \u_riscv_top.core0_irq_lines[18] ;
+ wire \u_riscv_top.core0_irq_lines[19] ;
+ wire \u_riscv_top.core0_irq_lines[1] ;
+ wire \u_riscv_top.core0_irq_lines[20] ;
+ wire \u_riscv_top.core0_irq_lines[21] ;
+ wire \u_riscv_top.core0_irq_lines[22] ;
+ wire \u_riscv_top.core0_irq_lines[23] ;
+ wire \u_riscv_top.core0_irq_lines[24] ;
+ wire \u_riscv_top.core0_irq_lines[25] ;
+ wire \u_riscv_top.core0_irq_lines[26] ;
+ wire \u_riscv_top.core0_irq_lines[27] ;
+ wire \u_riscv_top.core0_irq_lines[28] ;
+ wire \u_riscv_top.core0_irq_lines[29] ;
+ wire \u_riscv_top.core0_irq_lines[2] ;
+ wire \u_riscv_top.core0_irq_lines[30] ;
+ wire \u_riscv_top.core0_irq_lines[31] ;
+ wire \u_riscv_top.core0_irq_lines[3] ;
+ wire \u_riscv_top.core0_irq_lines[4] ;
+ wire \u_riscv_top.core0_irq_lines[5] ;
+ wire \u_riscv_top.core0_irq_lines[6] ;
+ wire \u_riscv_top.core0_irq_lines[7] ;
+ wire \u_riscv_top.core0_irq_lines[8] ;
+ wire \u_riscv_top.core0_irq_lines[9] ;
+ wire \u_riscv_top.core0_soft_irq ;
+ wire \u_riscv_top.core0_timer_irq ;
+ wire \u_riscv_top.core0_timer_val[0] ;
+ wire \u_riscv_top.core0_timer_val[10] ;
+ wire \u_riscv_top.core0_timer_val[11] ;
+ wire \u_riscv_top.core0_timer_val[12] ;
+ wire \u_riscv_top.core0_timer_val[13] ;
+ wire \u_riscv_top.core0_timer_val[14] ;
+ wire \u_riscv_top.core0_timer_val[15] ;
+ wire \u_riscv_top.core0_timer_val[16] ;
+ wire \u_riscv_top.core0_timer_val[17] ;
+ wire \u_riscv_top.core0_timer_val[18] ;
+ wire \u_riscv_top.core0_timer_val[19] ;
+ wire \u_riscv_top.core0_timer_val[1] ;
+ wire \u_riscv_top.core0_timer_val[20] ;
+ wire \u_riscv_top.core0_timer_val[21] ;
+ wire \u_riscv_top.core0_timer_val[22] ;
+ wire \u_riscv_top.core0_timer_val[23] ;
+ wire \u_riscv_top.core0_timer_val[24] ;
+ wire \u_riscv_top.core0_timer_val[25] ;
+ wire \u_riscv_top.core0_timer_val[26] ;
+ wire \u_riscv_top.core0_timer_val[27] ;
+ wire \u_riscv_top.core0_timer_val[28] ;
+ wire \u_riscv_top.core0_timer_val[29] ;
+ wire \u_riscv_top.core0_timer_val[2] ;
+ wire \u_riscv_top.core0_timer_val[30] ;
+ wire \u_riscv_top.core0_timer_val[31] ;
+ wire \u_riscv_top.core0_timer_val[32] ;
+ wire \u_riscv_top.core0_timer_val[33] ;
+ wire \u_riscv_top.core0_timer_val[34] ;
+ wire \u_riscv_top.core0_timer_val[35] ;
+ wire \u_riscv_top.core0_timer_val[36] ;
+ wire \u_riscv_top.core0_timer_val[37] ;
+ wire \u_riscv_top.core0_timer_val[38] ;
+ wire \u_riscv_top.core0_timer_val[39] ;
+ wire \u_riscv_top.core0_timer_val[3] ;
+ wire \u_riscv_top.core0_timer_val[40] ;
+ wire \u_riscv_top.core0_timer_val[41] ;
+ wire \u_riscv_top.core0_timer_val[42] ;
+ wire \u_riscv_top.core0_timer_val[43] ;
+ wire \u_riscv_top.core0_timer_val[44] ;
+ wire \u_riscv_top.core0_timer_val[45] ;
+ wire \u_riscv_top.core0_timer_val[46] ;
+ wire \u_riscv_top.core0_timer_val[47] ;
+ wire \u_riscv_top.core0_timer_val[48] ;
+ wire \u_riscv_top.core0_timer_val[49] ;
+ wire \u_riscv_top.core0_timer_val[4] ;
+ wire \u_riscv_top.core0_timer_val[50] ;
+ wire \u_riscv_top.core0_timer_val[51] ;
+ wire \u_riscv_top.core0_timer_val[52] ;
+ wire \u_riscv_top.core0_timer_val[53] ;
+ wire \u_riscv_top.core0_timer_val[54] ;
+ wire \u_riscv_top.core0_timer_val[55] ;
+ wire \u_riscv_top.core0_timer_val[56] ;
+ wire \u_riscv_top.core0_timer_val[57] ;
+ wire \u_riscv_top.core0_timer_val[58] ;
+ wire \u_riscv_top.core0_timer_val[59] ;
+ wire \u_riscv_top.core0_timer_val[5] ;
+ wire \u_riscv_top.core0_timer_val[60] ;
+ wire \u_riscv_top.core0_timer_val[61] ;
+ wire \u_riscv_top.core0_timer_val[62] ;
+ wire \u_riscv_top.core0_timer_val[63] ;
+ wire \u_riscv_top.core0_timer_val[6] ;
+ wire \u_riscv_top.core0_timer_val[7] ;
+ wire \u_riscv_top.core0_timer_val[8] ;
+ wire \u_riscv_top.core0_timer_val[9] ;
+ wire \u_riscv_top.core0_uid[0] ;
+ wire \u_riscv_top.core0_uid[1] ;
+ wire \u_riscv_top.core1_debug[0] ;
+ wire \u_riscv_top.core1_debug[10] ;
+ wire \u_riscv_top.core1_debug[11] ;
+ wire \u_riscv_top.core1_debug[12] ;
+ wire \u_riscv_top.core1_debug[13] ;
+ wire \u_riscv_top.core1_debug[14] ;
+ wire \u_riscv_top.core1_debug[15] ;
+ wire \u_riscv_top.core1_debug[16] ;
+ wire \u_riscv_top.core1_debug[17] ;
+ wire \u_riscv_top.core1_debug[18] ;
+ wire \u_riscv_top.core1_debug[19] ;
+ wire \u_riscv_top.core1_debug[1] ;
+ wire \u_riscv_top.core1_debug[20] ;
+ wire \u_riscv_top.core1_debug[21] ;
+ wire \u_riscv_top.core1_debug[22] ;
+ wire \u_riscv_top.core1_debug[23] ;
+ wire \u_riscv_top.core1_debug[24] ;
+ wire \u_riscv_top.core1_debug[25] ;
+ wire \u_riscv_top.core1_debug[26] ;
+ wire \u_riscv_top.core1_debug[27] ;
+ wire \u_riscv_top.core1_debug[28] ;
+ wire \u_riscv_top.core1_debug[29] ;
+ wire \u_riscv_top.core1_debug[2] ;
+ wire \u_riscv_top.core1_debug[30] ;
+ wire \u_riscv_top.core1_debug[31] ;
+ wire \u_riscv_top.core1_debug[32] ;
+ wire \u_riscv_top.core1_debug[33] ;
+ wire \u_riscv_top.core1_debug[34] ;
+ wire \u_riscv_top.core1_debug[35] ;
+ wire \u_riscv_top.core1_debug[36] ;
+ wire \u_riscv_top.core1_debug[37] ;
+ wire \u_riscv_top.core1_debug[38] ;
+ wire \u_riscv_top.core1_debug[39] ;
+ wire \u_riscv_top.core1_debug[3] ;
+ wire \u_riscv_top.core1_debug[40] ;
+ wire \u_riscv_top.core1_debug[41] ;
+ wire \u_riscv_top.core1_debug[42] ;
+ wire \u_riscv_top.core1_debug[43] ;
+ wire \u_riscv_top.core1_debug[44] ;
+ wire \u_riscv_top.core1_debug[45] ;
+ wire \u_riscv_top.core1_debug[46] ;
+ wire \u_riscv_top.core1_debug[47] ;
+ wire \u_riscv_top.core1_debug[48] ;
+ wire \u_riscv_top.core1_debug[4] ;
+ wire \u_riscv_top.core1_debug[5] ;
+ wire \u_riscv_top.core1_debug[6] ;
+ wire \u_riscv_top.core1_debug[7] ;
+ wire \u_riscv_top.core1_debug[8] ;
+ wire \u_riscv_top.core1_debug[9] ;
+ wire \u_riscv_top.core1_dmem_addr[0] ;
+ wire \u_riscv_top.core1_dmem_addr[10] ;
+ wire \u_riscv_top.core1_dmem_addr[11] ;
+ wire \u_riscv_top.core1_dmem_addr[12] ;
+ wire \u_riscv_top.core1_dmem_addr[13] ;
+ wire \u_riscv_top.core1_dmem_addr[14] ;
+ wire \u_riscv_top.core1_dmem_addr[15] ;
+ wire \u_riscv_top.core1_dmem_addr[16] ;
+ wire \u_riscv_top.core1_dmem_addr[17] ;
+ wire \u_riscv_top.core1_dmem_addr[18] ;
+ wire \u_riscv_top.core1_dmem_addr[19] ;
+ wire \u_riscv_top.core1_dmem_addr[1] ;
+ wire \u_riscv_top.core1_dmem_addr[20] ;
+ wire \u_riscv_top.core1_dmem_addr[21] ;
+ wire \u_riscv_top.core1_dmem_addr[22] ;
+ wire \u_riscv_top.core1_dmem_addr[23] ;
+ wire \u_riscv_top.core1_dmem_addr[24] ;
+ wire \u_riscv_top.core1_dmem_addr[25] ;
+ wire \u_riscv_top.core1_dmem_addr[26] ;
+ wire \u_riscv_top.core1_dmem_addr[27] ;
+ wire \u_riscv_top.core1_dmem_addr[28] ;
+ wire \u_riscv_top.core1_dmem_addr[29] ;
+ wire \u_riscv_top.core1_dmem_addr[2] ;
+ wire \u_riscv_top.core1_dmem_addr[30] ;
+ wire \u_riscv_top.core1_dmem_addr[31] ;
+ wire \u_riscv_top.core1_dmem_addr[3] ;
+ wire \u_riscv_top.core1_dmem_addr[4] ;
+ wire \u_riscv_top.core1_dmem_addr[5] ;
+ wire \u_riscv_top.core1_dmem_addr[6] ;
+ wire \u_riscv_top.core1_dmem_addr[7] ;
+ wire \u_riscv_top.core1_dmem_addr[8] ;
+ wire \u_riscv_top.core1_dmem_addr[9] ;
+ wire \u_riscv_top.core1_dmem_cmd ;
+ wire \u_riscv_top.core1_dmem_rdata[0] ;
+ wire \u_riscv_top.core1_dmem_rdata[10] ;
+ wire \u_riscv_top.core1_dmem_rdata[11] ;
+ wire \u_riscv_top.core1_dmem_rdata[12] ;
+ wire \u_riscv_top.core1_dmem_rdata[13] ;
+ wire \u_riscv_top.core1_dmem_rdata[14] ;
+ wire \u_riscv_top.core1_dmem_rdata[15] ;
+ wire \u_riscv_top.core1_dmem_rdata[16] ;
+ wire \u_riscv_top.core1_dmem_rdata[17] ;
+ wire \u_riscv_top.core1_dmem_rdata[18] ;
+ wire \u_riscv_top.core1_dmem_rdata[19] ;
+ wire \u_riscv_top.core1_dmem_rdata[1] ;
+ wire \u_riscv_top.core1_dmem_rdata[20] ;
+ wire \u_riscv_top.core1_dmem_rdata[21] ;
+ wire \u_riscv_top.core1_dmem_rdata[22] ;
+ wire \u_riscv_top.core1_dmem_rdata[23] ;
+ wire \u_riscv_top.core1_dmem_rdata[24] ;
+ wire \u_riscv_top.core1_dmem_rdata[25] ;
+ wire \u_riscv_top.core1_dmem_rdata[26] ;
+ wire \u_riscv_top.core1_dmem_rdata[27] ;
+ wire \u_riscv_top.core1_dmem_rdata[28] ;
+ wire \u_riscv_top.core1_dmem_rdata[29] ;
+ wire \u_riscv_top.core1_dmem_rdata[2] ;
+ wire \u_riscv_top.core1_dmem_rdata[30] ;
+ wire \u_riscv_top.core1_dmem_rdata[31] ;
+ wire \u_riscv_top.core1_dmem_rdata[3] ;
+ wire \u_riscv_top.core1_dmem_rdata[4] ;
+ wire \u_riscv_top.core1_dmem_rdata[5] ;
+ wire \u_riscv_top.core1_dmem_rdata[6] ;
+ wire \u_riscv_top.core1_dmem_rdata[7] ;
+ wire \u_riscv_top.core1_dmem_rdata[8] ;
+ wire \u_riscv_top.core1_dmem_rdata[9] ;
+ wire \u_riscv_top.core1_dmem_req ;
+ wire \u_riscv_top.core1_dmem_req_ack ;
+ wire \u_riscv_top.core1_dmem_resp[0] ;
+ wire \u_riscv_top.core1_dmem_resp[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[0] ;
+ wire \u_riscv_top.core1_dmem_wdata[10] ;
+ wire \u_riscv_top.core1_dmem_wdata[11] ;
+ wire \u_riscv_top.core1_dmem_wdata[12] ;
+ wire \u_riscv_top.core1_dmem_wdata[13] ;
+ wire \u_riscv_top.core1_dmem_wdata[14] ;
+ wire \u_riscv_top.core1_dmem_wdata[15] ;
+ wire \u_riscv_top.core1_dmem_wdata[16] ;
+ wire \u_riscv_top.core1_dmem_wdata[17] ;
+ wire \u_riscv_top.core1_dmem_wdata[18] ;
+ wire \u_riscv_top.core1_dmem_wdata[19] ;
+ wire \u_riscv_top.core1_dmem_wdata[1] ;
+ wire \u_riscv_top.core1_dmem_wdata[20] ;
+ wire \u_riscv_top.core1_dmem_wdata[21] ;
+ wire \u_riscv_top.core1_dmem_wdata[22] ;
+ wire \u_riscv_top.core1_dmem_wdata[23] ;
+ wire \u_riscv_top.core1_dmem_wdata[24] ;
+ wire \u_riscv_top.core1_dmem_wdata[25] ;
+ wire \u_riscv_top.core1_dmem_wdata[26] ;
+ wire \u_riscv_top.core1_dmem_wdata[27] ;
+ wire \u_riscv_top.core1_dmem_wdata[28] ;
+ wire \u_riscv_top.core1_dmem_wdata[29] ;
+ wire \u_riscv_top.core1_dmem_wdata[2] ;
+ wire \u_riscv_top.core1_dmem_wdata[30] ;
+ wire \u_riscv_top.core1_dmem_wdata[31] ;
+ wire \u_riscv_top.core1_dmem_wdata[3] ;
+ wire \u_riscv_top.core1_dmem_wdata[4] ;
+ wire \u_riscv_top.core1_dmem_wdata[5] ;
+ wire \u_riscv_top.core1_dmem_wdata[6] ;
+ wire \u_riscv_top.core1_dmem_wdata[7] ;
+ wire \u_riscv_top.core1_dmem_wdata[8] ;
+ wire \u_riscv_top.core1_dmem_wdata[9] ;
+ wire \u_riscv_top.core1_dmem_width[0] ;
+ wire \u_riscv_top.core1_dmem_width[1] ;
+ wire \u_riscv_top.core1_imem_addr[0] ;
+ wire \u_riscv_top.core1_imem_addr[10] ;
+ wire \u_riscv_top.core1_imem_addr[11] ;
+ wire \u_riscv_top.core1_imem_addr[12] ;
+ wire \u_riscv_top.core1_imem_addr[13] ;
+ wire \u_riscv_top.core1_imem_addr[14] ;
+ wire \u_riscv_top.core1_imem_addr[15] ;
+ wire \u_riscv_top.core1_imem_addr[16] ;
+ wire \u_riscv_top.core1_imem_addr[17] ;
+ wire \u_riscv_top.core1_imem_addr[18] ;
+ wire \u_riscv_top.core1_imem_addr[19] ;
+ wire \u_riscv_top.core1_imem_addr[1] ;
+ wire \u_riscv_top.core1_imem_addr[20] ;
+ wire \u_riscv_top.core1_imem_addr[21] ;
+ wire \u_riscv_top.core1_imem_addr[22] ;
+ wire \u_riscv_top.core1_imem_addr[23] ;
+ wire \u_riscv_top.core1_imem_addr[24] ;
+ wire \u_riscv_top.core1_imem_addr[25] ;
+ wire \u_riscv_top.core1_imem_addr[26] ;
+ wire \u_riscv_top.core1_imem_addr[27] ;
+ wire \u_riscv_top.core1_imem_addr[28] ;
+ wire \u_riscv_top.core1_imem_addr[29] ;
+ wire \u_riscv_top.core1_imem_addr[2] ;
+ wire \u_riscv_top.core1_imem_addr[30] ;
+ wire \u_riscv_top.core1_imem_addr[31] ;
+ wire \u_riscv_top.core1_imem_addr[3] ;
+ wire \u_riscv_top.core1_imem_addr[4] ;
+ wire \u_riscv_top.core1_imem_addr[5] ;
+ wire \u_riscv_top.core1_imem_addr[6] ;
+ wire \u_riscv_top.core1_imem_addr[7] ;
+ wire \u_riscv_top.core1_imem_addr[8] ;
+ wire \u_riscv_top.core1_imem_addr[9] ;
+ wire \u_riscv_top.core1_imem_bl[0] ;
+ wire \u_riscv_top.core1_imem_bl[1] ;
+ wire \u_riscv_top.core1_imem_bl[2] ;
+ wire \u_riscv_top.core1_imem_cmd ;
+ wire \u_riscv_top.core1_imem_rdata[0] ;
+ wire \u_riscv_top.core1_imem_rdata[10] ;
+ wire \u_riscv_top.core1_imem_rdata[11] ;
+ wire \u_riscv_top.core1_imem_rdata[12] ;
+ wire \u_riscv_top.core1_imem_rdata[13] ;
+ wire \u_riscv_top.core1_imem_rdata[14] ;
+ wire \u_riscv_top.core1_imem_rdata[15] ;
+ wire \u_riscv_top.core1_imem_rdata[16] ;
+ wire \u_riscv_top.core1_imem_rdata[17] ;
+ wire \u_riscv_top.core1_imem_rdata[18] ;
+ wire \u_riscv_top.core1_imem_rdata[19] ;
+ wire \u_riscv_top.core1_imem_rdata[1] ;
+ wire \u_riscv_top.core1_imem_rdata[20] ;
+ wire \u_riscv_top.core1_imem_rdata[21] ;
+ wire \u_riscv_top.core1_imem_rdata[22] ;
+ wire \u_riscv_top.core1_imem_rdata[23] ;
+ wire \u_riscv_top.core1_imem_rdata[24] ;
+ wire \u_riscv_top.core1_imem_rdata[25] ;
+ wire \u_riscv_top.core1_imem_rdata[26] ;
+ wire \u_riscv_top.core1_imem_rdata[27] ;
+ wire \u_riscv_top.core1_imem_rdata[28] ;
+ wire \u_riscv_top.core1_imem_rdata[29] ;
+ wire \u_riscv_top.core1_imem_rdata[2] ;
+ wire \u_riscv_top.core1_imem_rdata[30] ;
+ wire \u_riscv_top.core1_imem_rdata[31] ;
+ wire \u_riscv_top.core1_imem_rdata[3] ;
+ wire \u_riscv_top.core1_imem_rdata[4] ;
+ wire \u_riscv_top.core1_imem_rdata[5] ;
+ wire \u_riscv_top.core1_imem_rdata[6] ;
+ wire \u_riscv_top.core1_imem_rdata[7] ;
+ wire \u_riscv_top.core1_imem_rdata[8] ;
+ wire \u_riscv_top.core1_imem_rdata[9] ;
+ wire \u_riscv_top.core1_imem_req ;
+ wire \u_riscv_top.core1_imem_req_ack ;
+ wire \u_riscv_top.core1_imem_resp[0] ;
+ wire \u_riscv_top.core1_imem_resp[1] ;
+ wire \u_riscv_top.core1_irq_lines[0] ;
+ wire \u_riscv_top.core1_irq_lines[10] ;
+ wire \u_riscv_top.core1_irq_lines[11] ;
+ wire \u_riscv_top.core1_irq_lines[12] ;
+ wire \u_riscv_top.core1_irq_lines[13] ;
+ wire \u_riscv_top.core1_irq_lines[14] ;
+ wire \u_riscv_top.core1_irq_lines[15] ;
+ wire \u_riscv_top.core1_irq_lines[16] ;
+ wire \u_riscv_top.core1_irq_lines[17] ;
+ wire \u_riscv_top.core1_irq_lines[18] ;
+ wire \u_riscv_top.core1_irq_lines[19] ;
+ wire \u_riscv_top.core1_irq_lines[1] ;
+ wire \u_riscv_top.core1_irq_lines[20] ;
+ wire \u_riscv_top.core1_irq_lines[21] ;
+ wire \u_riscv_top.core1_irq_lines[22] ;
+ wire \u_riscv_top.core1_irq_lines[23] ;
+ wire \u_riscv_top.core1_irq_lines[24] ;
+ wire \u_riscv_top.core1_irq_lines[25] ;
+ wire \u_riscv_top.core1_irq_lines[26] ;
+ wire \u_riscv_top.core1_irq_lines[27] ;
+ wire \u_riscv_top.core1_irq_lines[28] ;
+ wire \u_riscv_top.core1_irq_lines[29] ;
+ wire \u_riscv_top.core1_irq_lines[2] ;
+ wire \u_riscv_top.core1_irq_lines[30] ;
+ wire \u_riscv_top.core1_irq_lines[31] ;
+ wire \u_riscv_top.core1_irq_lines[3] ;
+ wire \u_riscv_top.core1_irq_lines[4] ;
+ wire \u_riscv_top.core1_irq_lines[5] ;
+ wire \u_riscv_top.core1_irq_lines[6] ;
+ wire \u_riscv_top.core1_irq_lines[7] ;
+ wire \u_riscv_top.core1_irq_lines[8] ;
+ wire \u_riscv_top.core1_irq_lines[9] ;
+ wire \u_riscv_top.core1_soft_irq ;
+ wire \u_riscv_top.core1_timer_irq ;
+ wire \u_riscv_top.core1_timer_val[0] ;
+ wire \u_riscv_top.core1_timer_val[10] ;
+ wire \u_riscv_top.core1_timer_val[11] ;
+ wire \u_riscv_top.core1_timer_val[12] ;
+ wire \u_riscv_top.core1_timer_val[13] ;
+ wire \u_riscv_top.core1_timer_val[14] ;
+ wire \u_riscv_top.core1_timer_val[15] ;
+ wire \u_riscv_top.core1_timer_val[16] ;
+ wire \u_riscv_top.core1_timer_val[17] ;
+ wire \u_riscv_top.core1_timer_val[18] ;
+ wire \u_riscv_top.core1_timer_val[19] ;
+ wire \u_riscv_top.core1_timer_val[1] ;
+ wire \u_riscv_top.core1_timer_val[20] ;
+ wire \u_riscv_top.core1_timer_val[21] ;
+ wire \u_riscv_top.core1_timer_val[22] ;
+ wire \u_riscv_top.core1_timer_val[23] ;
+ wire \u_riscv_top.core1_timer_val[24] ;
+ wire \u_riscv_top.core1_timer_val[25] ;
+ wire \u_riscv_top.core1_timer_val[26] ;
+ wire \u_riscv_top.core1_timer_val[27] ;
+ wire \u_riscv_top.core1_timer_val[28] ;
+ wire \u_riscv_top.core1_timer_val[29] ;
+ wire \u_riscv_top.core1_timer_val[2] ;
+ wire \u_riscv_top.core1_timer_val[30] ;
+ wire \u_riscv_top.core1_timer_val[31] ;
+ wire \u_riscv_top.core1_timer_val[32] ;
+ wire \u_riscv_top.core1_timer_val[33] ;
+ wire \u_riscv_top.core1_timer_val[34] ;
+ wire \u_riscv_top.core1_timer_val[35] ;
+ wire \u_riscv_top.core1_timer_val[36] ;
+ wire \u_riscv_top.core1_timer_val[37] ;
+ wire \u_riscv_top.core1_timer_val[38] ;
+ wire \u_riscv_top.core1_timer_val[39] ;
+ wire \u_riscv_top.core1_timer_val[3] ;
+ wire \u_riscv_top.core1_timer_val[40] ;
+ wire \u_riscv_top.core1_timer_val[41] ;
+ wire \u_riscv_top.core1_timer_val[42] ;
+ wire \u_riscv_top.core1_timer_val[43] ;
+ wire \u_riscv_top.core1_timer_val[44] ;
+ wire \u_riscv_top.core1_timer_val[45] ;
+ wire \u_riscv_top.core1_timer_val[46] ;
+ wire \u_riscv_top.core1_timer_val[47] ;
+ wire \u_riscv_top.core1_timer_val[48] ;
+ wire \u_riscv_top.core1_timer_val[49] ;
+ wire \u_riscv_top.core1_timer_val[4] ;
+ wire \u_riscv_top.core1_timer_val[50] ;
+ wire \u_riscv_top.core1_timer_val[51] ;
+ wire \u_riscv_top.core1_timer_val[52] ;
+ wire \u_riscv_top.core1_timer_val[53] ;
+ wire \u_riscv_top.core1_timer_val[54] ;
+ wire \u_riscv_top.core1_timer_val[55] ;
+ wire \u_riscv_top.core1_timer_val[56] ;
+ wire \u_riscv_top.core1_timer_val[57] ;
+ wire \u_riscv_top.core1_timer_val[58] ;
+ wire \u_riscv_top.core1_timer_val[59] ;
+ wire \u_riscv_top.core1_timer_val[5] ;
+ wire \u_riscv_top.core1_timer_val[60] ;
+ wire \u_riscv_top.core1_timer_val[61] ;
+ wire \u_riscv_top.core1_timer_val[62] ;
+ wire \u_riscv_top.core1_timer_val[63] ;
+ wire \u_riscv_top.core1_timer_val[6] ;
+ wire \u_riscv_top.core1_timer_val[7] ;
+ wire \u_riscv_top.core1_timer_val[8] ;
+ wire \u_riscv_top.core1_timer_val[9] ;
+ wire \u_riscv_top.core1_uid[0] ;
+ wire \u_riscv_top.core1_uid[1] ;
+ wire \u_riscv_top.core_clk_core0_skew ;
+ wire \u_riscv_top.core_clk_core1_skew ;
+ wire \u_riscv_top.core_clk_icon_skew ;
+ wire \u_riscv_top.core_clk_int[0] ;
+ wire \u_riscv_top.core_clk_int[1] ;
+ wire \u_riscv_top.core_clk_int[2] ;
+ wire \u_riscv_top.core_clk_int[3] ;
+ wire \u_riscv_top.core_clk_int[4] ;
+ wire \u_riscv_top.core_clk_int[5] ;
+ wire \u_riscv_top.core_clk_intf_skew ;
+ wire \u_riscv_top.core_clk_out[0] ;
+ wire \u_riscv_top.core_clk_out[1] ;
+ wire \u_riscv_top.core_dcache_addr[0] ;
+ wire \u_riscv_top.core_dcache_addr[10] ;
+ wire \u_riscv_top.core_dcache_addr[11] ;
+ wire \u_riscv_top.core_dcache_addr[12] ;
+ wire \u_riscv_top.core_dcache_addr[13] ;
+ wire \u_riscv_top.core_dcache_addr[14] ;
+ wire \u_riscv_top.core_dcache_addr[15] ;
+ wire \u_riscv_top.core_dcache_addr[16] ;
+ wire \u_riscv_top.core_dcache_addr[17] ;
+ wire \u_riscv_top.core_dcache_addr[18] ;
+ wire \u_riscv_top.core_dcache_addr[19] ;
+ wire \u_riscv_top.core_dcache_addr[1] ;
+ wire \u_riscv_top.core_dcache_addr[20] ;
+ wire \u_riscv_top.core_dcache_addr[21] ;
+ wire \u_riscv_top.core_dcache_addr[22] ;
+ wire \u_riscv_top.core_dcache_addr[23] ;
+ wire \u_riscv_top.core_dcache_addr[24] ;
+ wire \u_riscv_top.core_dcache_addr[25] ;
+ wire \u_riscv_top.core_dcache_addr[26] ;
+ wire \u_riscv_top.core_dcache_addr[27] ;
+ wire \u_riscv_top.core_dcache_addr[28] ;
+ wire \u_riscv_top.core_dcache_addr[29] ;
+ wire \u_riscv_top.core_dcache_addr[2] ;
+ wire \u_riscv_top.core_dcache_addr[30] ;
+ wire \u_riscv_top.core_dcache_addr[31] ;
+ wire \u_riscv_top.core_dcache_addr[3] ;
+ wire \u_riscv_top.core_dcache_addr[4] ;
+ wire \u_riscv_top.core_dcache_addr[5] ;
+ wire \u_riscv_top.core_dcache_addr[6] ;
+ wire \u_riscv_top.core_dcache_addr[7] ;
+ wire \u_riscv_top.core_dcache_addr[8] ;
+ wire \u_riscv_top.core_dcache_addr[9] ;
+ wire \u_riscv_top.core_dcache_cmd ;
+ wire \u_riscv_top.core_dcache_rdata[0] ;
+ wire \u_riscv_top.core_dcache_rdata[10] ;
+ wire \u_riscv_top.core_dcache_rdata[11] ;
+ wire \u_riscv_top.core_dcache_rdata[12] ;
+ wire \u_riscv_top.core_dcache_rdata[13] ;
+ wire \u_riscv_top.core_dcache_rdata[14] ;
+ wire \u_riscv_top.core_dcache_rdata[15] ;
+ wire \u_riscv_top.core_dcache_rdata[16] ;
+ wire \u_riscv_top.core_dcache_rdata[17] ;
+ wire \u_riscv_top.core_dcache_rdata[18] ;
+ wire \u_riscv_top.core_dcache_rdata[19] ;
+ wire \u_riscv_top.core_dcache_rdata[1] ;
+ wire \u_riscv_top.core_dcache_rdata[20] ;
+ wire \u_riscv_top.core_dcache_rdata[21] ;
+ wire \u_riscv_top.core_dcache_rdata[22] ;
+ wire \u_riscv_top.core_dcache_rdata[23] ;
+ wire \u_riscv_top.core_dcache_rdata[24] ;
+ wire \u_riscv_top.core_dcache_rdata[25] ;
+ wire \u_riscv_top.core_dcache_rdata[26] ;
+ wire \u_riscv_top.core_dcache_rdata[27] ;
+ wire \u_riscv_top.core_dcache_rdata[28] ;
+ wire \u_riscv_top.core_dcache_rdata[29] ;
+ wire \u_riscv_top.core_dcache_rdata[2] ;
+ wire \u_riscv_top.core_dcache_rdata[30] ;
+ wire \u_riscv_top.core_dcache_rdata[31] ;
+ wire \u_riscv_top.core_dcache_rdata[3] ;
+ wire \u_riscv_top.core_dcache_rdata[4] ;
+ wire \u_riscv_top.core_dcache_rdata[5] ;
+ wire \u_riscv_top.core_dcache_rdata[6] ;
+ wire \u_riscv_top.core_dcache_rdata[7] ;
+ wire \u_riscv_top.core_dcache_rdata[8] ;
+ wire \u_riscv_top.core_dcache_rdata[9] ;
+ wire \u_riscv_top.core_dcache_req ;
+ wire \u_riscv_top.core_dcache_req_ack ;
+ wire \u_riscv_top.core_dcache_resp[0] ;
+ wire \u_riscv_top.core_dcache_resp[1] ;
+ wire \u_riscv_top.core_dcache_wdata[0] ;
+ wire \u_riscv_top.core_dcache_wdata[10] ;
+ wire \u_riscv_top.core_dcache_wdata[11] ;
+ wire \u_riscv_top.core_dcache_wdata[12] ;
+ wire \u_riscv_top.core_dcache_wdata[13] ;
+ wire \u_riscv_top.core_dcache_wdata[14] ;
+ wire \u_riscv_top.core_dcache_wdata[15] ;
+ wire \u_riscv_top.core_dcache_wdata[16] ;
+ wire \u_riscv_top.core_dcache_wdata[17] ;
+ wire \u_riscv_top.core_dcache_wdata[18] ;
+ wire \u_riscv_top.core_dcache_wdata[19] ;
+ wire \u_riscv_top.core_dcache_wdata[1] ;
+ wire \u_riscv_top.core_dcache_wdata[20] ;
+ wire \u_riscv_top.core_dcache_wdata[21] ;
+ wire \u_riscv_top.core_dcache_wdata[22] ;
+ wire \u_riscv_top.core_dcache_wdata[23] ;
+ wire \u_riscv_top.core_dcache_wdata[24] ;
+ wire \u_riscv_top.core_dcache_wdata[25] ;
+ wire \u_riscv_top.core_dcache_wdata[26] ;
+ wire \u_riscv_top.core_dcache_wdata[27] ;
+ wire \u_riscv_top.core_dcache_wdata[28] ;
+ wire \u_riscv_top.core_dcache_wdata[29] ;
+ wire \u_riscv_top.core_dcache_wdata[2] ;
+ wire \u_riscv_top.core_dcache_wdata[30] ;
+ wire \u_riscv_top.core_dcache_wdata[31] ;
+ wire \u_riscv_top.core_dcache_wdata[3] ;
+ wire \u_riscv_top.core_dcache_wdata[4] ;
+ wire \u_riscv_top.core_dcache_wdata[5] ;
+ wire \u_riscv_top.core_dcache_wdata[6] ;
+ wire \u_riscv_top.core_dcache_wdata[7] ;
+ wire \u_riscv_top.core_dcache_wdata[8] ;
+ wire \u_riscv_top.core_dcache_wdata[9] ;
+ wire \u_riscv_top.core_dcache_width[0] ;
+ wire \u_riscv_top.core_dcache_width[1] ;
+ wire \u_riscv_top.core_dmem_addr[0] ;
+ wire \u_riscv_top.core_dmem_addr[10] ;
+ wire \u_riscv_top.core_dmem_addr[11] ;
+ wire \u_riscv_top.core_dmem_addr[12] ;
+ wire \u_riscv_top.core_dmem_addr[13] ;
+ wire \u_riscv_top.core_dmem_addr[14] ;
+ wire \u_riscv_top.core_dmem_addr[15] ;
+ wire \u_riscv_top.core_dmem_addr[16] ;
+ wire \u_riscv_top.core_dmem_addr[17] ;
+ wire \u_riscv_top.core_dmem_addr[18] ;
+ wire \u_riscv_top.core_dmem_addr[19] ;
+ wire \u_riscv_top.core_dmem_addr[1] ;
+ wire \u_riscv_top.core_dmem_addr[20] ;
+ wire \u_riscv_top.core_dmem_addr[21] ;
+ wire \u_riscv_top.core_dmem_addr[22] ;
+ wire \u_riscv_top.core_dmem_addr[23] ;
+ wire \u_riscv_top.core_dmem_addr[24] ;
+ wire \u_riscv_top.core_dmem_addr[25] ;
+ wire \u_riscv_top.core_dmem_addr[26] ;
+ wire \u_riscv_top.core_dmem_addr[27] ;
+ wire \u_riscv_top.core_dmem_addr[28] ;
+ wire \u_riscv_top.core_dmem_addr[29] ;
+ wire \u_riscv_top.core_dmem_addr[2] ;
+ wire \u_riscv_top.core_dmem_addr[30] ;
+ wire \u_riscv_top.core_dmem_addr[31] ;
+ wire \u_riscv_top.core_dmem_addr[3] ;
+ wire \u_riscv_top.core_dmem_addr[4] ;
+ wire \u_riscv_top.core_dmem_addr[5] ;
+ wire \u_riscv_top.core_dmem_addr[6] ;
+ wire \u_riscv_top.core_dmem_addr[7] ;
+ wire \u_riscv_top.core_dmem_addr[8] ;
+ wire \u_riscv_top.core_dmem_addr[9] ;
+ wire \u_riscv_top.core_dmem_bl[0] ;
+ wire \u_riscv_top.core_dmem_bl[1] ;
+ wire \u_riscv_top.core_dmem_bl[2] ;
+ wire \u_riscv_top.core_dmem_cmd ;
+ wire \u_riscv_top.core_dmem_rdata[0] ;
+ wire \u_riscv_top.core_dmem_rdata[10] ;
+ wire \u_riscv_top.core_dmem_rdata[11] ;
+ wire \u_riscv_top.core_dmem_rdata[12] ;
+ wire \u_riscv_top.core_dmem_rdata[13] ;
+ wire \u_riscv_top.core_dmem_rdata[14] ;
+ wire \u_riscv_top.core_dmem_rdata[15] ;
+ wire \u_riscv_top.core_dmem_rdata[16] ;
+ wire \u_riscv_top.core_dmem_rdata[17] ;
+ wire \u_riscv_top.core_dmem_rdata[18] ;
+ wire \u_riscv_top.core_dmem_rdata[19] ;
+ wire \u_riscv_top.core_dmem_rdata[1] ;
+ wire \u_riscv_top.core_dmem_rdata[20] ;
+ wire \u_riscv_top.core_dmem_rdata[21] ;
+ wire \u_riscv_top.core_dmem_rdata[22] ;
+ wire \u_riscv_top.core_dmem_rdata[23] ;
+ wire \u_riscv_top.core_dmem_rdata[24] ;
+ wire \u_riscv_top.core_dmem_rdata[25] ;
+ wire \u_riscv_top.core_dmem_rdata[26] ;
+ wire \u_riscv_top.core_dmem_rdata[27] ;
+ wire \u_riscv_top.core_dmem_rdata[28] ;
+ wire \u_riscv_top.core_dmem_rdata[29] ;
+ wire \u_riscv_top.core_dmem_rdata[2] ;
+ wire \u_riscv_top.core_dmem_rdata[30] ;
+ wire \u_riscv_top.core_dmem_rdata[31] ;
+ wire \u_riscv_top.core_dmem_rdata[3] ;
+ wire \u_riscv_top.core_dmem_rdata[4] ;
+ wire \u_riscv_top.core_dmem_rdata[5] ;
+ wire \u_riscv_top.core_dmem_rdata[6] ;
+ wire \u_riscv_top.core_dmem_rdata[7] ;
+ wire \u_riscv_top.core_dmem_rdata[8] ;
+ wire \u_riscv_top.core_dmem_rdata[9] ;
+ wire \u_riscv_top.core_dmem_req ;
+ wire \u_riscv_top.core_dmem_req_ack ;
+ wire \u_riscv_top.core_dmem_resp[0] ;
+ wire \u_riscv_top.core_dmem_resp[1] ;
+ wire \u_riscv_top.core_dmem_wdata[0] ;
+ wire \u_riscv_top.core_dmem_wdata[10] ;
+ wire \u_riscv_top.core_dmem_wdata[11] ;
+ wire \u_riscv_top.core_dmem_wdata[12] ;
+ wire \u_riscv_top.core_dmem_wdata[13] ;
+ wire \u_riscv_top.core_dmem_wdata[14] ;
+ wire \u_riscv_top.core_dmem_wdata[15] ;
+ wire \u_riscv_top.core_dmem_wdata[16] ;
+ wire \u_riscv_top.core_dmem_wdata[17] ;
+ wire \u_riscv_top.core_dmem_wdata[18] ;
+ wire \u_riscv_top.core_dmem_wdata[19] ;
+ wire \u_riscv_top.core_dmem_wdata[1] ;
+ wire \u_riscv_top.core_dmem_wdata[20] ;
+ wire \u_riscv_top.core_dmem_wdata[21] ;
+ wire \u_riscv_top.core_dmem_wdata[22] ;
+ wire \u_riscv_top.core_dmem_wdata[23] ;
+ wire \u_riscv_top.core_dmem_wdata[24] ;
+ wire \u_riscv_top.core_dmem_wdata[25] ;
+ wire \u_riscv_top.core_dmem_wdata[26] ;
+ wire \u_riscv_top.core_dmem_wdata[27] ;
+ wire \u_riscv_top.core_dmem_wdata[28] ;
+ wire \u_riscv_top.core_dmem_wdata[29] ;
+ wire \u_riscv_top.core_dmem_wdata[2] ;
+ wire \u_riscv_top.core_dmem_wdata[30] ;
+ wire \u_riscv_top.core_dmem_wdata[31] ;
+ wire \u_riscv_top.core_dmem_wdata[3] ;
+ wire \u_riscv_top.core_dmem_wdata[4] ;
+ wire \u_riscv_top.core_dmem_wdata[5] ;
+ wire \u_riscv_top.core_dmem_wdata[6] ;
+ wire \u_riscv_top.core_dmem_wdata[7] ;
+ wire \u_riscv_top.core_dmem_wdata[8] ;
+ wire \u_riscv_top.core_dmem_wdata[9] ;
+ wire \u_riscv_top.core_dmem_width[0] ;
+ wire \u_riscv_top.core_dmem_width[1] ;
+ wire \u_riscv_top.core_icache_addr[0] ;
+ wire \u_riscv_top.core_icache_addr[10] ;
+ wire \u_riscv_top.core_icache_addr[11] ;
+ wire \u_riscv_top.core_icache_addr[12] ;
+ wire \u_riscv_top.core_icache_addr[13] ;
+ wire \u_riscv_top.core_icache_addr[14] ;
+ wire \u_riscv_top.core_icache_addr[15] ;
+ wire \u_riscv_top.core_icache_addr[16] ;
+ wire \u_riscv_top.core_icache_addr[17] ;
+ wire \u_riscv_top.core_icache_addr[18] ;
+ wire \u_riscv_top.core_icache_addr[19] ;
+ wire \u_riscv_top.core_icache_addr[1] ;
+ wire \u_riscv_top.core_icache_addr[20] ;
+ wire \u_riscv_top.core_icache_addr[21] ;
+ wire \u_riscv_top.core_icache_addr[22] ;
+ wire \u_riscv_top.core_icache_addr[23] ;
+ wire \u_riscv_top.core_icache_addr[24] ;
+ wire \u_riscv_top.core_icache_addr[25] ;
+ wire \u_riscv_top.core_icache_addr[26] ;
+ wire \u_riscv_top.core_icache_addr[27] ;
+ wire \u_riscv_top.core_icache_addr[28] ;
+ wire \u_riscv_top.core_icache_addr[29] ;
+ wire \u_riscv_top.core_icache_addr[2] ;
+ wire \u_riscv_top.core_icache_addr[30] ;
+ wire \u_riscv_top.core_icache_addr[31] ;
+ wire \u_riscv_top.core_icache_addr[3] ;
+ wire \u_riscv_top.core_icache_addr[4] ;
+ wire \u_riscv_top.core_icache_addr[5] ;
+ wire \u_riscv_top.core_icache_addr[6] ;
+ wire \u_riscv_top.core_icache_addr[7] ;
+ wire \u_riscv_top.core_icache_addr[8] ;
+ wire \u_riscv_top.core_icache_addr[9] ;
+ wire \u_riscv_top.core_icache_bl[0] ;
+ wire \u_riscv_top.core_icache_bl[1] ;
+ wire \u_riscv_top.core_icache_bl[2] ;
+ wire \u_riscv_top.core_icache_cmd ;
+ wire \u_riscv_top.core_icache_rdata[0] ;
+ wire \u_riscv_top.core_icache_rdata[10] ;
+ wire \u_riscv_top.core_icache_rdata[11] ;
+ wire \u_riscv_top.core_icache_rdata[12] ;
+ wire \u_riscv_top.core_icache_rdata[13] ;
+ wire \u_riscv_top.core_icache_rdata[14] ;
+ wire \u_riscv_top.core_icache_rdata[15] ;
+ wire \u_riscv_top.core_icache_rdata[16] ;
+ wire \u_riscv_top.core_icache_rdata[17] ;
+ wire \u_riscv_top.core_icache_rdata[18] ;
+ wire \u_riscv_top.core_icache_rdata[19] ;
+ wire \u_riscv_top.core_icache_rdata[1] ;
+ wire \u_riscv_top.core_icache_rdata[20] ;
+ wire \u_riscv_top.core_icache_rdata[21] ;
+ wire \u_riscv_top.core_icache_rdata[22] ;
+ wire \u_riscv_top.core_icache_rdata[23] ;
+ wire \u_riscv_top.core_icache_rdata[24] ;
+ wire \u_riscv_top.core_icache_rdata[25] ;
+ wire \u_riscv_top.core_icache_rdata[26] ;
+ wire \u_riscv_top.core_icache_rdata[27] ;
+ wire \u_riscv_top.core_icache_rdata[28] ;
+ wire \u_riscv_top.core_icache_rdata[29] ;
+ wire \u_riscv_top.core_icache_rdata[2] ;
+ wire \u_riscv_top.core_icache_rdata[30] ;
+ wire \u_riscv_top.core_icache_rdata[31] ;
+ wire \u_riscv_top.core_icache_rdata[3] ;
+ wire \u_riscv_top.core_icache_rdata[4] ;
+ wire \u_riscv_top.core_icache_rdata[5] ;
+ wire \u_riscv_top.core_icache_rdata[6] ;
+ wire \u_riscv_top.core_icache_rdata[7] ;
+ wire \u_riscv_top.core_icache_rdata[8] ;
+ wire \u_riscv_top.core_icache_rdata[9] ;
+ wire \u_riscv_top.core_icache_req ;
+ wire \u_riscv_top.core_icache_req_ack ;
+ wire \u_riscv_top.core_icache_resp[0] ;
+ wire \u_riscv_top.core_icache_resp[1] ;
+ wire \u_riscv_top.core_icache_width[0] ;
+ wire \u_riscv_top.core_icache_width[1] ;
+ wire \u_riscv_top.cpu_intf_rst_n ;
+ wire \u_riscv_top.dcache_mem_addr0[0] ;
+ wire \u_riscv_top.dcache_mem_addr0[1] ;
+ wire \u_riscv_top.dcache_mem_addr0[2] ;
+ wire \u_riscv_top.dcache_mem_addr0[3] ;
+ wire \u_riscv_top.dcache_mem_addr0[4] ;
+ wire \u_riscv_top.dcache_mem_addr0[5] ;
+ wire \u_riscv_top.dcache_mem_addr0[6] ;
+ wire \u_riscv_top.dcache_mem_addr0[7] ;
+ wire \u_riscv_top.dcache_mem_addr0[8] ;
+ wire \u_riscv_top.dcache_mem_addr1[0] ;
+ wire \u_riscv_top.dcache_mem_addr1[1] ;
+ wire \u_riscv_top.dcache_mem_addr1[2] ;
+ wire \u_riscv_top.dcache_mem_addr1[3] ;
+ wire \u_riscv_top.dcache_mem_addr1[4] ;
+ wire \u_riscv_top.dcache_mem_addr1[5] ;
+ wire \u_riscv_top.dcache_mem_addr1[6] ;
+ wire \u_riscv_top.dcache_mem_addr1[7] ;
+ wire \u_riscv_top.dcache_mem_addr1[8] ;
+ wire \u_riscv_top.dcache_mem_clk0 ;
+ wire \u_riscv_top.dcache_mem_clk1 ;
+ wire \u_riscv_top.dcache_mem_csb0 ;
+ wire \u_riscv_top.dcache_mem_csb1 ;
+ wire \u_riscv_top.dcache_mem_din0[0] ;
+ wire \u_riscv_top.dcache_mem_din0[10] ;
+ wire \u_riscv_top.dcache_mem_din0[11] ;
+ wire \u_riscv_top.dcache_mem_din0[12] ;
+ wire \u_riscv_top.dcache_mem_din0[13] ;
+ wire \u_riscv_top.dcache_mem_din0[14] ;
+ wire \u_riscv_top.dcache_mem_din0[15] ;
+ wire \u_riscv_top.dcache_mem_din0[16] ;
+ wire \u_riscv_top.dcache_mem_din0[17] ;
+ wire \u_riscv_top.dcache_mem_din0[18] ;
+ wire \u_riscv_top.dcache_mem_din0[19] ;
+ wire \u_riscv_top.dcache_mem_din0[1] ;
+ wire \u_riscv_top.dcache_mem_din0[20] ;
+ wire \u_riscv_top.dcache_mem_din0[21] ;
+ wire \u_riscv_top.dcache_mem_din0[22] ;
+ wire \u_riscv_top.dcache_mem_din0[23] ;
+ wire \u_riscv_top.dcache_mem_din0[24] ;
+ wire \u_riscv_top.dcache_mem_din0[25] ;
+ wire \u_riscv_top.dcache_mem_din0[26] ;
+ wire \u_riscv_top.dcache_mem_din0[27] ;
+ wire \u_riscv_top.dcache_mem_din0[28] ;
+ wire \u_riscv_top.dcache_mem_din0[29] ;
+ wire \u_riscv_top.dcache_mem_din0[2] ;
+ wire \u_riscv_top.dcache_mem_din0[30] ;
+ wire \u_riscv_top.dcache_mem_din0[31] ;
+ wire \u_riscv_top.dcache_mem_din0[3] ;
+ wire \u_riscv_top.dcache_mem_din0[4] ;
+ wire \u_riscv_top.dcache_mem_din0[5] ;
+ wire \u_riscv_top.dcache_mem_din0[6] ;
+ wire \u_riscv_top.dcache_mem_din0[7] ;
+ wire \u_riscv_top.dcache_mem_din0[8] ;
+ wire \u_riscv_top.dcache_mem_din0[9] ;
+ wire \u_riscv_top.dcache_mem_dout0[0] ;
+ wire \u_riscv_top.dcache_mem_dout0[10] ;
+ wire \u_riscv_top.dcache_mem_dout0[11] ;
+ wire \u_riscv_top.dcache_mem_dout0[12] ;
+ wire \u_riscv_top.dcache_mem_dout0[13] ;
+ wire \u_riscv_top.dcache_mem_dout0[14] ;
+ wire \u_riscv_top.dcache_mem_dout0[15] ;
+ wire \u_riscv_top.dcache_mem_dout0[16] ;
+ wire \u_riscv_top.dcache_mem_dout0[17] ;
+ wire \u_riscv_top.dcache_mem_dout0[18] ;
+ wire \u_riscv_top.dcache_mem_dout0[19] ;
+ wire \u_riscv_top.dcache_mem_dout0[1] ;
+ wire \u_riscv_top.dcache_mem_dout0[20] ;
+ wire \u_riscv_top.dcache_mem_dout0[21] ;
+ wire \u_riscv_top.dcache_mem_dout0[22] ;
+ wire \u_riscv_top.dcache_mem_dout0[23] ;
+ wire \u_riscv_top.dcache_mem_dout0[24] ;
+ wire \u_riscv_top.dcache_mem_dout0[25] ;
+ wire \u_riscv_top.dcache_mem_dout0[26] ;
+ wire \u_riscv_top.dcache_mem_dout0[27] ;
+ wire \u_riscv_top.dcache_mem_dout0[28] ;
+ wire \u_riscv_top.dcache_mem_dout0[29] ;
+ wire \u_riscv_top.dcache_mem_dout0[2] ;
+ wire \u_riscv_top.dcache_mem_dout0[30] ;
+ wire \u_riscv_top.dcache_mem_dout0[31] ;
+ wire \u_riscv_top.dcache_mem_dout0[3] ;
+ wire \u_riscv_top.dcache_mem_dout0[4] ;
+ wire \u_riscv_top.dcache_mem_dout0[5] ;
+ wire \u_riscv_top.dcache_mem_dout0[6] ;
+ wire \u_riscv_top.dcache_mem_dout0[7] ;
+ wire \u_riscv_top.dcache_mem_dout0[8] ;
+ wire \u_riscv_top.dcache_mem_dout0[9] ;
+ wire \u_riscv_top.dcache_mem_dout1[0] ;
+ wire \u_riscv_top.dcache_mem_dout1[10] ;
+ wire \u_riscv_top.dcache_mem_dout1[11] ;
+ wire \u_riscv_top.dcache_mem_dout1[12] ;
+ wire \u_riscv_top.dcache_mem_dout1[13] ;
+ wire \u_riscv_top.dcache_mem_dout1[14] ;
+ wire \u_riscv_top.dcache_mem_dout1[15] ;
+ wire \u_riscv_top.dcache_mem_dout1[16] ;
+ wire \u_riscv_top.dcache_mem_dout1[17] ;
+ wire \u_riscv_top.dcache_mem_dout1[18] ;
+ wire \u_riscv_top.dcache_mem_dout1[19] ;
+ wire \u_riscv_top.dcache_mem_dout1[1] ;
+ wire \u_riscv_top.dcache_mem_dout1[20] ;
+ wire \u_riscv_top.dcache_mem_dout1[21] ;
+ wire \u_riscv_top.dcache_mem_dout1[22] ;
+ wire \u_riscv_top.dcache_mem_dout1[23] ;
+ wire \u_riscv_top.dcache_mem_dout1[24] ;
+ wire \u_riscv_top.dcache_mem_dout1[25] ;
+ wire \u_riscv_top.dcache_mem_dout1[26] ;
+ wire \u_riscv_top.dcache_mem_dout1[27] ;
+ wire \u_riscv_top.dcache_mem_dout1[28] ;
+ wire \u_riscv_top.dcache_mem_dout1[29] ;
+ wire \u_riscv_top.dcache_mem_dout1[2] ;
+ wire \u_riscv_top.dcache_mem_dout1[30] ;
+ wire \u_riscv_top.dcache_mem_dout1[31] ;
+ wire \u_riscv_top.dcache_mem_dout1[3] ;
+ wire \u_riscv_top.dcache_mem_dout1[4] ;
+ wire \u_riscv_top.dcache_mem_dout1[5] ;
+ wire \u_riscv_top.dcache_mem_dout1[6] ;
+ wire \u_riscv_top.dcache_mem_dout1[7] ;
+ wire \u_riscv_top.dcache_mem_dout1[8] ;
+ wire \u_riscv_top.dcache_mem_dout1[9] ;
+ wire \u_riscv_top.dcache_mem_web0 ;
+ wire \u_riscv_top.dcache_mem_wmask0[0] ;
+ wire \u_riscv_top.dcache_mem_wmask0[1] ;
+ wire \u_riscv_top.dcache_mem_wmask0[2] ;
+ wire \u_riscv_top.dcache_mem_wmask0[3] ;
+ wire \u_riscv_top.fpu_dmem_addr[0] ;
+ wire \u_riscv_top.fpu_dmem_addr[1] ;
+ wire \u_riscv_top.fpu_dmem_addr[2] ;
+ wire \u_riscv_top.fpu_dmem_addr[3] ;
+ wire \u_riscv_top.fpu_dmem_addr[4] ;
+ wire \u_riscv_top.fpu_dmem_cmd ;
+ wire \u_riscv_top.fpu_dmem_rdata[0] ;
+ wire \u_riscv_top.fpu_dmem_rdata[10] ;
+ wire \u_riscv_top.fpu_dmem_rdata[11] ;
+ wire \u_riscv_top.fpu_dmem_rdata[12] ;
+ wire \u_riscv_top.fpu_dmem_rdata[13] ;
+ wire \u_riscv_top.fpu_dmem_rdata[14] ;
+ wire \u_riscv_top.fpu_dmem_rdata[15] ;
+ wire \u_riscv_top.fpu_dmem_rdata[16] ;
+ wire \u_riscv_top.fpu_dmem_rdata[17] ;
+ wire \u_riscv_top.fpu_dmem_rdata[18] ;
+ wire \u_riscv_top.fpu_dmem_rdata[19] ;
+ wire \u_riscv_top.fpu_dmem_rdata[1] ;
+ wire \u_riscv_top.fpu_dmem_rdata[20] ;
+ wire \u_riscv_top.fpu_dmem_rdata[21] ;
+ wire \u_riscv_top.fpu_dmem_rdata[22] ;
+ wire \u_riscv_top.fpu_dmem_rdata[23] ;
+ wire \u_riscv_top.fpu_dmem_rdata[24] ;
+ wire \u_riscv_top.fpu_dmem_rdata[25] ;
+ wire \u_riscv_top.fpu_dmem_rdata[26] ;
+ wire \u_riscv_top.fpu_dmem_rdata[27] ;
+ wire \u_riscv_top.fpu_dmem_rdata[28] ;
+ wire \u_riscv_top.fpu_dmem_rdata[29] ;
+ wire \u_riscv_top.fpu_dmem_rdata[2] ;
+ wire \u_riscv_top.fpu_dmem_rdata[30] ;
+ wire \u_riscv_top.fpu_dmem_rdata[31] ;
+ wire \u_riscv_top.fpu_dmem_rdata[3] ;
+ wire \u_riscv_top.fpu_dmem_rdata[4] ;
+ wire \u_riscv_top.fpu_dmem_rdata[5] ;
+ wire \u_riscv_top.fpu_dmem_rdata[6] ;
+ wire \u_riscv_top.fpu_dmem_rdata[7] ;
+ wire \u_riscv_top.fpu_dmem_rdata[8] ;
+ wire \u_riscv_top.fpu_dmem_rdata[9] ;
+ wire \u_riscv_top.fpu_dmem_req ;
+ wire \u_riscv_top.fpu_dmem_req_ack ;
+ wire \u_riscv_top.fpu_dmem_resp[0] ;
+ wire \u_riscv_top.fpu_dmem_resp[1] ;
+ wire \u_riscv_top.fpu_dmem_wdata[0] ;
+ wire \u_riscv_top.fpu_dmem_wdata[10] ;
+ wire \u_riscv_top.fpu_dmem_wdata[11] ;
+ wire \u_riscv_top.fpu_dmem_wdata[12] ;
+ wire \u_riscv_top.fpu_dmem_wdata[13] ;
+ wire \u_riscv_top.fpu_dmem_wdata[14] ;
+ wire \u_riscv_top.fpu_dmem_wdata[15] ;
+ wire \u_riscv_top.fpu_dmem_wdata[16] ;
+ wire \u_riscv_top.fpu_dmem_wdata[17] ;
+ wire \u_riscv_top.fpu_dmem_wdata[18] ;
+ wire \u_riscv_top.fpu_dmem_wdata[19] ;
+ wire \u_riscv_top.fpu_dmem_wdata[1] ;
+ wire \u_riscv_top.fpu_dmem_wdata[20] ;
+ wire \u_riscv_top.fpu_dmem_wdata[21] ;
+ wire \u_riscv_top.fpu_dmem_wdata[22] ;
+ wire \u_riscv_top.fpu_dmem_wdata[23] ;
+ wire \u_riscv_top.fpu_dmem_wdata[24] ;
+ wire \u_riscv_top.fpu_dmem_wdata[25] ;
+ wire \u_riscv_top.fpu_dmem_wdata[26] ;
+ wire \u_riscv_top.fpu_dmem_wdata[27] ;
+ wire \u_riscv_top.fpu_dmem_wdata[28] ;
+ wire \u_riscv_top.fpu_dmem_wdata[29] ;
+ wire \u_riscv_top.fpu_dmem_wdata[2] ;
+ wire \u_riscv_top.fpu_dmem_wdata[30] ;
+ wire \u_riscv_top.fpu_dmem_wdata[31] ;
+ wire \u_riscv_top.fpu_dmem_wdata[3] ;
+ wire \u_riscv_top.fpu_dmem_wdata[4] ;
+ wire \u_riscv_top.fpu_dmem_wdata[5] ;
+ wire \u_riscv_top.fpu_dmem_wdata[6] ;
+ wire \u_riscv_top.fpu_dmem_wdata[7] ;
+ wire \u_riscv_top.fpu_dmem_wdata[8] ;
+ wire \u_riscv_top.fpu_dmem_wdata[9] ;
+ wire \u_riscv_top.fpu_dmem_width[0] ;
+ wire \u_riscv_top.fpu_dmem_width[1] ;
+ wire \u_riscv_top.icache_mem_addr0[0] ;
+ wire \u_riscv_top.icache_mem_addr0[1] ;
+ wire \u_riscv_top.icache_mem_addr0[2] ;
+ wire \u_riscv_top.icache_mem_addr0[3] ;
+ wire \u_riscv_top.icache_mem_addr0[4] ;
+ wire \u_riscv_top.icache_mem_addr0[5] ;
+ wire \u_riscv_top.icache_mem_addr0[6] ;
+ wire \u_riscv_top.icache_mem_addr0[7] ;
+ wire \u_riscv_top.icache_mem_addr0[8] ;
+ wire \u_riscv_top.icache_mem_addr1[0] ;
+ wire \u_riscv_top.icache_mem_addr1[1] ;
+ wire \u_riscv_top.icache_mem_addr1[2] ;
+ wire \u_riscv_top.icache_mem_addr1[3] ;
+ wire \u_riscv_top.icache_mem_addr1[4] ;
+ wire \u_riscv_top.icache_mem_addr1[5] ;
+ wire \u_riscv_top.icache_mem_addr1[6] ;
+ wire \u_riscv_top.icache_mem_addr1[7] ;
+ wire \u_riscv_top.icache_mem_addr1[8] ;
+ wire \u_riscv_top.icache_mem_clk0 ;
+ wire \u_riscv_top.icache_mem_clk1 ;
+ wire \u_riscv_top.icache_mem_csb0 ;
+ wire \u_riscv_top.icache_mem_csb1 ;
+ wire \u_riscv_top.icache_mem_din0[0] ;
+ wire \u_riscv_top.icache_mem_din0[10] ;
+ wire \u_riscv_top.icache_mem_din0[11] ;
+ wire \u_riscv_top.icache_mem_din0[12] ;
+ wire \u_riscv_top.icache_mem_din0[13] ;
+ wire \u_riscv_top.icache_mem_din0[14] ;
+ wire \u_riscv_top.icache_mem_din0[15] ;
+ wire \u_riscv_top.icache_mem_din0[16] ;
+ wire \u_riscv_top.icache_mem_din0[17] ;
+ wire \u_riscv_top.icache_mem_din0[18] ;
+ wire \u_riscv_top.icache_mem_din0[19] ;
+ wire \u_riscv_top.icache_mem_din0[1] ;
+ wire \u_riscv_top.icache_mem_din0[20] ;
+ wire \u_riscv_top.icache_mem_din0[21] ;
+ wire \u_riscv_top.icache_mem_din0[22] ;
+ wire \u_riscv_top.icache_mem_din0[23] ;
+ wire \u_riscv_top.icache_mem_din0[24] ;
+ wire \u_riscv_top.icache_mem_din0[25] ;
+ wire \u_riscv_top.icache_mem_din0[26] ;
+ wire \u_riscv_top.icache_mem_din0[27] ;
+ wire \u_riscv_top.icache_mem_din0[28] ;
+ wire \u_riscv_top.icache_mem_din0[29] ;
+ wire \u_riscv_top.icache_mem_din0[2] ;
+ wire \u_riscv_top.icache_mem_din0[30] ;
+ wire \u_riscv_top.icache_mem_din0[31] ;
+ wire \u_riscv_top.icache_mem_din0[3] ;
+ wire \u_riscv_top.icache_mem_din0[4] ;
+ wire \u_riscv_top.icache_mem_din0[5] ;
+ wire \u_riscv_top.icache_mem_din0[6] ;
+ wire \u_riscv_top.icache_mem_din0[7] ;
+ wire \u_riscv_top.icache_mem_din0[8] ;
+ wire \u_riscv_top.icache_mem_din0[9] ;
+ wire \u_riscv_top.icache_mem_dout1[0] ;
+ wire \u_riscv_top.icache_mem_dout1[10] ;
+ wire \u_riscv_top.icache_mem_dout1[11] ;
+ wire \u_riscv_top.icache_mem_dout1[12] ;
+ wire \u_riscv_top.icache_mem_dout1[13] ;
+ wire \u_riscv_top.icache_mem_dout1[14] ;
+ wire \u_riscv_top.icache_mem_dout1[15] ;
+ wire \u_riscv_top.icache_mem_dout1[16] ;
+ wire \u_riscv_top.icache_mem_dout1[17] ;
+ wire \u_riscv_top.icache_mem_dout1[18] ;
+ wire \u_riscv_top.icache_mem_dout1[19] ;
+ wire \u_riscv_top.icache_mem_dout1[1] ;
+ wire \u_riscv_top.icache_mem_dout1[20] ;
+ wire \u_riscv_top.icache_mem_dout1[21] ;
+ wire \u_riscv_top.icache_mem_dout1[22] ;
+ wire \u_riscv_top.icache_mem_dout1[23] ;
+ wire \u_riscv_top.icache_mem_dout1[24] ;
+ wire \u_riscv_top.icache_mem_dout1[25] ;
+ wire \u_riscv_top.icache_mem_dout1[26] ;
+ wire \u_riscv_top.icache_mem_dout1[27] ;
+ wire \u_riscv_top.icache_mem_dout1[28] ;
+ wire \u_riscv_top.icache_mem_dout1[29] ;
+ wire \u_riscv_top.icache_mem_dout1[2] ;
+ wire \u_riscv_top.icache_mem_dout1[30] ;
+ wire \u_riscv_top.icache_mem_dout1[31] ;
+ wire \u_riscv_top.icache_mem_dout1[3] ;
+ wire \u_riscv_top.icache_mem_dout1[4] ;
+ wire \u_riscv_top.icache_mem_dout1[5] ;
+ wire \u_riscv_top.icache_mem_dout1[6] ;
+ wire \u_riscv_top.icache_mem_dout1[7] ;
+ wire \u_riscv_top.icache_mem_dout1[8] ;
+ wire \u_riscv_top.icache_mem_dout1[9] ;
+ wire \u_riscv_top.icache_mem_web0 ;
+ wire \u_riscv_top.icache_mem_wmask0[0] ;
+ wire \u_riscv_top.icache_mem_wmask0[1] ;
+ wire \u_riscv_top.icache_mem_wmask0[2] ;
+ wire \u_riscv_top.icache_mem_wmask0[3] ;
+ wire \u_riscv_top.irq_lines[0] ;
+ wire \u_riscv_top.irq_lines[10] ;
+ wire \u_riscv_top.irq_lines[11] ;
+ wire \u_riscv_top.irq_lines[12] ;
+ wire \u_riscv_top.irq_lines[13] ;
+ wire \u_riscv_top.irq_lines[14] ;
+ wire \u_riscv_top.irq_lines[15] ;
+ wire \u_riscv_top.irq_lines[16] ;
+ wire \u_riscv_top.irq_lines[17] ;
+ wire \u_riscv_top.irq_lines[18] ;
+ wire \u_riscv_top.irq_lines[19] ;
+ wire \u_riscv_top.irq_lines[1] ;
+ wire \u_riscv_top.irq_lines[20] ;
+ wire \u_riscv_top.irq_lines[21] ;
+ wire \u_riscv_top.irq_lines[22] ;
+ wire \u_riscv_top.irq_lines[23] ;
+ wire \u_riscv_top.irq_lines[24] ;
+ wire \u_riscv_top.irq_lines[25] ;
+ wire \u_riscv_top.irq_lines[26] ;
+ wire \u_riscv_top.irq_lines[27] ;
+ wire \u_riscv_top.irq_lines[28] ;
+ wire \u_riscv_top.irq_lines[29] ;
+ wire \u_riscv_top.irq_lines[2] ;
+ wire \u_riscv_top.irq_lines[30] ;
+ wire \u_riscv_top.irq_lines[31] ;
+ wire \u_riscv_top.irq_lines[3] ;
+ wire \u_riscv_top.irq_lines[4] ;
+ wire \u_riscv_top.irq_lines[5] ;
+ wire \u_riscv_top.irq_lines[6] ;
+ wire \u_riscv_top.irq_lines[7] ;
+ wire \u_riscv_top.irq_lines[8] ;
+ wire \u_riscv_top.irq_lines[9] ;
+ wire \u_riscv_top.pwrup_rst_n ;
+ wire \u_riscv_top.rtc_clk ;
+ wire \u_riscv_top.soft_irq ;
+ wire \u_riscv_top.sram0_addr0[0] ;
+ wire \u_riscv_top.sram0_addr0[1] ;
+ wire \u_riscv_top.sram0_addr0[2] ;
+ wire \u_riscv_top.sram0_addr0[3] ;
+ wire \u_riscv_top.sram0_addr0[4] ;
+ wire \u_riscv_top.sram0_addr0[5] ;
+ wire \u_riscv_top.sram0_addr0[6] ;
+ wire \u_riscv_top.sram0_addr0[7] ;
+ wire \u_riscv_top.sram0_addr0[8] ;
+ wire \u_riscv_top.sram0_addr1[0] ;
+ wire \u_riscv_top.sram0_addr1[1] ;
+ wire \u_riscv_top.sram0_addr1[2] ;
+ wire \u_riscv_top.sram0_addr1[3] ;
+ wire \u_riscv_top.sram0_addr1[4] ;
+ wire \u_riscv_top.sram0_addr1[5] ;
+ wire \u_riscv_top.sram0_addr1[6] ;
+ wire \u_riscv_top.sram0_addr1[7] ;
+ wire \u_riscv_top.sram0_addr1[8] ;
+ wire \u_riscv_top.sram0_clk0 ;
+ wire \u_riscv_top.sram0_clk1 ;
+ wire \u_riscv_top.sram0_csb0 ;
+ wire \u_riscv_top.sram0_csb1 ;
+ wire \u_riscv_top.sram0_din0[0] ;
+ wire \u_riscv_top.sram0_din0[10] ;
+ wire \u_riscv_top.sram0_din0[11] ;
+ wire \u_riscv_top.sram0_din0[12] ;
+ wire \u_riscv_top.sram0_din0[13] ;
+ wire \u_riscv_top.sram0_din0[14] ;
+ wire \u_riscv_top.sram0_din0[15] ;
+ wire \u_riscv_top.sram0_din0[16] ;
+ wire \u_riscv_top.sram0_din0[17] ;
+ wire \u_riscv_top.sram0_din0[18] ;
+ wire \u_riscv_top.sram0_din0[19] ;
+ wire \u_riscv_top.sram0_din0[1] ;
+ wire \u_riscv_top.sram0_din0[20] ;
+ wire \u_riscv_top.sram0_din0[21] ;
+ wire \u_riscv_top.sram0_din0[22] ;
+ wire \u_riscv_top.sram0_din0[23] ;
+ wire \u_riscv_top.sram0_din0[24] ;
+ wire \u_riscv_top.sram0_din0[25] ;
+ wire \u_riscv_top.sram0_din0[26] ;
+ wire \u_riscv_top.sram0_din0[27] ;
+ wire \u_riscv_top.sram0_din0[28] ;
+ wire \u_riscv_top.sram0_din0[29] ;
+ wire \u_riscv_top.sram0_din0[2] ;
+ wire \u_riscv_top.sram0_din0[30] ;
+ wire \u_riscv_top.sram0_din0[31] ;
+ wire \u_riscv_top.sram0_din0[3] ;
+ wire \u_riscv_top.sram0_din0[4] ;
+ wire \u_riscv_top.sram0_din0[5] ;
+ wire \u_riscv_top.sram0_din0[6] ;
+ wire \u_riscv_top.sram0_din0[7] ;
+ wire \u_riscv_top.sram0_din0[8] ;
+ wire \u_riscv_top.sram0_din0[9] ;
+ wire \u_riscv_top.sram0_dout0[0] ;
+ wire \u_riscv_top.sram0_dout0[10] ;
+ wire \u_riscv_top.sram0_dout0[11] ;
+ wire \u_riscv_top.sram0_dout0[12] ;
+ wire \u_riscv_top.sram0_dout0[13] ;
+ wire \u_riscv_top.sram0_dout0[14] ;
+ wire \u_riscv_top.sram0_dout0[15] ;
+ wire \u_riscv_top.sram0_dout0[16] ;
+ wire \u_riscv_top.sram0_dout0[17] ;
+ wire \u_riscv_top.sram0_dout0[18] ;
+ wire \u_riscv_top.sram0_dout0[19] ;
+ wire \u_riscv_top.sram0_dout0[1] ;
+ wire \u_riscv_top.sram0_dout0[20] ;
+ wire \u_riscv_top.sram0_dout0[21] ;
+ wire \u_riscv_top.sram0_dout0[22] ;
+ wire \u_riscv_top.sram0_dout0[23] ;
+ wire \u_riscv_top.sram0_dout0[24] ;
+ wire \u_riscv_top.sram0_dout0[25] ;
+ wire \u_riscv_top.sram0_dout0[26] ;
+ wire \u_riscv_top.sram0_dout0[27] ;
+ wire \u_riscv_top.sram0_dout0[28] ;
+ wire \u_riscv_top.sram0_dout0[29] ;
+ wire \u_riscv_top.sram0_dout0[2] ;
+ wire \u_riscv_top.sram0_dout0[30] ;
+ wire \u_riscv_top.sram0_dout0[31] ;
+ wire \u_riscv_top.sram0_dout0[3] ;
+ wire \u_riscv_top.sram0_dout0[4] ;
+ wire \u_riscv_top.sram0_dout0[5] ;
+ wire \u_riscv_top.sram0_dout0[6] ;
+ wire \u_riscv_top.sram0_dout0[7] ;
+ wire \u_riscv_top.sram0_dout0[8] ;
+ wire \u_riscv_top.sram0_dout0[9] ;
+ wire \u_riscv_top.sram0_dout1[0] ;
+ wire \u_riscv_top.sram0_dout1[10] ;
+ wire \u_riscv_top.sram0_dout1[11] ;
+ wire \u_riscv_top.sram0_dout1[12] ;
+ wire \u_riscv_top.sram0_dout1[13] ;
+ wire \u_riscv_top.sram0_dout1[14] ;
+ wire \u_riscv_top.sram0_dout1[15] ;
+ wire \u_riscv_top.sram0_dout1[16] ;
+ wire \u_riscv_top.sram0_dout1[17] ;
+ wire \u_riscv_top.sram0_dout1[18] ;
+ wire \u_riscv_top.sram0_dout1[19] ;
+ wire \u_riscv_top.sram0_dout1[1] ;
+ wire \u_riscv_top.sram0_dout1[20] ;
+ wire \u_riscv_top.sram0_dout1[21] ;
+ wire \u_riscv_top.sram0_dout1[22] ;
+ wire \u_riscv_top.sram0_dout1[23] ;
+ wire \u_riscv_top.sram0_dout1[24] ;
+ wire \u_riscv_top.sram0_dout1[25] ;
+ wire \u_riscv_top.sram0_dout1[26] ;
+ wire \u_riscv_top.sram0_dout1[27] ;
+ wire \u_riscv_top.sram0_dout1[28] ;
+ wire \u_riscv_top.sram0_dout1[29] ;
+ wire \u_riscv_top.sram0_dout1[2] ;
+ wire \u_riscv_top.sram0_dout1[30] ;
+ wire \u_riscv_top.sram0_dout1[31] ;
+ wire \u_riscv_top.sram0_dout1[3] ;
+ wire \u_riscv_top.sram0_dout1[4] ;
+ wire \u_riscv_top.sram0_dout1[5] ;
+ wire \u_riscv_top.sram0_dout1[6] ;
+ wire \u_riscv_top.sram0_dout1[7] ;
+ wire \u_riscv_top.sram0_dout1[8] ;
+ wire \u_riscv_top.sram0_dout1[9] ;
+ wire \u_riscv_top.sram0_web0 ;
+ wire \u_riscv_top.sram0_wmask0[0] ;
+ wire \u_riscv_top.sram0_wmask0[1] ;
+ wire \u_riscv_top.sram0_wmask0[2] ;
+ wire \u_riscv_top.sram0_wmask0[3] ;
+ wire \u_riscv_top.wb_clk ;
+ wire \u_riscv_top.wb_dcache_ack_i ;
+ wire \u_riscv_top.wb_dcache_adr_o[0] ;
+ wire \u_riscv_top.wb_dcache_adr_o[10] ;
+ wire \u_riscv_top.wb_dcache_adr_o[11] ;
+ wire \u_riscv_top.wb_dcache_adr_o[12] ;
+ wire \u_riscv_top.wb_dcache_adr_o[13] ;
+ wire \u_riscv_top.wb_dcache_adr_o[14] ;
+ wire \u_riscv_top.wb_dcache_adr_o[15] ;
+ wire \u_riscv_top.wb_dcache_adr_o[16] ;
+ wire \u_riscv_top.wb_dcache_adr_o[17] ;
+ wire \u_riscv_top.wb_dcache_adr_o[18] ;
+ wire \u_riscv_top.wb_dcache_adr_o[19] ;
+ wire \u_riscv_top.wb_dcache_adr_o[1] ;
+ wire \u_riscv_top.wb_dcache_adr_o[20] ;
+ wire \u_riscv_top.wb_dcache_adr_o[21] ;
+ wire \u_riscv_top.wb_dcache_adr_o[22] ;
+ wire \u_riscv_top.wb_dcache_adr_o[23] ;
+ wire \u_riscv_top.wb_dcache_adr_o[24] ;
+ wire \u_riscv_top.wb_dcache_adr_o[25] ;
+ wire \u_riscv_top.wb_dcache_adr_o[26] ;
+ wire \u_riscv_top.wb_dcache_adr_o[27] ;
+ wire \u_riscv_top.wb_dcache_adr_o[28] ;
+ wire \u_riscv_top.wb_dcache_adr_o[29] ;
+ wire \u_riscv_top.wb_dcache_adr_o[2] ;
+ wire \u_riscv_top.wb_dcache_adr_o[30] ;
+ wire \u_riscv_top.wb_dcache_adr_o[31] ;
+ wire \u_riscv_top.wb_dcache_adr_o[3] ;
+ wire \u_riscv_top.wb_dcache_adr_o[4] ;
+ wire \u_riscv_top.wb_dcache_adr_o[5] ;
+ wire \u_riscv_top.wb_dcache_adr_o[6] ;
+ wire \u_riscv_top.wb_dcache_adr_o[7] ;
+ wire \u_riscv_top.wb_dcache_adr_o[8] ;
+ wire \u_riscv_top.wb_dcache_adr_o[9] ;
+ wire \u_riscv_top.wb_dcache_bl_o[0] ;
+ wire \u_riscv_top.wb_dcache_bl_o[1] ;
+ wire \u_riscv_top.wb_dcache_bl_o[2] ;
+ wire \u_riscv_top.wb_dcache_bl_o[3] ;
+ wire \u_riscv_top.wb_dcache_bl_o[4] ;
+ wire \u_riscv_top.wb_dcache_bl_o[5] ;
+ wire \u_riscv_top.wb_dcache_bl_o[6] ;
+ wire \u_riscv_top.wb_dcache_bl_o[7] ;
+ wire \u_riscv_top.wb_dcache_bl_o[8] ;
+ wire \u_riscv_top.wb_dcache_bl_o[9] ;
+ wire \u_riscv_top.wb_dcache_bry_o ;
+ wire \u_riscv_top.wb_dcache_cyc_o ;
+ wire \u_riscv_top.wb_dcache_dat_i[0] ;
+ wire \u_riscv_top.wb_dcache_dat_i[10] ;
+ wire \u_riscv_top.wb_dcache_dat_i[11] ;
+ wire \u_riscv_top.wb_dcache_dat_i[12] ;
+ wire \u_riscv_top.wb_dcache_dat_i[13] ;
+ wire \u_riscv_top.wb_dcache_dat_i[14] ;
+ wire \u_riscv_top.wb_dcache_dat_i[15] ;
+ wire \u_riscv_top.wb_dcache_dat_i[16] ;
+ wire \u_riscv_top.wb_dcache_dat_i[17] ;
+ wire \u_riscv_top.wb_dcache_dat_i[18] ;
+ wire \u_riscv_top.wb_dcache_dat_i[19] ;
+ wire \u_riscv_top.wb_dcache_dat_i[1] ;
+ wire \u_riscv_top.wb_dcache_dat_i[20] ;
+ wire \u_riscv_top.wb_dcache_dat_i[21] ;
+ wire \u_riscv_top.wb_dcache_dat_i[22] ;
+ wire \u_riscv_top.wb_dcache_dat_i[23] ;
+ wire \u_riscv_top.wb_dcache_dat_i[24] ;
+ wire \u_riscv_top.wb_dcache_dat_i[25] ;
+ wire \u_riscv_top.wb_dcache_dat_i[26] ;
+ wire \u_riscv_top.wb_dcache_dat_i[27] ;
+ wire \u_riscv_top.wb_dcache_dat_i[28] ;
+ wire \u_riscv_top.wb_dcache_dat_i[29] ;
+ wire \u_riscv_top.wb_dcache_dat_i[2] ;
+ wire \u_riscv_top.wb_dcache_dat_i[30] ;
+ wire \u_riscv_top.wb_dcache_dat_i[31] ;
+ wire \u_riscv_top.wb_dcache_dat_i[3] ;
+ wire \u_riscv_top.wb_dcache_dat_i[4] ;
+ wire \u_riscv_top.wb_dcache_dat_i[5] ;
+ wire \u_riscv_top.wb_dcache_dat_i[6] ;
+ wire \u_riscv_top.wb_dcache_dat_i[7] ;
+ wire \u_riscv_top.wb_dcache_dat_i[8] ;
+ wire \u_riscv_top.wb_dcache_dat_i[9] ;
+ wire \u_riscv_top.wb_dcache_dat_o[0] ;
+ wire \u_riscv_top.wb_dcache_dat_o[10] ;
+ wire \u_riscv_top.wb_dcache_dat_o[11] ;
+ wire \u_riscv_top.wb_dcache_dat_o[12] ;
+ wire \u_riscv_top.wb_dcache_dat_o[13] ;
+ wire \u_riscv_top.wb_dcache_dat_o[14] ;
+ wire \u_riscv_top.wb_dcache_dat_o[15] ;
+ wire \u_riscv_top.wb_dcache_dat_o[16] ;
+ wire \u_riscv_top.wb_dcache_dat_o[17] ;
+ wire \u_riscv_top.wb_dcache_dat_o[18] ;
+ wire \u_riscv_top.wb_dcache_dat_o[19] ;
+ wire \u_riscv_top.wb_dcache_dat_o[1] ;
+ wire \u_riscv_top.wb_dcache_dat_o[20] ;
+ wire \u_riscv_top.wb_dcache_dat_o[21] ;
+ wire \u_riscv_top.wb_dcache_dat_o[22] ;
+ wire \u_riscv_top.wb_dcache_dat_o[23] ;
+ wire \u_riscv_top.wb_dcache_dat_o[24] ;
+ wire \u_riscv_top.wb_dcache_dat_o[25] ;
+ wire \u_riscv_top.wb_dcache_dat_o[26] ;
+ wire \u_riscv_top.wb_dcache_dat_o[27] ;
+ wire \u_riscv_top.wb_dcache_dat_o[28] ;
+ wire \u_riscv_top.wb_dcache_dat_o[29] ;
+ wire \u_riscv_top.wb_dcache_dat_o[2] ;
+ wire \u_riscv_top.wb_dcache_dat_o[30] ;
+ wire \u_riscv_top.wb_dcache_dat_o[31] ;
+ wire \u_riscv_top.wb_dcache_dat_o[3] ;
+ wire \u_riscv_top.wb_dcache_dat_o[4] ;
+ wire \u_riscv_top.wb_dcache_dat_o[5] ;
+ wire \u_riscv_top.wb_dcache_dat_o[6] ;
+ wire \u_riscv_top.wb_dcache_dat_o[7] ;
+ wire \u_riscv_top.wb_dcache_dat_o[8] ;
+ wire \u_riscv_top.wb_dcache_dat_o[9] ;
+ wire \u_riscv_top.wb_dcache_err_i ;
+ wire \u_riscv_top.wb_dcache_lack_i ;
+ wire \u_riscv_top.wb_dcache_sel_o[0] ;
+ wire \u_riscv_top.wb_dcache_sel_o[1] ;
+ wire \u_riscv_top.wb_dcache_sel_o[2] ;
+ wire \u_riscv_top.wb_dcache_sel_o[3] ;
+ wire \u_riscv_top.wb_dcache_stb_o ;
+ wire \u_riscv_top.wb_dcache_we_o ;
+ wire \u_riscv_top.wb_icache_ack_i ;
+ wire \u_riscv_top.wb_icache_adr_o[0] ;
+ wire \u_riscv_top.wb_icache_adr_o[10] ;
+ wire \u_riscv_top.wb_icache_adr_o[11] ;
+ wire \u_riscv_top.wb_icache_adr_o[12] ;
+ wire \u_riscv_top.wb_icache_adr_o[13] ;
+ wire \u_riscv_top.wb_icache_adr_o[14] ;
+ wire \u_riscv_top.wb_icache_adr_o[15] ;
+ wire \u_riscv_top.wb_icache_adr_o[16] ;
+ wire \u_riscv_top.wb_icache_adr_o[17] ;
+ wire \u_riscv_top.wb_icache_adr_o[18] ;
+ wire \u_riscv_top.wb_icache_adr_o[19] ;
+ wire \u_riscv_top.wb_icache_adr_o[1] ;
+ wire \u_riscv_top.wb_icache_adr_o[20] ;
+ wire \u_riscv_top.wb_icache_adr_o[21] ;
+ wire \u_riscv_top.wb_icache_adr_o[22] ;
+ wire \u_riscv_top.wb_icache_adr_o[23] ;
+ wire \u_riscv_top.wb_icache_adr_o[24] ;
+ wire \u_riscv_top.wb_icache_adr_o[25] ;
+ wire \u_riscv_top.wb_icache_adr_o[26] ;
+ wire \u_riscv_top.wb_icache_adr_o[27] ;
+ wire \u_riscv_top.wb_icache_adr_o[28] ;
+ wire \u_riscv_top.wb_icache_adr_o[29] ;
+ wire \u_riscv_top.wb_icache_adr_o[2] ;
+ wire \u_riscv_top.wb_icache_adr_o[30] ;
+ wire \u_riscv_top.wb_icache_adr_o[31] ;
+ wire \u_riscv_top.wb_icache_adr_o[3] ;
+ wire \u_riscv_top.wb_icache_adr_o[4] ;
+ wire \u_riscv_top.wb_icache_adr_o[5] ;
+ wire \u_riscv_top.wb_icache_adr_o[6] ;
+ wire \u_riscv_top.wb_icache_adr_o[7] ;
+ wire \u_riscv_top.wb_icache_adr_o[8] ;
+ wire \u_riscv_top.wb_icache_adr_o[9] ;
+ wire \u_riscv_top.wb_icache_bl_o[0] ;
+ wire \u_riscv_top.wb_icache_bl_o[1] ;
+ wire \u_riscv_top.wb_icache_bl_o[2] ;
+ wire \u_riscv_top.wb_icache_bl_o[3] ;
+ wire \u_riscv_top.wb_icache_bl_o[4] ;
+ wire \u_riscv_top.wb_icache_bl_o[5] ;
+ wire \u_riscv_top.wb_icache_bl_o[6] ;
+ wire \u_riscv_top.wb_icache_bl_o[7] ;
+ wire \u_riscv_top.wb_icache_bl_o[8] ;
+ wire \u_riscv_top.wb_icache_bl_o[9] ;
+ wire \u_riscv_top.wb_icache_bry_o ;
+ wire \u_riscv_top.wb_icache_cyc_o ;
+ wire \u_riscv_top.wb_icache_dat_i[0] ;
+ wire \u_riscv_top.wb_icache_dat_i[10] ;
+ wire \u_riscv_top.wb_icache_dat_i[11] ;
+ wire \u_riscv_top.wb_icache_dat_i[12] ;
+ wire \u_riscv_top.wb_icache_dat_i[13] ;
+ wire \u_riscv_top.wb_icache_dat_i[14] ;
+ wire \u_riscv_top.wb_icache_dat_i[15] ;
+ wire \u_riscv_top.wb_icache_dat_i[16] ;
+ wire \u_riscv_top.wb_icache_dat_i[17] ;
+ wire \u_riscv_top.wb_icache_dat_i[18] ;
+ wire \u_riscv_top.wb_icache_dat_i[19] ;
+ wire \u_riscv_top.wb_icache_dat_i[1] ;
+ wire \u_riscv_top.wb_icache_dat_i[20] ;
+ wire \u_riscv_top.wb_icache_dat_i[21] ;
+ wire \u_riscv_top.wb_icache_dat_i[22] ;
+ wire \u_riscv_top.wb_icache_dat_i[23] ;
+ wire \u_riscv_top.wb_icache_dat_i[24] ;
+ wire \u_riscv_top.wb_icache_dat_i[25] ;
+ wire \u_riscv_top.wb_icache_dat_i[26] ;
+ wire \u_riscv_top.wb_icache_dat_i[27] ;
+ wire \u_riscv_top.wb_icache_dat_i[28] ;
+ wire \u_riscv_top.wb_icache_dat_i[29] ;
+ wire \u_riscv_top.wb_icache_dat_i[2] ;
+ wire \u_riscv_top.wb_icache_dat_i[30] ;
+ wire \u_riscv_top.wb_icache_dat_i[31] ;
+ wire \u_riscv_top.wb_icache_dat_i[3] ;
+ wire \u_riscv_top.wb_icache_dat_i[4] ;
+ wire \u_riscv_top.wb_icache_dat_i[5] ;
+ wire \u_riscv_top.wb_icache_dat_i[6] ;
+ wire \u_riscv_top.wb_icache_dat_i[7] ;
+ wire \u_riscv_top.wb_icache_dat_i[8] ;
+ wire \u_riscv_top.wb_icache_dat_i[9] ;
+ wire \u_riscv_top.wb_icache_err_i ;
+ wire \u_riscv_top.wb_icache_lack_i ;
+ wire \u_riscv_top.wb_icache_sel_o[0] ;
+ wire \u_riscv_top.wb_icache_sel_o[1] ;
+ wire \u_riscv_top.wb_icache_sel_o[2] ;
+ wire \u_riscv_top.wb_icache_sel_o[3] ;
+ wire \u_riscv_top.wb_icache_stb_o ;
+ wire \u_riscv_top.wb_icache_we_o ;
+ wire \u_riscv_top.wbd_clk_int ;
+ wire \u_riscv_top.wbd_dmem_ack_i ;
+ wire \u_riscv_top.wbd_dmem_adr_o[0] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[10] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[11] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[12] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[13] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[14] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[15] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[16] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[17] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[18] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[19] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[1] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[20] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[21] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[22] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[23] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[24] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[25] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[26] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[27] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[28] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[29] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[2] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[30] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[31] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[3] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[4] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[5] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[6] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[7] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[8] ;
+ wire \u_riscv_top.wbd_dmem_adr_o[9] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[0] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[1] ;
+ wire \u_riscv_top.wbd_dmem_bl_o[2] ;
+ wire \u_riscv_top.wbd_dmem_bry_o ;
+ wire \u_riscv_top.wbd_dmem_dat_i[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_i[9] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[0] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[10] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[11] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[12] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[13] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[14] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[15] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[16] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[17] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[18] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[19] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[1] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[20] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[21] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[22] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[23] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[24] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[25] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[26] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[27] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[28] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[29] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[2] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[30] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[31] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[3] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[4] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[5] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[6] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[7] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[8] ;
+ wire \u_riscv_top.wbd_dmem_dat_o[9] ;
+ wire \u_riscv_top.wbd_dmem_err_i ;
+ wire \u_riscv_top.wbd_dmem_lack_i ;
+ wire \u_riscv_top.wbd_dmem_sel_o[0] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[1] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[2] ;
+ wire \u_riscv_top.wbd_dmem_sel_o[3] ;
+ wire \u_riscv_top.wbd_dmem_stb_o ;
+ wire \u_riscv_top.wbd_dmem_we_o ;
+ wire \uart_rst_n[0] ;
+ wire \uart_rst_n[1] ;
+ wire \uart_rxd[0] ;
+ wire \uart_rxd[1] ;
+ wire \uart_txd[0] ;
+ wire \uart_txd[1] ;
+ wire uartm_rxd;
+ wire uartm_txd;
+ wire usb_clk;
+ wire usb_dn_i;
+ wire usb_dn_o;
+ wire usb_dp_i;
+ wire usb_dp_o;
+ wire usb_intr_o;
+ wire usb_oen;
+ wire usb_rst_n;
+ wire wbd_clk_int;
+ wire wbd_clk_pinmux_rp;
+ wire wbd_clk_pinmux_skew;
+ wire wbd_clk_qspi_rp;
+ wire wbd_clk_spi;
+ wire wbd_clk_uart_rp;
+ wire wbd_clk_uart_skew;
+ wire wbd_clk_wh;
+ wire wbd_clk_wi_skew;
+ wire wbd_glbl_ack_i;
+ wire \wbd_glbl_adr_o[0] ;
+ wire \wbd_glbl_adr_o[1] ;
+ wire \wbd_glbl_adr_o[2] ;
+ wire \wbd_glbl_adr_o[3] ;
+ wire \wbd_glbl_adr_o[4] ;
+ wire \wbd_glbl_adr_o[5] ;
+ wire \wbd_glbl_adr_o[6] ;
+ wire \wbd_glbl_adr_o[7] ;
+ wire \wbd_glbl_adr_o[8] ;
+ wire \wbd_glbl_adr_o[9] ;
+ wire wbd_glbl_cyc_o;
+ wire \wbd_glbl_dat_i[0] ;
+ wire \wbd_glbl_dat_i[10] ;
+ wire \wbd_glbl_dat_i[11] ;
+ wire \wbd_glbl_dat_i[12] ;
+ wire \wbd_glbl_dat_i[13] ;
+ wire \wbd_glbl_dat_i[14] ;
+ wire \wbd_glbl_dat_i[15] ;
+ wire \wbd_glbl_dat_i[16] ;
+ wire \wbd_glbl_dat_i[17] ;
+ wire \wbd_glbl_dat_i[18] ;
+ wire \wbd_glbl_dat_i[19] ;
+ wire \wbd_glbl_dat_i[1] ;
+ wire \wbd_glbl_dat_i[20] ;
+ wire \wbd_glbl_dat_i[21] ;
+ wire \wbd_glbl_dat_i[22] ;
+ wire \wbd_glbl_dat_i[23] ;
+ wire \wbd_glbl_dat_i[24] ;
+ wire \wbd_glbl_dat_i[25] ;
+ wire \wbd_glbl_dat_i[26] ;
+ wire \wbd_glbl_dat_i[27] ;
+ wire \wbd_glbl_dat_i[28] ;
+ wire \wbd_glbl_dat_i[29] ;
+ wire \wbd_glbl_dat_i[2] ;
+ wire \wbd_glbl_dat_i[30] ;
+ wire \wbd_glbl_dat_i[31] ;
+ wire \wbd_glbl_dat_i[3] ;
+ wire \wbd_glbl_dat_i[4] ;
+ wire \wbd_glbl_dat_i[5] ;
+ wire \wbd_glbl_dat_i[6] ;
+ wire \wbd_glbl_dat_i[7] ;
+ wire \wbd_glbl_dat_i[8] ;
+ wire \wbd_glbl_dat_i[9] ;
+ wire \wbd_glbl_dat_o[0] ;
+ wire \wbd_glbl_dat_o[10] ;
+ wire \wbd_glbl_dat_o[11] ;
+ wire \wbd_glbl_dat_o[12] ;
+ wire \wbd_glbl_dat_o[13] ;
+ wire \wbd_glbl_dat_o[14] ;
+ wire \wbd_glbl_dat_o[15] ;
+ wire \wbd_glbl_dat_o[16] ;
+ wire \wbd_glbl_dat_o[17] ;
+ wire \wbd_glbl_dat_o[18] ;
+ wire \wbd_glbl_dat_o[19] ;
+ wire \wbd_glbl_dat_o[1] ;
+ wire \wbd_glbl_dat_o[20] ;
+ wire \wbd_glbl_dat_o[21] ;
+ wire \wbd_glbl_dat_o[22] ;
+ wire \wbd_glbl_dat_o[23] ;
+ wire \wbd_glbl_dat_o[24] ;
+ wire \wbd_glbl_dat_o[25] ;
+ wire \wbd_glbl_dat_o[26] ;
+ wire \wbd_glbl_dat_o[27] ;
+ wire \wbd_glbl_dat_o[28] ;
+ wire \wbd_glbl_dat_o[29] ;
+ wire \wbd_glbl_dat_o[2] ;
+ wire \wbd_glbl_dat_o[30] ;
+ wire \wbd_glbl_dat_o[31] ;
+ wire \wbd_glbl_dat_o[3] ;
+ wire \wbd_glbl_dat_o[4] ;
+ wire \wbd_glbl_dat_o[5] ;
+ wire \wbd_glbl_dat_o[6] ;
+ wire \wbd_glbl_dat_o[7] ;
+ wire \wbd_glbl_dat_o[8] ;
+ wire \wbd_glbl_dat_o[9] ;
+ wire \wbd_glbl_sel_o[0] ;
+ wire \wbd_glbl_sel_o[1] ;
+ wire \wbd_glbl_sel_o[2] ;
+ wire \wbd_glbl_sel_o[3] ;
+ wire wbd_glbl_stb_o;
+ wire wbd_glbl_we_o;
+ wire wbd_int_ack_o;
+ wire \wbd_int_adr_i[0] ;
+ wire \wbd_int_adr_i[10] ;
+ wire \wbd_int_adr_i[11] ;
+ wire \wbd_int_adr_i[12] ;
+ wire \wbd_int_adr_i[13] ;
+ wire \wbd_int_adr_i[14] ;
+ wire \wbd_int_adr_i[15] ;
+ wire \wbd_int_adr_i[16] ;
+ wire \wbd_int_adr_i[17] ;
+ wire \wbd_int_adr_i[18] ;
+ wire \wbd_int_adr_i[19] ;
+ wire \wbd_int_adr_i[1] ;
+ wire \wbd_int_adr_i[20] ;
+ wire \wbd_int_adr_i[21] ;
+ wire \wbd_int_adr_i[22] ;
+ wire \wbd_int_adr_i[23] ;
+ wire \wbd_int_adr_i[24] ;
+ wire \wbd_int_adr_i[25] ;
+ wire \wbd_int_adr_i[26] ;
+ wire \wbd_int_adr_i[27] ;
+ wire \wbd_int_adr_i[28] ;
+ wire \wbd_int_adr_i[29] ;
+ wire \wbd_int_adr_i[2] ;
+ wire \wbd_int_adr_i[30] ;
+ wire \wbd_int_adr_i[31] ;
+ wire \wbd_int_adr_i[3] ;
+ wire \wbd_int_adr_i[4] ;
+ wire \wbd_int_adr_i[5] ;
+ wire \wbd_int_adr_i[6] ;
+ wire \wbd_int_adr_i[7] ;
+ wire \wbd_int_adr_i[8] ;
+ wire \wbd_int_adr_i[9] ;
+ wire wbd_int_cyc_i;
+ wire \wbd_int_dat_i[0] ;
+ wire \wbd_int_dat_i[10] ;
+ wire \wbd_int_dat_i[11] ;
+ wire \wbd_int_dat_i[12] ;
+ wire \wbd_int_dat_i[13] ;
+ wire \wbd_int_dat_i[14] ;
+ wire \wbd_int_dat_i[15] ;
+ wire \wbd_int_dat_i[16] ;
+ wire \wbd_int_dat_i[17] ;
+ wire \wbd_int_dat_i[18] ;
+ wire \wbd_int_dat_i[19] ;
+ wire \wbd_int_dat_i[1] ;
+ wire \wbd_int_dat_i[20] ;
+ wire \wbd_int_dat_i[21] ;
+ wire \wbd_int_dat_i[22] ;
+ wire \wbd_int_dat_i[23] ;
+ wire \wbd_int_dat_i[24] ;
+ wire \wbd_int_dat_i[25] ;
+ wire \wbd_int_dat_i[26] ;
+ wire \wbd_int_dat_i[27] ;
+ wire \wbd_int_dat_i[28] ;
+ wire \wbd_int_dat_i[29] ;
+ wire \wbd_int_dat_i[2] ;
+ wire \wbd_int_dat_i[30] ;
+ wire \wbd_int_dat_i[31] ;
+ wire \wbd_int_dat_i[3] ;
+ wire \wbd_int_dat_i[4] ;
+ wire \wbd_int_dat_i[5] ;
+ wire \wbd_int_dat_i[6] ;
+ wire \wbd_int_dat_i[7] ;
+ wire \wbd_int_dat_i[8] ;
+ wire \wbd_int_dat_i[9] ;
+ wire \wbd_int_dat_o[0] ;
+ wire \wbd_int_dat_o[10] ;
+ wire \wbd_int_dat_o[11] ;
+ wire \wbd_int_dat_o[12] ;
+ wire \wbd_int_dat_o[13] ;
+ wire \wbd_int_dat_o[14] ;
+ wire \wbd_int_dat_o[15] ;
+ wire \wbd_int_dat_o[16] ;
+ wire \wbd_int_dat_o[17] ;
+ wire \wbd_int_dat_o[18] ;
+ wire \wbd_int_dat_o[19] ;
+ wire \wbd_int_dat_o[1] ;
+ wire \wbd_int_dat_o[20] ;
+ wire \wbd_int_dat_o[21] ;
+ wire \wbd_int_dat_o[22] ;
+ wire \wbd_int_dat_o[23] ;
+ wire \wbd_int_dat_o[24] ;
+ wire \wbd_int_dat_o[25] ;
+ wire \wbd_int_dat_o[26] ;
+ wire \wbd_int_dat_o[27] ;
+ wire \wbd_int_dat_o[28] ;
+ wire \wbd_int_dat_o[29] ;
+ wire \wbd_int_dat_o[2] ;
+ wire \wbd_int_dat_o[30] ;
+ wire \wbd_int_dat_o[31] ;
+ wire \wbd_int_dat_o[3] ;
+ wire \wbd_int_dat_o[4] ;
+ wire \wbd_int_dat_o[5] ;
+ wire \wbd_int_dat_o[6] ;
+ wire \wbd_int_dat_o[7] ;
+ wire \wbd_int_dat_o[8] ;
+ wire \wbd_int_dat_o[9] ;
+ wire wbd_int_err_o;
+ wire \wbd_int_sel_i[0] ;
+ wire \wbd_int_sel_i[1] ;
+ wire \wbd_int_sel_i[2] ;
+ wire \wbd_int_sel_i[3] ;
+ wire wbd_int_stb_i;
+ wire wbd_int_we_i;
+ wire wbd_pll_rst_n;
+ wire wbd_spim_ack_i;
+ wire \wbd_spim_adr_o[0] ;
+ wire \wbd_spim_adr_o[10] ;
+ wire \wbd_spim_adr_o[11] ;
+ wire \wbd_spim_adr_o[12] ;
+ wire \wbd_spim_adr_o[13] ;
+ wire \wbd_spim_adr_o[14] ;
+ wire \wbd_spim_adr_o[15] ;
+ wire \wbd_spim_adr_o[16] ;
+ wire \wbd_spim_adr_o[17] ;
+ wire \wbd_spim_adr_o[18] ;
+ wire \wbd_spim_adr_o[19] ;
+ wire \wbd_spim_adr_o[1] ;
+ wire \wbd_spim_adr_o[20] ;
+ wire \wbd_spim_adr_o[21] ;
+ wire \wbd_spim_adr_o[22] ;
+ wire \wbd_spim_adr_o[23] ;
+ wire \wbd_spim_adr_o[24] ;
+ wire \wbd_spim_adr_o[25] ;
+ wire \wbd_spim_adr_o[26] ;
+ wire \wbd_spim_adr_o[27] ;
+ wire \wbd_spim_adr_o[28] ;
+ wire \wbd_spim_adr_o[29] ;
+ wire \wbd_spim_adr_o[2] ;
+ wire \wbd_spim_adr_o[30] ;
+ wire \wbd_spim_adr_o[31] ;
+ wire \wbd_spim_adr_o[3] ;
+ wire \wbd_spim_adr_o[4] ;
+ wire \wbd_spim_adr_o[5] ;
+ wire \wbd_spim_adr_o[6] ;
+ wire \wbd_spim_adr_o[7] ;
+ wire \wbd_spim_adr_o[8] ;
+ wire \wbd_spim_adr_o[9] ;
+ wire \wbd_spim_bl_o[0] ;
+ wire \wbd_spim_bl_o[1] ;
+ wire \wbd_spim_bl_o[2] ;
+ wire \wbd_spim_bl_o[3] ;
+ wire \wbd_spim_bl_o[4] ;
+ wire \wbd_spim_bl_o[5] ;
+ wire \wbd_spim_bl_o[6] ;
+ wire \wbd_spim_bl_o[7] ;
+ wire \wbd_spim_bl_o[8] ;
+ wire \wbd_spim_bl_o[9] ;
+ wire wbd_spim_bry_o;
+ wire wbd_spim_cyc_o;
+ wire \wbd_spim_dat_i[0] ;
+ wire \wbd_spim_dat_i[10] ;
+ wire \wbd_spim_dat_i[11] ;
+ wire \wbd_spim_dat_i[12] ;
+ wire \wbd_spim_dat_i[13] ;
+ wire \wbd_spim_dat_i[14] ;
+ wire \wbd_spim_dat_i[15] ;
+ wire \wbd_spim_dat_i[16] ;
+ wire \wbd_spim_dat_i[17] ;
+ wire \wbd_spim_dat_i[18] ;
+ wire \wbd_spim_dat_i[19] ;
+ wire \wbd_spim_dat_i[1] ;
+ wire \wbd_spim_dat_i[20] ;
+ wire \wbd_spim_dat_i[21] ;
+ wire \wbd_spim_dat_i[22] ;
+ wire \wbd_spim_dat_i[23] ;
+ wire \wbd_spim_dat_i[24] ;
+ wire \wbd_spim_dat_i[25] ;
+ wire \wbd_spim_dat_i[26] ;
+ wire \wbd_spim_dat_i[27] ;
+ wire \wbd_spim_dat_i[28] ;
+ wire \wbd_spim_dat_i[29] ;
+ wire \wbd_spim_dat_i[2] ;
+ wire \wbd_spim_dat_i[30] ;
+ wire \wbd_spim_dat_i[31] ;
+ wire \wbd_spim_dat_i[3] ;
+ wire \wbd_spim_dat_i[4] ;
+ wire \wbd_spim_dat_i[5] ;
+ wire \wbd_spim_dat_i[6] ;
+ wire \wbd_spim_dat_i[7] ;
+ wire \wbd_spim_dat_i[8] ;
+ wire \wbd_spim_dat_i[9] ;
+ wire \wbd_spim_dat_o[0] ;
+ wire \wbd_spim_dat_o[10] ;
+ wire \wbd_spim_dat_o[11] ;
+ wire \wbd_spim_dat_o[12] ;
+ wire \wbd_spim_dat_o[13] ;
+ wire \wbd_spim_dat_o[14] ;
+ wire \wbd_spim_dat_o[15] ;
+ wire \wbd_spim_dat_o[16] ;
+ wire \wbd_spim_dat_o[17] ;
+ wire \wbd_spim_dat_o[18] ;
+ wire \wbd_spim_dat_o[19] ;
+ wire \wbd_spim_dat_o[1] ;
+ wire \wbd_spim_dat_o[20] ;
+ wire \wbd_spim_dat_o[21] ;
+ wire \wbd_spim_dat_o[22] ;
+ wire \wbd_spim_dat_o[23] ;
+ wire \wbd_spim_dat_o[24] ;
+ wire \wbd_spim_dat_o[25] ;
+ wire \wbd_spim_dat_o[26] ;
+ wire \wbd_spim_dat_o[27] ;
+ wire \wbd_spim_dat_o[28] ;
+ wire \wbd_spim_dat_o[29] ;
+ wire \wbd_spim_dat_o[2] ;
+ wire \wbd_spim_dat_o[30] ;
+ wire \wbd_spim_dat_o[31] ;
+ wire \wbd_spim_dat_o[3] ;
+ wire \wbd_spim_dat_o[4] ;
+ wire \wbd_spim_dat_o[5] ;
+ wire \wbd_spim_dat_o[6] ;
+ wire \wbd_spim_dat_o[7] ;
+ wire \wbd_spim_dat_o[8] ;
+ wire \wbd_spim_dat_o[9] ;
+ wire wbd_spim_err_i;
+ wire wbd_spim_lack_i;
+ wire \wbd_spim_sel_o[0] ;
+ wire \wbd_spim_sel_o[1] ;
+ wire \wbd_spim_sel_o[2] ;
+ wire \wbd_spim_sel_o[3] ;
+ wire wbd_spim_stb_o;
+ wire wbd_spim_we_o;
+ wire wbd_uart_ack_i;
+ wire \wbd_uart_adr_o[0] ;
+ wire \wbd_uart_adr_o[1] ;
+ wire \wbd_uart_adr_o[2] ;
+ wire \wbd_uart_adr_o[3] ;
+ wire \wbd_uart_adr_o[4] ;
+ wire \wbd_uart_adr_o[5] ;
+ wire \wbd_uart_adr_o[6] ;
+ wire \wbd_uart_adr_o[7] ;
+ wire \wbd_uart_adr_o[8] ;
+ wire wbd_uart_cyc_o;
+ wire \wbd_uart_dat_i[0] ;
+ wire \wbd_uart_dat_i[10] ;
+ wire \wbd_uart_dat_i[11] ;
+ wire \wbd_uart_dat_i[12] ;
+ wire \wbd_uart_dat_i[13] ;
+ wire \wbd_uart_dat_i[14] ;
+ wire \wbd_uart_dat_i[15] ;
+ wire \wbd_uart_dat_i[16] ;
+ wire \wbd_uart_dat_i[17] ;
+ wire \wbd_uart_dat_i[18] ;
+ wire \wbd_uart_dat_i[19] ;
+ wire \wbd_uart_dat_i[1] ;
+ wire \wbd_uart_dat_i[20] ;
+ wire \wbd_uart_dat_i[21] ;
+ wire \wbd_uart_dat_i[22] ;
+ wire \wbd_uart_dat_i[23] ;
+ wire \wbd_uart_dat_i[24] ;
+ wire \wbd_uart_dat_i[25] ;
+ wire \wbd_uart_dat_i[26] ;
+ wire \wbd_uart_dat_i[27] ;
+ wire \wbd_uart_dat_i[28] ;
+ wire \wbd_uart_dat_i[29] ;
+ wire \wbd_uart_dat_i[2] ;
+ wire \wbd_uart_dat_i[30] ;
+ wire \wbd_uart_dat_i[31] ;
+ wire \wbd_uart_dat_i[3] ;
+ wire \wbd_uart_dat_i[4] ;
+ wire \wbd_uart_dat_i[5] ;
+ wire \wbd_uart_dat_i[6] ;
+ wire \wbd_uart_dat_i[7] ;
+ wire \wbd_uart_dat_i[8] ;
+ wire \wbd_uart_dat_i[9] ;
+ wire \wbd_uart_dat_o[0] ;
+ wire \wbd_uart_dat_o[10] ;
+ wire \wbd_uart_dat_o[11] ;
+ wire \wbd_uart_dat_o[12] ;
+ wire \wbd_uart_dat_o[13] ;
+ wire \wbd_uart_dat_o[14] ;
+ wire \wbd_uart_dat_o[15] ;
+ wire \wbd_uart_dat_o[16] ;
+ wire \wbd_uart_dat_o[17] ;
+ wire \wbd_uart_dat_o[18] ;
+ wire \wbd_uart_dat_o[19] ;
+ wire \wbd_uart_dat_o[1] ;
+ wire \wbd_uart_dat_o[20] ;
+ wire \wbd_uart_dat_o[21] ;
+ wire \wbd_uart_dat_o[22] ;
+ wire \wbd_uart_dat_o[23] ;
+ wire \wbd_uart_dat_o[24] ;
+ wire \wbd_uart_dat_o[25] ;
+ wire \wbd_uart_dat_o[26] ;
+ wire \wbd_uart_dat_o[27] ;
+ wire \wbd_uart_dat_o[28] ;
+ wire \wbd_uart_dat_o[29] ;
+ wire \wbd_uart_dat_o[2] ;
+ wire \wbd_uart_dat_o[30] ;
+ wire \wbd_uart_dat_o[31] ;
+ wire \wbd_uart_dat_o[3] ;
+ wire \wbd_uart_dat_o[4] ;
+ wire \wbd_uart_dat_o[5] ;
+ wire \wbd_uart_dat_o[6] ;
+ wire \wbd_uart_dat_o[7] ;
+ wire \wbd_uart_dat_o[8] ;
+ wire \wbd_uart_dat_o[9] ;
+ wire \wbd_uart_sel_o[0] ;
+ wire \wbd_uart_sel_o[1] ;
+ wire \wbd_uart_sel_o[2] ;
+ wire \wbd_uart_sel_o[3] ;
+ wire wbd_uart_stb_o;
+ wire wbd_uart_we_o;
+ wire xtal_clk;
+
+ dac_top u_4x8bit_dac (.Vout0(analog_io[15]),
+    .Vout1(analog_io[16]),
+    .Vout2(analog_io[17]),
+    .Vout3(analog_io[18]),
+    .Vref(analog_io[23]),
+    .vccd1(vdda1),
+    .vssd1(vssa1),
+    .DIn0({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .DIn1({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .DIn2({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .DIn3({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }));
+ aes_top u_aes (.dmem_cmd(\u_riscv_top.aes_dmem_cmd ),
+    .dmem_req(\u_riscv_top.aes_dmem_req ),
+    .dmem_req_ack(\u_riscv_top.aes_dmem_req_ack ),
+    .mclk(cpu_clk_aes),
+    .rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(\cpu_clk_rp[6] ),
+    .wbd_clk_out(cpu_clk_aes),
+    .cfg_cska({\cfg_ccska_aes_rp[3] ,
+    \cfg_ccska_aes_rp[2] ,
+    \cfg_ccska_aes_rp[1] ,
+    \cfg_ccska_aes_rp[0] }),
+    .dmem_addr({\u_riscv_top.aes_dmem_addr[6] ,
+    \u_riscv_top.aes_dmem_addr[5] ,
+    \u_riscv_top.aes_dmem_addr[4] ,
+    \u_riscv_top.aes_dmem_addr[3] ,
+    \u_riscv_top.aes_dmem_addr[2] ,
+    \u_riscv_top.aes_dmem_addr[1] ,
+    \u_riscv_top.aes_dmem_addr[0] }),
+    .dmem_rdata({\u_riscv_top.aes_dmem_rdata[31] ,
+    \u_riscv_top.aes_dmem_rdata[30] ,
+    \u_riscv_top.aes_dmem_rdata[29] ,
+    \u_riscv_top.aes_dmem_rdata[28] ,
+    \u_riscv_top.aes_dmem_rdata[27] ,
+    \u_riscv_top.aes_dmem_rdata[26] ,
+    \u_riscv_top.aes_dmem_rdata[25] ,
+    \u_riscv_top.aes_dmem_rdata[24] ,
+    \u_riscv_top.aes_dmem_rdata[23] ,
+    \u_riscv_top.aes_dmem_rdata[22] ,
+    \u_riscv_top.aes_dmem_rdata[21] ,
+    \u_riscv_top.aes_dmem_rdata[20] ,
+    \u_riscv_top.aes_dmem_rdata[19] ,
+    \u_riscv_top.aes_dmem_rdata[18] ,
+    \u_riscv_top.aes_dmem_rdata[17] ,
+    \u_riscv_top.aes_dmem_rdata[16] ,
+    \u_riscv_top.aes_dmem_rdata[15] ,
+    \u_riscv_top.aes_dmem_rdata[14] ,
+    \u_riscv_top.aes_dmem_rdata[13] ,
+    \u_riscv_top.aes_dmem_rdata[12] ,
+    \u_riscv_top.aes_dmem_rdata[11] ,
+    \u_riscv_top.aes_dmem_rdata[10] ,
+    \u_riscv_top.aes_dmem_rdata[9] ,
+    \u_riscv_top.aes_dmem_rdata[8] ,
+    \u_riscv_top.aes_dmem_rdata[7] ,
+    \u_riscv_top.aes_dmem_rdata[6] ,
+    \u_riscv_top.aes_dmem_rdata[5] ,
+    \u_riscv_top.aes_dmem_rdata[4] ,
+    \u_riscv_top.aes_dmem_rdata[3] ,
+    \u_riscv_top.aes_dmem_rdata[2] ,
+    \u_riscv_top.aes_dmem_rdata[1] ,
+    \u_riscv_top.aes_dmem_rdata[0] }),
+    .dmem_resp({\u_riscv_top.aes_dmem_resp[1] ,
+    \u_riscv_top.aes_dmem_resp[0] }),
+    .dmem_wdata({\u_riscv_top.aes_dmem_wdata[31] ,
+    \u_riscv_top.aes_dmem_wdata[30] ,
+    \u_riscv_top.aes_dmem_wdata[29] ,
+    \u_riscv_top.aes_dmem_wdata[28] ,
+    \u_riscv_top.aes_dmem_wdata[27] ,
+    \u_riscv_top.aes_dmem_wdata[26] ,
+    \u_riscv_top.aes_dmem_wdata[25] ,
+    \u_riscv_top.aes_dmem_wdata[24] ,
+    \u_riscv_top.aes_dmem_wdata[23] ,
+    \u_riscv_top.aes_dmem_wdata[22] ,
+    \u_riscv_top.aes_dmem_wdata[21] ,
+    \u_riscv_top.aes_dmem_wdata[20] ,
+    \u_riscv_top.aes_dmem_wdata[19] ,
+    \u_riscv_top.aes_dmem_wdata[18] ,
+    \u_riscv_top.aes_dmem_wdata[17] ,
+    \u_riscv_top.aes_dmem_wdata[16] ,
+    \u_riscv_top.aes_dmem_wdata[15] ,
+    \u_riscv_top.aes_dmem_wdata[14] ,
+    \u_riscv_top.aes_dmem_wdata[13] ,
+    \u_riscv_top.aes_dmem_wdata[12] ,
+    \u_riscv_top.aes_dmem_wdata[11] ,
+    \u_riscv_top.aes_dmem_wdata[10] ,
+    \u_riscv_top.aes_dmem_wdata[9] ,
+    \u_riscv_top.aes_dmem_wdata[8] ,
+    \u_riscv_top.aes_dmem_wdata[7] ,
+    \u_riscv_top.aes_dmem_wdata[6] ,
+    \u_riscv_top.aes_dmem_wdata[5] ,
+    \u_riscv_top.aes_dmem_wdata[4] ,
+    \u_riscv_top.aes_dmem_wdata[3] ,
+    \u_riscv_top.aes_dmem_wdata[2] ,
+    \u_riscv_top.aes_dmem_wdata[1] ,
+    \u_riscv_top.aes_dmem_wdata[0] }),
+    .dmem_width({\u_riscv_top.aes_dmem_width[1] ,
+    \u_riscv_top.aes_dmem_width[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb (.csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .web0(\u_riscv_top.dcache_mem_web0 ),
+    .clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }));
+ fpu_wrapper u_fpu (.dmem_cmd(\u_riscv_top.fpu_dmem_cmd ),
+    .dmem_req(\u_riscv_top.fpu_dmem_req ),
+    .dmem_req_ack(\u_riscv_top.fpu_dmem_req_ack ),
+    .mclk(cpu_clk_fpu),
+    .rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(\cpu_clk_rp[7] ),
+    .wbd_clk_out(cpu_clk_fpu),
+    .cfg_cska({\cfg_ccska_fpu_rp[3] ,
+    \cfg_ccska_fpu_rp[2] ,
+    \cfg_ccska_fpu_rp[1] ,
+    \cfg_ccska_fpu_rp[0] }),
+    .dmem_addr({\u_riscv_top.fpu_dmem_addr[4] ,
+    \u_riscv_top.fpu_dmem_addr[3] ,
+    \u_riscv_top.fpu_dmem_addr[2] ,
+    \u_riscv_top.fpu_dmem_addr[1] ,
+    \u_riscv_top.fpu_dmem_addr[0] }),
+    .dmem_rdata({\u_riscv_top.fpu_dmem_rdata[31] ,
+    \u_riscv_top.fpu_dmem_rdata[30] ,
+    \u_riscv_top.fpu_dmem_rdata[29] ,
+    \u_riscv_top.fpu_dmem_rdata[28] ,
+    \u_riscv_top.fpu_dmem_rdata[27] ,
+    \u_riscv_top.fpu_dmem_rdata[26] ,
+    \u_riscv_top.fpu_dmem_rdata[25] ,
+    \u_riscv_top.fpu_dmem_rdata[24] ,
+    \u_riscv_top.fpu_dmem_rdata[23] ,
+    \u_riscv_top.fpu_dmem_rdata[22] ,
+    \u_riscv_top.fpu_dmem_rdata[21] ,
+    \u_riscv_top.fpu_dmem_rdata[20] ,
+    \u_riscv_top.fpu_dmem_rdata[19] ,
+    \u_riscv_top.fpu_dmem_rdata[18] ,
+    \u_riscv_top.fpu_dmem_rdata[17] ,
+    \u_riscv_top.fpu_dmem_rdata[16] ,
+    \u_riscv_top.fpu_dmem_rdata[15] ,
+    \u_riscv_top.fpu_dmem_rdata[14] ,
+    \u_riscv_top.fpu_dmem_rdata[13] ,
+    \u_riscv_top.fpu_dmem_rdata[12] ,
+    \u_riscv_top.fpu_dmem_rdata[11] ,
+    \u_riscv_top.fpu_dmem_rdata[10] ,
+    \u_riscv_top.fpu_dmem_rdata[9] ,
+    \u_riscv_top.fpu_dmem_rdata[8] ,
+    \u_riscv_top.fpu_dmem_rdata[7] ,
+    \u_riscv_top.fpu_dmem_rdata[6] ,
+    \u_riscv_top.fpu_dmem_rdata[5] ,
+    \u_riscv_top.fpu_dmem_rdata[4] ,
+    \u_riscv_top.fpu_dmem_rdata[3] ,
+    \u_riscv_top.fpu_dmem_rdata[2] ,
+    \u_riscv_top.fpu_dmem_rdata[1] ,
+    \u_riscv_top.fpu_dmem_rdata[0] }),
+    .dmem_resp({\u_riscv_top.fpu_dmem_resp[1] ,
+    \u_riscv_top.fpu_dmem_resp[0] }),
+    .dmem_wdata({\u_riscv_top.fpu_dmem_wdata[31] ,
+    \u_riscv_top.fpu_dmem_wdata[30] ,
+    \u_riscv_top.fpu_dmem_wdata[29] ,
+    \u_riscv_top.fpu_dmem_wdata[28] ,
+    \u_riscv_top.fpu_dmem_wdata[27] ,
+    \u_riscv_top.fpu_dmem_wdata[26] ,
+    \u_riscv_top.fpu_dmem_wdata[25] ,
+    \u_riscv_top.fpu_dmem_wdata[24] ,
+    \u_riscv_top.fpu_dmem_wdata[23] ,
+    \u_riscv_top.fpu_dmem_wdata[22] ,
+    \u_riscv_top.fpu_dmem_wdata[21] ,
+    \u_riscv_top.fpu_dmem_wdata[20] ,
+    \u_riscv_top.fpu_dmem_wdata[19] ,
+    \u_riscv_top.fpu_dmem_wdata[18] ,
+    \u_riscv_top.fpu_dmem_wdata[17] ,
+    \u_riscv_top.fpu_dmem_wdata[16] ,
+    \u_riscv_top.fpu_dmem_wdata[15] ,
+    \u_riscv_top.fpu_dmem_wdata[14] ,
+    \u_riscv_top.fpu_dmem_wdata[13] ,
+    \u_riscv_top.fpu_dmem_wdata[12] ,
+    \u_riscv_top.fpu_dmem_wdata[11] ,
+    \u_riscv_top.fpu_dmem_wdata[10] ,
+    \u_riscv_top.fpu_dmem_wdata[9] ,
+    \u_riscv_top.fpu_dmem_wdata[8] ,
+    \u_riscv_top.fpu_dmem_wdata[7] ,
+    \u_riscv_top.fpu_dmem_wdata[6] ,
+    \u_riscv_top.fpu_dmem_wdata[5] ,
+    \u_riscv_top.fpu_dmem_wdata[4] ,
+    \u_riscv_top.fpu_dmem_wdata[3] ,
+    \u_riscv_top.fpu_dmem_wdata[2] ,
+    \u_riscv_top.fpu_dmem_wdata[1] ,
+    \u_riscv_top.fpu_dmem_wdata[0] }),
+    .dmem_width({\u_riscv_top.fpu_dmem_width[1] ,
+    \u_riscv_top.fpu_dmem_width[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb (.csb0(\u_riscv_top.icache_mem_csb0 ),
+    .csb1(\u_riscv_top.icache_mem_csb1 ),
+    .web0(\u_riscv_top.icache_mem_web0 ),
+    .clk0(\u_riscv_top.icache_mem_clk0 ),
+    .clk1(\u_riscv_top.icache_mem_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .dout0({_NC1,
+    _NC2,
+    _NC3,
+    _NC4,
+    _NC5,
+    _NC6,
+    _NC7,
+    _NC8,
+    _NC9,
+    _NC10,
+    _NC11,
+    _NC12,
+    _NC13,
+    _NC14,
+    _NC15,
+    _NC16,
+    _NC17,
+    _NC18,
+    _NC19,
+    _NC20,
+    _NC21,
+    _NC22,
+    _NC23,
+    _NC24,
+    _NC25,
+    _NC26,
+    _NC27,
+    _NC28,
+    _NC29,
+    _NC30,
+    _NC31,
+    _NC32}),
+    .dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }));
+ wb_interconnect u_intercon (.clk_i(wbd_clk_wi_skew),
+    .m0_wbd_ack_o(wbd_int_ack_o),
+    .m0_wbd_cyc_i(wbd_int_cyc_i),
+    .m0_wbd_err_o(wbd_int_err_o),
+    .m0_wbd_stb_i(wbd_int_stb_i),
+    .m0_wbd_we_i(wbd_int_we_i),
+    .m1_wbd_ack_o(\u_riscv_top.wbd_dmem_ack_i ),
+    .m1_wbd_bry_i(\u_riscv_top.wbd_dmem_bry_o ),
+    .m1_wbd_cyc_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_err_o(\u_riscv_top.wbd_dmem_err_i ),
+    .m1_wbd_lack_o(\u_riscv_top.wbd_dmem_lack_i ),
+    .m1_wbd_stb_i(\u_riscv_top.wbd_dmem_stb_o ),
+    .m1_wbd_we_i(\u_riscv_top.wbd_dmem_we_o ),
+    .m2_wbd_ack_o(\u_riscv_top.wb_dcache_ack_i ),
+    .m2_wbd_bry_i(\u_riscv_top.wb_dcache_bry_o ),
+    .m2_wbd_cyc_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_err_o(\u_riscv_top.wb_dcache_err_i ),
+    .m2_wbd_lack_o(\u_riscv_top.wb_dcache_lack_i ),
+    .m2_wbd_stb_i(\u_riscv_top.wb_dcache_stb_o ),
+    .m2_wbd_we_i(\u_riscv_top.wb_dcache_we_o ),
+    .m3_wbd_ack_o(\u_riscv_top.wb_icache_ack_i ),
+    .m3_wbd_bry_i(\u_riscv_top.wb_icache_bry_o ),
+    .m3_wbd_cyc_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_err_o(\u_riscv_top.wb_icache_err_i ),
+    .m3_wbd_lack_o(\u_riscv_top.wb_icache_lack_i ),
+    .m3_wbd_stb_i(\u_riscv_top.wb_icache_stb_o ),
+    .m3_wbd_we_i(\u_riscv_top.wb_icache_we_o ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .s0_wbd_ack_i(wbd_spim_ack_i),
+    .s0_wbd_bry_o(wbd_spim_bry_o),
+    .s0_wbd_cyc_o(wbd_spim_cyc_o),
+    .s0_wbd_lack_i(wbd_spim_lack_i),
+    .s0_wbd_stb_o(wbd_spim_stb_o),
+    .s0_wbd_we_o(wbd_spim_we_o),
+    .s1_wbd_ack_i(wbd_uart_ack_i),
+    .s1_wbd_cyc_o(wbd_uart_cyc_o),
+    .s1_wbd_stb_o(wbd_uart_stb_o),
+    .s1_wbd_we_o(wbd_uart_we_o),
+    .s2_wbd_ack_i(wbd_glbl_ack_i),
+    .s2_wbd_cyc_o(wbd_glbl_cyc_o),
+    .s2_wbd_stb_o(wbd_glbl_stb_o),
+    .s2_wbd_we_o(wbd_glbl_we_o),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_int),
+    .wbd_clk_wi(wbd_clk_wi_skew),
+    .cfg_cska_wi({\cfg_clk_skew_ctrl1[3] ,
+    \cfg_clk_skew_ctrl1[2] ,
+    \cfg_clk_skew_ctrl1[1] ,
+    \cfg_clk_skew_ctrl1[0] }),
+    .ch_clk_in({cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    cpu_clk,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int,
+    wbd_clk_int}),
+    .ch_clk_out({\cpu_clk_rp[9] ,
+    \cpu_clk_rp[8] ,
+    \cpu_clk_rp[7] ,
+    \cpu_clk_rp[6] ,
+    \u_riscv_top.core_clk_int[5] ,
+    \u_riscv_top.core_clk_int[4] ,
+    \u_riscv_top.core_clk_int[3] ,
+    \u_riscv_top.core_clk_int[2] ,
+    \u_riscv_top.core_clk_int[1] ,
+    \u_riscv_top.core_clk_int[0] ,
+    wbd_clk_pinmux_rp,
+    wbd_clk_uart_rp,
+    wbd_clk_qspi_rp,
+    \u_riscv_top.wbd_clk_int }),
+    .ch_data_in({\cfg_clk_skew_ctrl2[31] ,
+    \cfg_clk_skew_ctrl2[30] ,
+    \cfg_clk_skew_ctrl2[29] ,
+    \cfg_clk_skew_ctrl2[28] ,
+    \cfg_clk_skew_ctrl2[27] ,
+    \cfg_clk_skew_ctrl2[26] ,
+    \cfg_clk_skew_ctrl2[25] ,
+    \cfg_clk_skew_ctrl2[24] ,
+    \strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] ,
+    \strap_uartm[1] ,
+    \strap_uartm[0] ,
+    \system_strap[31] ,
+    \system_strap[30] ,
+    \system_strap[29] ,
+    \system_strap[28] ,
+    \system_strap[27] ,
+    \system_strap[26] ,
+    \system_strap[25] ,
+    \system_strap[24] ,
+    \system_strap[23] ,
+    \system_strap[22] ,
+    \system_strap[21] ,
+    \system_strap[20] ,
+    \system_strap[19] ,
+    \system_strap[18] ,
+    \system_strap[17] ,
+    \system_strap[16] ,
+    \system_strap[15] ,
+    \system_strap[14] ,
+    \system_strap[13] ,
+    \system_strap[12] ,
+    \system_strap[11] ,
+    \system_strap[10] ,
+    \system_strap[9] ,
+    \system_strap[8] ,
+    \system_strap[7] ,
+    \system_strap[6] ,
+    \system_strap[5] ,
+    \system_strap[4] ,
+    \system_strap[3] ,
+    \system_strap[2] ,
+    \system_strap[1] ,
+    \system_strap[0] ,
+    p_reset_n,
+    e_reset_n,
+    cfg_strap_pad_ctrl,
+    soft_irq,
+    \irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] ,
+    \cfg_clk_skew_ctrl2[23] ,
+    \cfg_clk_skew_ctrl2[22] ,
+    \cfg_clk_skew_ctrl2[21] ,
+    \cfg_clk_skew_ctrl2[20] ,
+    \cfg_clk_skew_ctrl2[19] ,
+    \cfg_clk_skew_ctrl2[18] ,
+    \cfg_clk_skew_ctrl2[17] ,
+    \cfg_clk_skew_ctrl2[16] ,
+    \cfg_clk_skew_ctrl2[15] ,
+    \cfg_clk_skew_ctrl2[14] ,
+    \cfg_clk_skew_ctrl2[13] ,
+    \cfg_clk_skew_ctrl2[12] ,
+    \cfg_clk_skew_ctrl2[11] ,
+    \cfg_clk_skew_ctrl2[10] ,
+    \cfg_clk_skew_ctrl2[9] ,
+    \cfg_clk_skew_ctrl2[8] ,
+    \cfg_clk_skew_ctrl2[7] ,
+    \cfg_clk_skew_ctrl2[6] ,
+    \cfg_clk_skew_ctrl2[5] ,
+    \cfg_clk_skew_ctrl2[4] ,
+    \cfg_clk_skew_ctrl2[3] ,
+    \cfg_clk_skew_ctrl2[2] ,
+    \cfg_clk_skew_ctrl2[1] ,
+    \cfg_clk_skew_ctrl2[0] ,
+    \cfg_clk_skew_ctrl1[27] ,
+    \cfg_clk_skew_ctrl1[26] ,
+    \cfg_clk_skew_ctrl1[25] ,
+    \cfg_clk_skew_ctrl1[24] ,
+    \cfg_clk_skew_ctrl1[23] ,
+    \cfg_clk_skew_ctrl1[22] ,
+    \cfg_clk_skew_ctrl1[21] ,
+    \cfg_clk_skew_ctrl1[20] ,
+    \cfg_clk_skew_ctrl1[19] ,
+    \cfg_clk_skew_ctrl1[18] ,
+    \cfg_clk_skew_ctrl1[17] ,
+    \cfg_clk_skew_ctrl1[16] ,
+    \cfg_clk_skew_ctrl1[15] ,
+    \cfg_clk_skew_ctrl1[14] ,
+    \cfg_clk_skew_ctrl1[13] ,
+    \cfg_clk_skew_ctrl1[12] ,
+    \cfg_clk_skew_ctrl1[11] ,
+    \cfg_clk_skew_ctrl1[10] ,
+    \cfg_clk_skew_ctrl1[9] ,
+    \cfg_clk_skew_ctrl1[8] }),
+    .ch_data_out({\cfg_ccska_fpu_rp[3] ,
+    \cfg_ccska_fpu_rp[2] ,
+    \cfg_ccska_fpu_rp[1] ,
+    \cfg_ccska_fpu_rp[0] ,
+    \cfg_ccska_aes_rp[3] ,
+    \cfg_ccska_aes_rp[2] ,
+    \cfg_ccska_aes_rp[1] ,
+    \cfg_ccska_aes_rp[0] ,
+    \strap_sticky_rp[31] ,
+    \strap_sticky_rp[30] ,
+    \strap_sticky_rp[29] ,
+    \strap_sticky_rp[28] ,
+    \strap_sticky_rp[27] ,
+    \strap_sticky_rp[26] ,
+    \strap_sticky_rp[25] ,
+    \strap_sticky_rp[24] ,
+    \strap_sticky_rp[23] ,
+    \strap_sticky_rp[22] ,
+    \strap_sticky_rp[21] ,
+    \strap_sticky_rp[20] ,
+    \strap_sticky_rp[19] ,
+    \strap_sticky_rp[18] ,
+    \strap_sticky_rp[17] ,
+    \strap_sticky_rp[16] ,
+    \strap_sticky_rp[15] ,
+    \strap_sticky_rp[14] ,
+    \strap_sticky_rp[13] ,
+    \strap_sticky_rp[12] ,
+    \strap_sticky_rp[11] ,
+    \strap_sticky_rp[10] ,
+    \strap_sticky_rp[9] ,
+    \strap_sticky_rp[8] ,
+    \strap_sticky_rp[7] ,
+    \strap_sticky_rp[6] ,
+    \strap_sticky_rp[5] ,
+    \strap_sticky_rp[4] ,
+    \strap_sticky_rp[3] ,
+    \strap_sticky_rp[2] ,
+    \strap_sticky_rp[1] ,
+    \strap_sticky_rp[0] ,
+    \strap_uartm_rp[1] ,
+    \strap_uartm_rp[0] ,
+    \system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] ,
+    p_reset_n_rp,
+    e_reset_n_rp,
+    cfg_strap_pad_ctrl_rp,
+    \u_riscv_top.soft_irq ,
+    \u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] ,
+    \cfg_ccska_riscv_core3_rp[3] ,
+    \cfg_ccska_riscv_core3_rp[2] ,
+    \cfg_ccska_riscv_core3_rp[1] ,
+    \cfg_ccska_riscv_core3_rp[0] ,
+    \cfg_ccska_riscv_core2_rp[3] ,
+    \cfg_ccska_riscv_core2_rp[2] ,
+    \cfg_ccska_riscv_core2_rp[1] ,
+    \cfg_ccska_riscv_core2_rp[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] ,
+    \cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] ,
+    \cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] ,
+    \cfg_wcska_uart_rp[3] ,
+    \cfg_wcska_uart_rp[2] ,
+    \cfg_wcska_uart_rp[1] ,
+    \cfg_wcska_uart_rp[0] ,
+    \cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .m0_wbd_adr_i({\wbd_int_adr_i[31] ,
+    \wbd_int_adr_i[30] ,
+    \wbd_int_adr_i[29] ,
+    \wbd_int_adr_i[28] ,
+    \wbd_int_adr_i[27] ,
+    \wbd_int_adr_i[26] ,
+    \wbd_int_adr_i[25] ,
+    \wbd_int_adr_i[24] ,
+    \wbd_int_adr_i[23] ,
+    \wbd_int_adr_i[22] ,
+    \wbd_int_adr_i[21] ,
+    \wbd_int_adr_i[20] ,
+    \wbd_int_adr_i[19] ,
+    \wbd_int_adr_i[18] ,
+    \wbd_int_adr_i[17] ,
+    \wbd_int_adr_i[16] ,
+    \wbd_int_adr_i[15] ,
+    \wbd_int_adr_i[14] ,
+    \wbd_int_adr_i[13] ,
+    \wbd_int_adr_i[12] ,
+    \wbd_int_adr_i[11] ,
+    \wbd_int_adr_i[10] ,
+    \wbd_int_adr_i[9] ,
+    \wbd_int_adr_i[8] ,
+    \wbd_int_adr_i[7] ,
+    \wbd_int_adr_i[6] ,
+    \wbd_int_adr_i[5] ,
+    \wbd_int_adr_i[4] ,
+    \wbd_int_adr_i[3] ,
+    \wbd_int_adr_i[2] ,
+    \wbd_int_adr_i[1] ,
+    \wbd_int_adr_i[0] }),
+    .m0_wbd_dat_i({\wbd_int_dat_i[31] ,
+    \wbd_int_dat_i[30] ,
+    \wbd_int_dat_i[29] ,
+    \wbd_int_dat_i[28] ,
+    \wbd_int_dat_i[27] ,
+    \wbd_int_dat_i[26] ,
+    \wbd_int_dat_i[25] ,
+    \wbd_int_dat_i[24] ,
+    \wbd_int_dat_i[23] ,
+    \wbd_int_dat_i[22] ,
+    \wbd_int_dat_i[21] ,
+    \wbd_int_dat_i[20] ,
+    \wbd_int_dat_i[19] ,
+    \wbd_int_dat_i[18] ,
+    \wbd_int_dat_i[17] ,
+    \wbd_int_dat_i[16] ,
+    \wbd_int_dat_i[15] ,
+    \wbd_int_dat_i[14] ,
+    \wbd_int_dat_i[13] ,
+    \wbd_int_dat_i[12] ,
+    \wbd_int_dat_i[11] ,
+    \wbd_int_dat_i[10] ,
+    \wbd_int_dat_i[9] ,
+    \wbd_int_dat_i[8] ,
+    \wbd_int_dat_i[7] ,
+    \wbd_int_dat_i[6] ,
+    \wbd_int_dat_i[5] ,
+    \wbd_int_dat_i[4] ,
+    \wbd_int_dat_i[3] ,
+    \wbd_int_dat_i[2] ,
+    \wbd_int_dat_i[1] ,
+    \wbd_int_dat_i[0] }),
+    .m0_wbd_dat_o({\wbd_int_dat_o[31] ,
+    \wbd_int_dat_o[30] ,
+    \wbd_int_dat_o[29] ,
+    \wbd_int_dat_o[28] ,
+    \wbd_int_dat_o[27] ,
+    \wbd_int_dat_o[26] ,
+    \wbd_int_dat_o[25] ,
+    \wbd_int_dat_o[24] ,
+    \wbd_int_dat_o[23] ,
+    \wbd_int_dat_o[22] ,
+    \wbd_int_dat_o[21] ,
+    \wbd_int_dat_o[20] ,
+    \wbd_int_dat_o[19] ,
+    \wbd_int_dat_o[18] ,
+    \wbd_int_dat_o[17] ,
+    \wbd_int_dat_o[16] ,
+    \wbd_int_dat_o[15] ,
+    \wbd_int_dat_o[14] ,
+    \wbd_int_dat_o[13] ,
+    \wbd_int_dat_o[12] ,
+    \wbd_int_dat_o[11] ,
+    \wbd_int_dat_o[10] ,
+    \wbd_int_dat_o[9] ,
+    \wbd_int_dat_o[8] ,
+    \wbd_int_dat_o[7] ,
+    \wbd_int_dat_o[6] ,
+    \wbd_int_dat_o[5] ,
+    \wbd_int_dat_o[4] ,
+    \wbd_int_dat_o[3] ,
+    \wbd_int_dat_o[2] ,
+    \wbd_int_dat_o[1] ,
+    \wbd_int_dat_o[0] }),
+    .m0_wbd_sel_i({\wbd_int_sel_i[3] ,
+    \wbd_int_sel_i[2] ,
+    \wbd_int_sel_i[1] ,
+    \wbd_int_sel_i[0] }),
+    .m1_wbd_adr_i({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .m1_wbd_bl_i({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .m1_wbd_dat_i({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .m1_wbd_dat_o({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .m1_wbd_sel_i({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }),
+    .m2_wbd_adr_i({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .m2_wbd_bl_i({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .m2_wbd_dat_i({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .m2_wbd_dat_o({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .m2_wbd_sel_i({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .m3_wbd_adr_i({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .m3_wbd_bl_i({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .m3_wbd_dat_o({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .m3_wbd_sel_i({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .s0_wbd_adr_o({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .s0_wbd_bl_o({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .s0_wbd_dat_i({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .s0_wbd_dat_o({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .s0_wbd_sel_o({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }),
+    .s1_wbd_adr_o({\wbd_uart_adr_o[8] ,
+    \wbd_uart_adr_o[7] ,
+    \wbd_uart_adr_o[6] ,
+    \wbd_uart_adr_o[5] ,
+    \wbd_uart_adr_o[4] ,
+    \wbd_uart_adr_o[3] ,
+    \wbd_uart_adr_o[2] ,
+    \wbd_uart_adr_o[1] ,
+    \wbd_uart_adr_o[0] }),
+    .s1_wbd_dat_i({\wbd_uart_dat_i[31] ,
+    \wbd_uart_dat_i[30] ,
+    \wbd_uart_dat_i[29] ,
+    \wbd_uart_dat_i[28] ,
+    \wbd_uart_dat_i[27] ,
+    \wbd_uart_dat_i[26] ,
+    \wbd_uart_dat_i[25] ,
+    \wbd_uart_dat_i[24] ,
+    \wbd_uart_dat_i[23] ,
+    \wbd_uart_dat_i[22] ,
+    \wbd_uart_dat_i[21] ,
+    \wbd_uart_dat_i[20] ,
+    \wbd_uart_dat_i[19] ,
+    \wbd_uart_dat_i[18] ,
+    \wbd_uart_dat_i[17] ,
+    \wbd_uart_dat_i[16] ,
+    \wbd_uart_dat_i[15] ,
+    \wbd_uart_dat_i[14] ,
+    \wbd_uart_dat_i[13] ,
+    \wbd_uart_dat_i[12] ,
+    \wbd_uart_dat_i[11] ,
+    \wbd_uart_dat_i[10] ,
+    \wbd_uart_dat_i[9] ,
+    \wbd_uart_dat_i[8] ,
+    \wbd_uart_dat_i[7] ,
+    \wbd_uart_dat_i[6] ,
+    \wbd_uart_dat_i[5] ,
+    \wbd_uart_dat_i[4] ,
+    \wbd_uart_dat_i[3] ,
+    \wbd_uart_dat_i[2] ,
+    \wbd_uart_dat_i[1] ,
+    \wbd_uart_dat_i[0] }),
+    .s1_wbd_dat_o({\wbd_uart_dat_o[31] ,
+    \wbd_uart_dat_o[30] ,
+    \wbd_uart_dat_o[29] ,
+    \wbd_uart_dat_o[28] ,
+    \wbd_uart_dat_o[27] ,
+    \wbd_uart_dat_o[26] ,
+    \wbd_uart_dat_o[25] ,
+    \wbd_uart_dat_o[24] ,
+    \wbd_uart_dat_o[23] ,
+    \wbd_uart_dat_o[22] ,
+    \wbd_uart_dat_o[21] ,
+    \wbd_uart_dat_o[20] ,
+    \wbd_uart_dat_o[19] ,
+    \wbd_uart_dat_o[18] ,
+    \wbd_uart_dat_o[17] ,
+    \wbd_uart_dat_o[16] ,
+    \wbd_uart_dat_o[15] ,
+    \wbd_uart_dat_o[14] ,
+    \wbd_uart_dat_o[13] ,
+    \wbd_uart_dat_o[12] ,
+    \wbd_uart_dat_o[11] ,
+    \wbd_uart_dat_o[10] ,
+    \wbd_uart_dat_o[9] ,
+    \wbd_uart_dat_o[8] ,
+    \wbd_uart_dat_o[7] ,
+    \wbd_uart_dat_o[6] ,
+    \wbd_uart_dat_o[5] ,
+    \wbd_uart_dat_o[4] ,
+    \wbd_uart_dat_o[3] ,
+    \wbd_uart_dat_o[2] ,
+    \wbd_uart_dat_o[1] ,
+    \wbd_uart_dat_o[0] }),
+    .s1_wbd_sel_o({\wbd_uart_sel_o[3] ,
+    \wbd_uart_sel_o[2] ,
+    \wbd_uart_sel_o[1] ,
+    \wbd_uart_sel_o[0] }),
+    .s2_wbd_adr_o({\wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .s2_wbd_dat_i({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .s2_wbd_dat_o({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .s2_wbd_sel_o({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }));
+ pinmux_top u_pinmux (.cfg_dco_mode(cfg_dco_mode),
+    .cfg_pll_enb(cfg_pll_enb),
+    .cfg_strap_pad_ctrl(cfg_strap_pad_ctrl_rp),
+    .cpu_clk(\cpu_clk_rp[8] ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .e_reset_n(e_reset_n_rp),
+    .i2cm_clk_i(i2cm_clk_i),
+    .i2cm_clk_o(i2cm_clk_o),
+    .i2cm_clk_oen(i2cm_clk_oen),
+    .i2cm_data_i(i2cm_data_i),
+    .i2cm_data_o(i2cm_data_o),
+    .i2cm_data_oen(i2cm_data_oen),
+    .i2cm_intr(i2cm_intr_o),
+    .i2cm_rst_n(i2c_rst_n),
+    .int_pll_clock(\pll_clk_out[0] ),
+    .mclk(wbd_clk_pinmux_skew),
+    .p_reset_n(p_reset_n_rp),
+    .pll_ref_clk(pll_ref_clk),
+    .pulse1m_mclk(pulse1m_mclk),
+    .qspim_rst_n(qspim_rst_n),
+    .reg_ack(wbd_glbl_ack_i),
+    .reg_cs(wbd_glbl_stb_o),
+    .reg_wr(wbd_glbl_we_o),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .s_reset_n(\u_riscv_top.pwrup_rst_n ),
+    .sflash_sck(sflash_sck),
+    .soft_irq(soft_irq),
+    .spim_miso(sspim_so),
+    .spim_mosi(sspim_si),
+    .spim_sck(sspim_sck),
+    .spis_miso(sspis_so),
+    .spis_mosi(sspis_si),
+    .spis_sck(sspis_sck),
+    .spis_ssn(sspis_ssn),
+    .sspim_rst_n(sspim_rst_n),
+    .uartm_rxd(uartm_rxd),
+    .uartm_txd(uartm_txd),
+    .usb_clk(usb_clk),
+    .usb_dn_i(usb_dn_i),
+    .usb_dn_o(usb_dn_o),
+    .usb_dp_i(usb_dp_i),
+    .usb_dp_o(usb_dp_o),
+    .usb_intr(usb_intr_o),
+    .usb_oen(usb_oen),
+    .usb_rst_n(usb_rst_n),
+    .user_clock1(wb_clk_i),
+    .user_clock2(user_clock2),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_clk_int(wbd_clk_pinmux_rp),
+    .wbd_clk_pinmux(wbd_clk_pinmux_skew),
+    .xtal_clk(xtal_clk),
+    .cfg_cska_pinmux({\cfg_wcska_pinmux_rp[3] ,
+    \cfg_wcska_pinmux_rp[2] ,
+    \cfg_wcska_pinmux_rp[1] ,
+    \cfg_wcska_pinmux_rp[0] }),
+    .cfg_dac0_mux_sel({\cfg_dac0_mux_sel[7] ,
+    \cfg_dac0_mux_sel[6] ,
+    \cfg_dac0_mux_sel[5] ,
+    \cfg_dac0_mux_sel[4] ,
+    \cfg_dac0_mux_sel[3] ,
+    \cfg_dac0_mux_sel[2] ,
+    \cfg_dac0_mux_sel[1] ,
+    \cfg_dac0_mux_sel[0] }),
+    .cfg_dac1_mux_sel({\cfg_dac1_mux_sel[7] ,
+    \cfg_dac1_mux_sel[6] ,
+    \cfg_dac1_mux_sel[5] ,
+    \cfg_dac1_mux_sel[4] ,
+    \cfg_dac1_mux_sel[3] ,
+    \cfg_dac1_mux_sel[2] ,
+    \cfg_dac1_mux_sel[1] ,
+    \cfg_dac1_mux_sel[0] }),
+    .cfg_dac2_mux_sel({\cfg_dac2_mux_sel[7] ,
+    \cfg_dac2_mux_sel[6] ,
+    \cfg_dac2_mux_sel[5] ,
+    \cfg_dac2_mux_sel[4] ,
+    \cfg_dac2_mux_sel[3] ,
+    \cfg_dac2_mux_sel[2] ,
+    \cfg_dac2_mux_sel[1] ,
+    \cfg_dac2_mux_sel[0] }),
+    .cfg_dac3_mux_sel({\cfg_dac3_mux_sel[7] ,
+    \cfg_dac3_mux_sel[6] ,
+    \cfg_dac3_mux_sel[5] ,
+    \cfg_dac3_mux_sel[4] ,
+    \cfg_dac3_mux_sel[3] ,
+    \cfg_dac3_mux_sel[2] ,
+    \cfg_dac3_mux_sel[1] ,
+    \cfg_dac3_mux_sel[0] }),
+    .cfg_dc_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }),
+    .cfg_pll_fed_div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .cfg_riscv_ctrl({\cfg_riscv_ctrl[15] ,
+    \cfg_riscv_ctrl[14] ,
+    \cfg_riscv_ctrl[13] ,
+    \cfg_riscv_ctrl[12] ,
+    \cfg_riscv_ctrl[11] ,
+    \cfg_riscv_ctrl[10] ,
+    \cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] ,
+    \cfg_riscv_ctrl[7] ,
+    \cfg_riscv_ctrl[6] ,
+    \cfg_riscv_ctrl[5] ,
+    \cfg_riscv_ctrl[4] ,
+    \cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] ,
+    \cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cpu_core_rst_n({\cpu_core_rst_n[3] ,
+    \cpu_core_rst_n[2] ,
+    \cpu_core_rst_n[1] ,
+    \cpu_core_rst_n[0] }),
+    .digital_io_in({io_in[37],
+    io_in[36],
+    io_in[35],
+    io_in[34],
+    io_in[33],
+    io_in[32],
+    io_in[31],
+    io_in[30],
+    io_in[29],
+    io_in[28],
+    io_in[27],
+    io_in[26],
+    io_in[25],
+    io_in[24],
+    io_in[23],
+    io_in[22],
+    io_in[21],
+    io_in[20],
+    io_in[19],
+    io_in[18],
+    io_in[17],
+    io_in[16],
+    io_in[15],
+    io_in[14],
+    io_in[13],
+    io_in[12],
+    io_in[11],
+    io_in[10],
+    io_in[9],
+    io_in[8],
+    io_in[7],
+    io_in[6],
+    io_in[5],
+    io_in[4],
+    io_in[3],
+    io_in[2],
+    io_in[1],
+    io_in[0]}),
+    .digital_io_oen({io_oeb[37],
+    io_oeb[36],
+    io_oeb[35],
+    io_oeb[34],
+    io_oeb[33],
+    io_oeb[32],
+    io_oeb[31],
+    io_oeb[30],
+    io_oeb[29],
+    io_oeb[28],
+    io_oeb[27],
+    io_oeb[26],
+    io_oeb[25],
+    io_oeb[24],
+    io_oeb[23],
+    io_oeb[22],
+    io_oeb[21],
+    io_oeb[20],
+    io_oeb[19],
+    io_oeb[18],
+    io_oeb[17],
+    io_oeb[16],
+    io_oeb[15],
+    io_oeb[14],
+    io_oeb[13],
+    io_oeb[12],
+    io_oeb[11],
+    io_oeb[10],
+    io_oeb[9],
+    io_oeb[8],
+    io_oeb[7],
+    io_oeb[6],
+    io_oeb[5],
+    io_oeb[4],
+    io_oeb[3],
+    io_oeb[2],
+    io_oeb[1],
+    io_oeb[0]}),
+    .digital_io_out({io_out[37],
+    io_out[36],
+    io_out[35],
+    io_out[34],
+    io_out[33],
+    io_out[32],
+    io_out[31],
+    io_out[30],
+    io_out[29],
+    io_out[28],
+    io_out[27],
+    io_out[26],
+    io_out[25],
+    io_out[24],
+    io_out[23],
+    io_out[22],
+    io_out[21],
+    io_out[20],
+    io_out[19],
+    io_out[18],
+    io_out[17],
+    io_out[16],
+    io_out[15],
+    io_out[14],
+    io_out[13],
+    io_out[12],
+    io_out[11],
+    io_out[10],
+    io_out[9],
+    io_out[8],
+    io_out[7],
+    io_out[6],
+    io_out[5],
+    io_out[4],
+    io_out[3],
+    io_out[2],
+    io_out[1],
+    io_out[0]}),
+    .irq_lines({\irq_lines[31] ,
+    \irq_lines[30] ,
+    \irq_lines[29] ,
+    \irq_lines[28] ,
+    \irq_lines[27] ,
+    \irq_lines[26] ,
+    \irq_lines[25] ,
+    \irq_lines[24] ,
+    \irq_lines[23] ,
+    \irq_lines[22] ,
+    \irq_lines[21] ,
+    \irq_lines[20] ,
+    \irq_lines[19] ,
+    \irq_lines[18] ,
+    \irq_lines[17] ,
+    \irq_lines[16] ,
+    \irq_lines[15] ,
+    \irq_lines[14] ,
+    \irq_lines[13] ,
+    \irq_lines[12] ,
+    \irq_lines[11] ,
+    \irq_lines[10] ,
+    \irq_lines[9] ,
+    \irq_lines[8] ,
+    \irq_lines[7] ,
+    \irq_lines[6] ,
+    \irq_lines[5] ,
+    \irq_lines[4] ,
+    \irq_lines[3] ,
+    \irq_lines[2] ,
+    \irq_lines[1] ,
+    \irq_lines[0] }),
+    .pinmux_debug({la_data_out[127],
+    la_data_out[126],
+    la_data_out[125],
+    la_data_out[124],
+    la_data_out[123],
+    la_data_out[122],
+    la_data_out[121],
+    la_data_out[120],
+    la_data_out[119],
+    la_data_out[118],
+    la_data_out[117],
+    la_data_out[116],
+    la_data_out[115],
+    la_data_out[114],
+    la_data_out[113],
+    la_data_out[112],
+    la_data_out[111],
+    la_data_out[110],
+    la_data_out[109],
+    la_data_out[108],
+    la_data_out[107],
+    la_data_out[106],
+    la_data_out[105],
+    la_data_out[104],
+    la_data_out[103],
+    la_data_out[102],
+    la_data_out[101],
+    la_data_out[100],
+    la_data_out[99],
+    la_data_out[98],
+    la_data_out[97],
+    la_data_out[96]}),
+    .reg_addr({\wbd_glbl_adr_o[9] ,
+    \wbd_glbl_adr_o[8] ,
+    \wbd_glbl_adr_o[7] ,
+    \wbd_glbl_adr_o[6] ,
+    \wbd_glbl_adr_o[5] ,
+    \wbd_glbl_adr_o[4] ,
+    \wbd_glbl_adr_o[3] ,
+    \wbd_glbl_adr_o[2] ,
+    \wbd_glbl_adr_o[1] ,
+    \wbd_glbl_adr_o[0] }),
+    .reg_be({\wbd_glbl_sel_o[3] ,
+    \wbd_glbl_sel_o[2] ,
+    \wbd_glbl_sel_o[1] ,
+    \wbd_glbl_sel_o[0] }),
+    .reg_rdata({\wbd_glbl_dat_i[31] ,
+    \wbd_glbl_dat_i[30] ,
+    \wbd_glbl_dat_i[29] ,
+    \wbd_glbl_dat_i[28] ,
+    \wbd_glbl_dat_i[27] ,
+    \wbd_glbl_dat_i[26] ,
+    \wbd_glbl_dat_i[25] ,
+    \wbd_glbl_dat_i[24] ,
+    \wbd_glbl_dat_i[23] ,
+    \wbd_glbl_dat_i[22] ,
+    \wbd_glbl_dat_i[21] ,
+    \wbd_glbl_dat_i[20] ,
+    \wbd_glbl_dat_i[19] ,
+    \wbd_glbl_dat_i[18] ,
+    \wbd_glbl_dat_i[17] ,
+    \wbd_glbl_dat_i[16] ,
+    \wbd_glbl_dat_i[15] ,
+    \wbd_glbl_dat_i[14] ,
+    \wbd_glbl_dat_i[13] ,
+    \wbd_glbl_dat_i[12] ,
+    \wbd_glbl_dat_i[11] ,
+    \wbd_glbl_dat_i[10] ,
+    \wbd_glbl_dat_i[9] ,
+    \wbd_glbl_dat_i[8] ,
+    \wbd_glbl_dat_i[7] ,
+    \wbd_glbl_dat_i[6] ,
+    \wbd_glbl_dat_i[5] ,
+    \wbd_glbl_dat_i[4] ,
+    \wbd_glbl_dat_i[3] ,
+    \wbd_glbl_dat_i[2] ,
+    \wbd_glbl_dat_i[1] ,
+    \wbd_glbl_dat_i[0] }),
+    .reg_wdata({\wbd_glbl_dat_o[31] ,
+    \wbd_glbl_dat_o[30] ,
+    \wbd_glbl_dat_o[29] ,
+    \wbd_glbl_dat_o[28] ,
+    \wbd_glbl_dat_o[27] ,
+    \wbd_glbl_dat_o[26] ,
+    \wbd_glbl_dat_o[25] ,
+    \wbd_glbl_dat_o[24] ,
+    \wbd_glbl_dat_o[23] ,
+    \wbd_glbl_dat_o[22] ,
+    \wbd_glbl_dat_o[21] ,
+    \wbd_glbl_dat_o[20] ,
+    \wbd_glbl_dat_o[19] ,
+    \wbd_glbl_dat_o[18] ,
+    \wbd_glbl_dat_o[17] ,
+    \wbd_glbl_dat_o[16] ,
+    \wbd_glbl_dat_o[15] ,
+    \wbd_glbl_dat_o[14] ,
+    \wbd_glbl_dat_o[13] ,
+    \wbd_glbl_dat_o[12] ,
+    \wbd_glbl_dat_o[11] ,
+    \wbd_glbl_dat_o[10] ,
+    \wbd_glbl_dat_o[9] ,
+    \wbd_glbl_dat_o[8] ,
+    \wbd_glbl_dat_o[7] ,
+    \wbd_glbl_dat_o[6] ,
+    \wbd_glbl_dat_o[5] ,
+    \wbd_glbl_dat_o[4] ,
+    \wbd_glbl_dat_o[3] ,
+    \wbd_glbl_dat_o[2] ,
+    \wbd_glbl_dat_o[1] ,
+    \wbd_glbl_dat_o[0] }),
+    .sflash_di({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .sflash_do({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .sflash_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .sflash_ss({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spim_ssn({\sspim_ssn[3] ,
+    \sspim_ssn[2] ,
+    \sspim_ssn[1] ,
+    \sspim_ssn[0] }),
+    .strap_sticky({\strap_sticky[31] ,
+    \strap_sticky[30] ,
+    \strap_sticky[29] ,
+    \strap_sticky[28] ,
+    \strap_sticky[27] ,
+    \strap_sticky[26] ,
+    \strap_sticky[25] ,
+    \strap_sticky[24] ,
+    \strap_sticky[23] ,
+    \strap_sticky[22] ,
+    \strap_sticky[21] ,
+    \strap_sticky[20] ,
+    \strap_sticky[19] ,
+    \strap_sticky[18] ,
+    \strap_sticky[17] ,
+    \strap_sticky[16] ,
+    \strap_sticky[15] ,
+    \strap_sticky[14] ,
+    \strap_sticky[13] ,
+    \strap_sticky[12] ,
+    \strap_sticky[11] ,
+    \strap_sticky[10] ,
+    \strap_sticky[9] ,
+    \strap_sticky[8] ,
+    \strap_sticky[7] ,
+    \strap_sticky[6] ,
+    \strap_sticky[5] ,
+    \strap_sticky[4] ,
+    \strap_sticky[3] ,
+    \strap_sticky[2] ,
+    \strap_sticky[1] ,
+    \strap_sticky[0] }),
+    .strap_uartm({\strap_uartm[1] ,
+    \strap_uartm[0] }),
+    .system_strap({\system_strap_rp[31] ,
+    \system_strap_rp[30] ,
+    \system_strap_rp[29] ,
+    \system_strap_rp[28] ,
+    \system_strap_rp[27] ,
+    \system_strap_rp[26] ,
+    \system_strap_rp[25] ,
+    \system_strap_rp[24] ,
+    \system_strap_rp[23] ,
+    \system_strap_rp[22] ,
+    \system_strap_rp[21] ,
+    \system_strap_rp[20] ,
+    \system_strap_rp[19] ,
+    \system_strap_rp[18] ,
+    \system_strap_rp[17] ,
+    \system_strap_rp[16] ,
+    \system_strap_rp[15] ,
+    \system_strap_rp[14] ,
+    \system_strap_rp[13] ,
+    \system_strap_rp[12] ,
+    \system_strap_rp[11] ,
+    \system_strap_rp[10] ,
+    \system_strap_rp[9] ,
+    \system_strap_rp[8] ,
+    \system_strap_rp[7] ,
+    \system_strap_rp[6] ,
+    \system_strap_rp[5] ,
+    \system_strap_rp[4] ,
+    \system_strap_rp[3] ,
+    \system_strap_rp[2] ,
+    \system_strap_rp[1] ,
+    \system_strap_rp[0] }),
+    .uart_rst_n({\uart_rst_n[1] ,
+    \uart_rst_n[0] }),
+    .uart_rxd({\uart_rxd[1] ,
+    \uart_rxd[0] }),
+    .uart_txd({\uart_txd[1] ,
+    \uart_txd[0] }),
+    .user_irq({user_irq[2],
+    user_irq[1],
+    user_irq[0]}));
+ dg_pll u_pll (.VGND(vssd1),
+    .VPWR(vccd1),
+    .dco(cfg_dco_mode),
+    .enable(cfg_pll_enb),
+    .osc(pll_ref_clk),
+    .resetb(wbd_pll_rst_n),
+    .clockp({\pll_clk_out[1] ,
+    \pll_clk_out[0] }),
+    .div({\cfg_pll_fed_div[4] ,
+    \cfg_pll_fed_div[3] ,
+    \cfg_pll_fed_div[2] ,
+    \cfg_pll_fed_div[1] ,
+    \cfg_pll_fed_div[0] }),
+    .ext_trim({\cfg_dc_trim[25] ,
+    \cfg_dc_trim[24] ,
+    \cfg_dc_trim[23] ,
+    \cfg_dc_trim[22] ,
+    \cfg_dc_trim[21] ,
+    \cfg_dc_trim[20] ,
+    \cfg_dc_trim[19] ,
+    \cfg_dc_trim[18] ,
+    \cfg_dc_trim[17] ,
+    \cfg_dc_trim[16] ,
+    \cfg_dc_trim[15] ,
+    \cfg_dc_trim[14] ,
+    \cfg_dc_trim[13] ,
+    \cfg_dc_trim[12] ,
+    \cfg_dc_trim[11] ,
+    \cfg_dc_trim[10] ,
+    \cfg_dc_trim[9] ,
+    \cfg_dc_trim[8] ,
+    \cfg_dc_trim[7] ,
+    \cfg_dc_trim[6] ,
+    \cfg_dc_trim[5] ,
+    \cfg_dc_trim[4] ,
+    \cfg_dc_trim[3] ,
+    \cfg_dc_trim[2] ,
+    \cfg_dc_trim[1] ,
+    \cfg_dc_trim[0] }));
+ qspim_top u_qspi_master (.cfg_init_bypass(\system_strap[30] ),
+    .mclk(wbd_clk_spi),
+    .rst_n(qspim_rst_n),
+    .spi_clk(sflash_sck),
+    .strap_pre_sram(\system_strap[15] ),
+    .strap_sram(\system_strap[9] ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wbd_ack_o(wbd_spim_ack_i),
+    .wbd_bry_i(wbd_spim_bry_o),
+    .wbd_clk_int(wbd_clk_qspi_rp),
+    .wbd_clk_spi(wbd_clk_spi),
+    .wbd_err_o(wbd_spim_err_i),
+    .wbd_lack_o(wbd_spim_lack_i),
+    .wbd_stb_i(wbd_spim_stb_o),
+    .wbd_we_i(wbd_spim_we_o),
+    .cfg_cska_sp_co({\cfg_wcska_qspi_co_rp[3] ,
+    \cfg_wcska_qspi_co_rp[2] ,
+    \cfg_wcska_qspi_co_rp[1] ,
+    \cfg_wcska_qspi_co_rp[0] }),
+    .cfg_cska_spi({\cfg_wcska_qspi_rp[3] ,
+    \cfg_wcska_qspi_rp[2] ,
+    \cfg_wcska_qspi_rp[1] ,
+    \cfg_wcska_qspi_rp[0] }),
+    .spi_csn({\spi_csn[3] ,
+    \spi_csn[2] ,
+    \spi_csn[1] ,
+    \spi_csn[0] }),
+    .spi_debug({la_data_out[95],
+    la_data_out[94],
+    la_data_out[93],
+    la_data_out[92],
+    la_data_out[91],
+    la_data_out[90],
+    la_data_out[89],
+    la_data_out[88],
+    la_data_out[87],
+    la_data_out[86],
+    la_data_out[85],
+    la_data_out[84],
+    la_data_out[83],
+    la_data_out[82],
+    la_data_out[81],
+    la_data_out[80],
+    la_data_out[79],
+    la_data_out[78],
+    la_data_out[77],
+    la_data_out[76],
+    la_data_out[75],
+    la_data_out[74],
+    la_data_out[73],
+    la_data_out[72],
+    la_data_out[71],
+    la_data_out[70],
+    la_data_out[69],
+    la_data_out[68],
+    la_data_out[67],
+    la_data_out[66],
+    la_data_out[65],
+    la_data_out[64]}),
+    .spi_oen({\sflash_oen[3] ,
+    \sflash_oen[2] ,
+    \sflash_oen[1] ,
+    \sflash_oen[0] }),
+    .spi_sdi({\sflash_di[3] ,
+    \sflash_di[2] ,
+    \sflash_di[1] ,
+    \sflash_di[0] }),
+    .spi_sdo({\sflash_do[3] ,
+    \sflash_do[2] ,
+    \sflash_do[1] ,
+    \sflash_do[0] }),
+    .strap_flash({\system_strap[11] ,
+    \system_strap[10] }),
+    .wbd_adr_i({\wbd_spim_adr_o[31] ,
+    \wbd_spim_adr_o[30] ,
+    \wbd_spim_adr_o[29] ,
+    \wbd_spim_adr_o[28] ,
+    \wbd_spim_adr_o[27] ,
+    \wbd_spim_adr_o[26] ,
+    \wbd_spim_adr_o[25] ,
+    \wbd_spim_adr_o[24] ,
+    \wbd_spim_adr_o[23] ,
+    \wbd_spim_adr_o[22] ,
+    \wbd_spim_adr_o[21] ,
+    \wbd_spim_adr_o[20] ,
+    \wbd_spim_adr_o[19] ,
+    \wbd_spim_adr_o[18] ,
+    \wbd_spim_adr_o[17] ,
+    \wbd_spim_adr_o[16] ,
+    \wbd_spim_adr_o[15] ,
+    \wbd_spim_adr_o[14] ,
+    \wbd_spim_adr_o[13] ,
+    \wbd_spim_adr_o[12] ,
+    \wbd_spim_adr_o[11] ,
+    \wbd_spim_adr_o[10] ,
+    \wbd_spim_adr_o[9] ,
+    \wbd_spim_adr_o[8] ,
+    \wbd_spim_adr_o[7] ,
+    \wbd_spim_adr_o[6] ,
+    \wbd_spim_adr_o[5] ,
+    \wbd_spim_adr_o[4] ,
+    \wbd_spim_adr_o[3] ,
+    \wbd_spim_adr_o[2] ,
+    \wbd_spim_adr_o[1] ,
+    \wbd_spim_adr_o[0] }),
+    .wbd_bl_i({\wbd_spim_bl_o[9] ,
+    \wbd_spim_bl_o[8] ,
+    \wbd_spim_bl_o[7] ,
+    \wbd_spim_bl_o[6] ,
+    \wbd_spim_bl_o[5] ,
+    \wbd_spim_bl_o[4] ,
+    \wbd_spim_bl_o[3] ,
+    \wbd_spim_bl_o[2] ,
+    \wbd_spim_bl_o[1] ,
+    \wbd_spim_bl_o[0] }),
+    .wbd_dat_i({\wbd_spim_dat_o[31] ,
+    \wbd_spim_dat_o[30] ,
+    \wbd_spim_dat_o[29] ,
+    \wbd_spim_dat_o[28] ,
+    \wbd_spim_dat_o[27] ,
+    \wbd_spim_dat_o[26] ,
+    \wbd_spim_dat_o[25] ,
+    \wbd_spim_dat_o[24] ,
+    \wbd_spim_dat_o[23] ,
+    \wbd_spim_dat_o[22] ,
+    \wbd_spim_dat_o[21] ,
+    \wbd_spim_dat_o[20] ,
+    \wbd_spim_dat_o[19] ,
+    \wbd_spim_dat_o[18] ,
+    \wbd_spim_dat_o[17] ,
+    \wbd_spim_dat_o[16] ,
+    \wbd_spim_dat_o[15] ,
+    \wbd_spim_dat_o[14] ,
+    \wbd_spim_dat_o[13] ,
+    \wbd_spim_dat_o[12] ,
+    \wbd_spim_dat_o[11] ,
+    \wbd_spim_dat_o[10] ,
+    \wbd_spim_dat_o[9] ,
+    \wbd_spim_dat_o[8] ,
+    \wbd_spim_dat_o[7] ,
+    \wbd_spim_dat_o[6] ,
+    \wbd_spim_dat_o[5] ,
+    \wbd_spim_dat_o[4] ,
+    \wbd_spim_dat_o[3] ,
+    \wbd_spim_dat_o[2] ,
+    \wbd_spim_dat_o[1] ,
+    \wbd_spim_dat_o[0] }),
+    .wbd_dat_o({\wbd_spim_dat_i[31] ,
+    \wbd_spim_dat_i[30] ,
+    \wbd_spim_dat_i[29] ,
+    \wbd_spim_dat_i[28] ,
+    \wbd_spim_dat_i[27] ,
+    \wbd_spim_dat_i[26] ,
+    \wbd_spim_dat_i[25] ,
+    \wbd_spim_dat_i[24] ,
+    \wbd_spim_dat_i[23] ,
+    \wbd_spim_dat_i[22] ,
+    \wbd_spim_dat_i[21] ,
+    \wbd_spim_dat_i[20] ,
+    \wbd_spim_dat_i[19] ,
+    \wbd_spim_dat_i[18] ,
+    \wbd_spim_dat_i[17] ,
+    \wbd_spim_dat_i[16] ,
+    \wbd_spim_dat_i[15] ,
+    \wbd_spim_dat_i[14] ,
+    \wbd_spim_dat_i[13] ,
+    \wbd_spim_dat_i[12] ,
+    \wbd_spim_dat_i[11] ,
+    \wbd_spim_dat_i[10] ,
+    \wbd_spim_dat_i[9] ,
+    \wbd_spim_dat_i[8] ,
+    \wbd_spim_dat_i[7] ,
+    \wbd_spim_dat_i[6] ,
+    \wbd_spim_dat_i[5] ,
+    \wbd_spim_dat_i[4] ,
+    \wbd_spim_dat_i[3] ,
+    \wbd_spim_dat_i[2] ,
+    \wbd_spim_dat_i[1] ,
+    \wbd_spim_dat_i[0] }),
+    .wbd_sel_i({\wbd_spim_sel_o[3] ,
+    \wbd_spim_sel_o[2] ,
+    \wbd_spim_sel_o[1] ,
+    \wbd_spim_sel_o[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_0  (.clk(\u_riscv_top.core_clk_core0_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[0] ),
+    .core2dmem_cmd_o(\u_riscv_top.core0_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core0_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core0_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core0_imem_req ),
+    .core_clk_int(\u_riscv_top.core_clk_int[2] ),
+    .core_clk_skew(\u_riscv_top.core_clk_core0_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core0_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core0_soft_irq ),
+    .cpu_rst_n(\cpu_core_rst_n[0] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core0_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core0_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core0[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core0[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }));
+ ycr_core_top \u_riscv_top.i_core_top_1  (.clk(\u_riscv_top.core_clk_core1_skew ),
+    .clk_o(\u_riscv_top.core_clk_out[1] ),
+    .core2dmem_cmd_o(\u_riscv_top.core1_dmem_cmd ),
+    .core2dmem_req_o(\u_riscv_top.core1_dmem_req ),
+    .core2imem_cmd_o(\u_riscv_top.core1_imem_cmd ),
+    .core2imem_req_o(\u_riscv_top.core1_imem_req ),
+    .core_clk_int(\u_riscv_top.core_clk_int[3] ),
+    .core_clk_skew(\u_riscv_top.core_clk_core1_skew ),
+    .core_irq_mtimer_i(\u_riscv_top.core1_timer_irq ),
+    .core_irq_soft_i(\u_riscv_top.core1_soft_irq ),
+    .cpu_rst_n(\cpu_core_rst_n[1] ),
+    .dmem2core_req_ack_i(\u_riscv_top.core1_dmem_req_ack ),
+    .imem2core_req_ack_i(\u_riscv_top.core1_imem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_core1[3] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[2] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[1] ,
+    \u_riscv_top.cfg_ccska_riscv_core1[0] }),
+    .core2dmem_addr_o({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core2dmem_wdata_o({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core2dmem_width_o({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core2imem_addr_o({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core2imem_bl_o({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core_irq_lines_i({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core_mtimer_val_i({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .dmem2core_rdata_i({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .dmem2core_resp_i({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .imem2core_rdata_i({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .imem2core_resp_i({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }));
+ ycr2_iconnect \u_riscv_top.u_connect  (.VGND(vssd1),
+    .VPWR(vccd1),
+    .aes_dmem_cmd(\u_riscv_top.aes_dmem_cmd ),
+    .aes_dmem_req(\u_riscv_top.aes_dmem_req ),
+    .aes_dmem_req_ack(\u_riscv_top.aes_dmem_req_ack ),
+    .cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .core0_dmem_cmd(\u_riscv_top.core0_dmem_cmd ),
+    .core0_dmem_req(\u_riscv_top.core0_dmem_req ),
+    .core0_dmem_req_ack(\u_riscv_top.core0_dmem_req_ack ),
+    .core0_imem_cmd(\u_riscv_top.core0_imem_cmd ),
+    .core0_imem_req(\u_riscv_top.core0_imem_req ),
+    .core0_imem_req_ack(\u_riscv_top.core0_imem_req_ack ),
+    .core0_irq_soft(\u_riscv_top.core0_soft_irq ),
+    .core0_timer_irq(\u_riscv_top.core0_timer_irq ),
+    .core1_dmem_cmd(\u_riscv_top.core1_dmem_cmd ),
+    .core1_dmem_req(\u_riscv_top.core1_dmem_req ),
+    .core1_dmem_req_ack(\u_riscv_top.core1_dmem_req_ack ),
+    .core1_imem_cmd(\u_riscv_top.core1_imem_cmd ),
+    .core1_imem_req(\u_riscv_top.core1_imem_req ),
+    .core1_imem_req_ack(\u_riscv_top.core1_imem_req_ack ),
+    .core1_irq_soft(\u_riscv_top.core1_soft_irq ),
+    .core1_timer_irq(\u_riscv_top.core1_timer_irq ),
+    .core_clk(\u_riscv_top.core_clk_icon_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[1] ),
+    .core_clk_skew(\u_riscv_top.core_clk_icon_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .core_irq_soft_i(\u_riscv_top.soft_irq ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .fpu_dmem_cmd(\u_riscv_top.fpu_dmem_cmd ),
+    .fpu_dmem_req(\u_riscv_top.fpu_dmem_req ),
+    .fpu_dmem_req_ack(\u_riscv_top.fpu_dmem_req_ack ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .rtc_clk(\u_riscv_top.rtc_clk ),
+    .sram0_clk0(\u_riscv_top.sram0_clk0 ),
+    .sram0_clk1(\u_riscv_top.sram0_clk1 ),
+    .sram0_csb0(\u_riscv_top.sram0_csb0 ),
+    .sram0_csb1(\u_riscv_top.sram0_csb1 ),
+    .sram0_web0(\u_riscv_top.sram0_web0 ),
+    .aes_dmem_addr({\u_riscv_top.aes_dmem_addr[6] ,
+    \u_riscv_top.aes_dmem_addr[5] ,
+    \u_riscv_top.aes_dmem_addr[4] ,
+    \u_riscv_top.aes_dmem_addr[3] ,
+    \u_riscv_top.aes_dmem_addr[2] ,
+    \u_riscv_top.aes_dmem_addr[1] ,
+    \u_riscv_top.aes_dmem_addr[0] }),
+    .aes_dmem_rdata({\u_riscv_top.aes_dmem_rdata[31] ,
+    \u_riscv_top.aes_dmem_rdata[30] ,
+    \u_riscv_top.aes_dmem_rdata[29] ,
+    \u_riscv_top.aes_dmem_rdata[28] ,
+    \u_riscv_top.aes_dmem_rdata[27] ,
+    \u_riscv_top.aes_dmem_rdata[26] ,
+    \u_riscv_top.aes_dmem_rdata[25] ,
+    \u_riscv_top.aes_dmem_rdata[24] ,
+    \u_riscv_top.aes_dmem_rdata[23] ,
+    \u_riscv_top.aes_dmem_rdata[22] ,
+    \u_riscv_top.aes_dmem_rdata[21] ,
+    \u_riscv_top.aes_dmem_rdata[20] ,
+    \u_riscv_top.aes_dmem_rdata[19] ,
+    \u_riscv_top.aes_dmem_rdata[18] ,
+    \u_riscv_top.aes_dmem_rdata[17] ,
+    \u_riscv_top.aes_dmem_rdata[16] ,
+    \u_riscv_top.aes_dmem_rdata[15] ,
+    \u_riscv_top.aes_dmem_rdata[14] ,
+    \u_riscv_top.aes_dmem_rdata[13] ,
+    \u_riscv_top.aes_dmem_rdata[12] ,
+    \u_riscv_top.aes_dmem_rdata[11] ,
+    \u_riscv_top.aes_dmem_rdata[10] ,
+    \u_riscv_top.aes_dmem_rdata[9] ,
+    \u_riscv_top.aes_dmem_rdata[8] ,
+    \u_riscv_top.aes_dmem_rdata[7] ,
+    \u_riscv_top.aes_dmem_rdata[6] ,
+    \u_riscv_top.aes_dmem_rdata[5] ,
+    \u_riscv_top.aes_dmem_rdata[4] ,
+    \u_riscv_top.aes_dmem_rdata[3] ,
+    \u_riscv_top.aes_dmem_rdata[2] ,
+    \u_riscv_top.aes_dmem_rdata[1] ,
+    \u_riscv_top.aes_dmem_rdata[0] }),
+    .aes_dmem_resp({\u_riscv_top.aes_dmem_resp[1] ,
+    \u_riscv_top.aes_dmem_resp[0] }),
+    .aes_dmem_wdata({\u_riscv_top.aes_dmem_wdata[31] ,
+    \u_riscv_top.aes_dmem_wdata[30] ,
+    \u_riscv_top.aes_dmem_wdata[29] ,
+    \u_riscv_top.aes_dmem_wdata[28] ,
+    \u_riscv_top.aes_dmem_wdata[27] ,
+    \u_riscv_top.aes_dmem_wdata[26] ,
+    \u_riscv_top.aes_dmem_wdata[25] ,
+    \u_riscv_top.aes_dmem_wdata[24] ,
+    \u_riscv_top.aes_dmem_wdata[23] ,
+    \u_riscv_top.aes_dmem_wdata[22] ,
+    \u_riscv_top.aes_dmem_wdata[21] ,
+    \u_riscv_top.aes_dmem_wdata[20] ,
+    \u_riscv_top.aes_dmem_wdata[19] ,
+    \u_riscv_top.aes_dmem_wdata[18] ,
+    \u_riscv_top.aes_dmem_wdata[17] ,
+    \u_riscv_top.aes_dmem_wdata[16] ,
+    \u_riscv_top.aes_dmem_wdata[15] ,
+    \u_riscv_top.aes_dmem_wdata[14] ,
+    \u_riscv_top.aes_dmem_wdata[13] ,
+    \u_riscv_top.aes_dmem_wdata[12] ,
+    \u_riscv_top.aes_dmem_wdata[11] ,
+    \u_riscv_top.aes_dmem_wdata[10] ,
+    \u_riscv_top.aes_dmem_wdata[9] ,
+    \u_riscv_top.aes_dmem_wdata[8] ,
+    \u_riscv_top.aes_dmem_wdata[7] ,
+    \u_riscv_top.aes_dmem_wdata[6] ,
+    \u_riscv_top.aes_dmem_wdata[5] ,
+    \u_riscv_top.aes_dmem_wdata[4] ,
+    \u_riscv_top.aes_dmem_wdata[3] ,
+    \u_riscv_top.aes_dmem_wdata[2] ,
+    \u_riscv_top.aes_dmem_wdata[1] ,
+    \u_riscv_top.aes_dmem_wdata[0] }),
+    .aes_dmem_width({\u_riscv_top.aes_dmem_width[1] ,
+    \u_riscv_top.aes_dmem_width[0] }),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_icon[3] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[2] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[1] ,
+    \u_riscv_top.cfg_ccska_riscv_icon[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[3] ,
+    \cfg_riscv_ctrl[2] }),
+    .core0_debug({\u_riscv_top.core0_debug[48] ,
+    \u_riscv_top.core0_debug[47] ,
+    \u_riscv_top.core0_debug[46] ,
+    \u_riscv_top.core0_debug[45] ,
+    \u_riscv_top.core0_debug[44] ,
+    \u_riscv_top.core0_debug[43] ,
+    \u_riscv_top.core0_debug[42] ,
+    \u_riscv_top.core0_debug[41] ,
+    \u_riscv_top.core0_debug[40] ,
+    \u_riscv_top.core0_debug[39] ,
+    \u_riscv_top.core0_debug[38] ,
+    \u_riscv_top.core0_debug[37] ,
+    \u_riscv_top.core0_debug[36] ,
+    \u_riscv_top.core0_debug[35] ,
+    \u_riscv_top.core0_debug[34] ,
+    \u_riscv_top.core0_debug[33] ,
+    \u_riscv_top.core0_debug[32] ,
+    \u_riscv_top.core0_debug[31] ,
+    \u_riscv_top.core0_debug[30] ,
+    \u_riscv_top.core0_debug[29] ,
+    \u_riscv_top.core0_debug[28] ,
+    \u_riscv_top.core0_debug[27] ,
+    \u_riscv_top.core0_debug[26] ,
+    \u_riscv_top.core0_debug[25] ,
+    \u_riscv_top.core0_debug[24] ,
+    \u_riscv_top.core0_debug[23] ,
+    \u_riscv_top.core0_debug[22] ,
+    \u_riscv_top.core0_debug[21] ,
+    \u_riscv_top.core0_debug[20] ,
+    \u_riscv_top.core0_debug[19] ,
+    \u_riscv_top.core0_debug[18] ,
+    \u_riscv_top.core0_debug[17] ,
+    \u_riscv_top.core0_debug[16] ,
+    \u_riscv_top.core0_debug[15] ,
+    \u_riscv_top.core0_debug[14] ,
+    \u_riscv_top.core0_debug[13] ,
+    \u_riscv_top.core0_debug[12] ,
+    \u_riscv_top.core0_debug[11] ,
+    \u_riscv_top.core0_debug[10] ,
+    \u_riscv_top.core0_debug[9] ,
+    \u_riscv_top.core0_debug[8] ,
+    \u_riscv_top.core0_debug[7] ,
+    \u_riscv_top.core0_debug[6] ,
+    \u_riscv_top.core0_debug[5] ,
+    \u_riscv_top.core0_debug[4] ,
+    \u_riscv_top.core0_debug[3] ,
+    \u_riscv_top.core0_debug[2] ,
+    \u_riscv_top.core0_debug[1] ,
+    \u_riscv_top.core0_debug[0] }),
+    .core0_dmem_addr({\u_riscv_top.core0_dmem_addr[31] ,
+    \u_riscv_top.core0_dmem_addr[30] ,
+    \u_riscv_top.core0_dmem_addr[29] ,
+    \u_riscv_top.core0_dmem_addr[28] ,
+    \u_riscv_top.core0_dmem_addr[27] ,
+    \u_riscv_top.core0_dmem_addr[26] ,
+    \u_riscv_top.core0_dmem_addr[25] ,
+    \u_riscv_top.core0_dmem_addr[24] ,
+    \u_riscv_top.core0_dmem_addr[23] ,
+    \u_riscv_top.core0_dmem_addr[22] ,
+    \u_riscv_top.core0_dmem_addr[21] ,
+    \u_riscv_top.core0_dmem_addr[20] ,
+    \u_riscv_top.core0_dmem_addr[19] ,
+    \u_riscv_top.core0_dmem_addr[18] ,
+    \u_riscv_top.core0_dmem_addr[17] ,
+    \u_riscv_top.core0_dmem_addr[16] ,
+    \u_riscv_top.core0_dmem_addr[15] ,
+    \u_riscv_top.core0_dmem_addr[14] ,
+    \u_riscv_top.core0_dmem_addr[13] ,
+    \u_riscv_top.core0_dmem_addr[12] ,
+    \u_riscv_top.core0_dmem_addr[11] ,
+    \u_riscv_top.core0_dmem_addr[10] ,
+    \u_riscv_top.core0_dmem_addr[9] ,
+    \u_riscv_top.core0_dmem_addr[8] ,
+    \u_riscv_top.core0_dmem_addr[7] ,
+    \u_riscv_top.core0_dmem_addr[6] ,
+    \u_riscv_top.core0_dmem_addr[5] ,
+    \u_riscv_top.core0_dmem_addr[4] ,
+    \u_riscv_top.core0_dmem_addr[3] ,
+    \u_riscv_top.core0_dmem_addr[2] ,
+    \u_riscv_top.core0_dmem_addr[1] ,
+    \u_riscv_top.core0_dmem_addr[0] }),
+    .core0_dmem_rdata({\u_riscv_top.core0_dmem_rdata[31] ,
+    \u_riscv_top.core0_dmem_rdata[30] ,
+    \u_riscv_top.core0_dmem_rdata[29] ,
+    \u_riscv_top.core0_dmem_rdata[28] ,
+    \u_riscv_top.core0_dmem_rdata[27] ,
+    \u_riscv_top.core0_dmem_rdata[26] ,
+    \u_riscv_top.core0_dmem_rdata[25] ,
+    \u_riscv_top.core0_dmem_rdata[24] ,
+    \u_riscv_top.core0_dmem_rdata[23] ,
+    \u_riscv_top.core0_dmem_rdata[22] ,
+    \u_riscv_top.core0_dmem_rdata[21] ,
+    \u_riscv_top.core0_dmem_rdata[20] ,
+    \u_riscv_top.core0_dmem_rdata[19] ,
+    \u_riscv_top.core0_dmem_rdata[18] ,
+    \u_riscv_top.core0_dmem_rdata[17] ,
+    \u_riscv_top.core0_dmem_rdata[16] ,
+    \u_riscv_top.core0_dmem_rdata[15] ,
+    \u_riscv_top.core0_dmem_rdata[14] ,
+    \u_riscv_top.core0_dmem_rdata[13] ,
+    \u_riscv_top.core0_dmem_rdata[12] ,
+    \u_riscv_top.core0_dmem_rdata[11] ,
+    \u_riscv_top.core0_dmem_rdata[10] ,
+    \u_riscv_top.core0_dmem_rdata[9] ,
+    \u_riscv_top.core0_dmem_rdata[8] ,
+    \u_riscv_top.core0_dmem_rdata[7] ,
+    \u_riscv_top.core0_dmem_rdata[6] ,
+    \u_riscv_top.core0_dmem_rdata[5] ,
+    \u_riscv_top.core0_dmem_rdata[4] ,
+    \u_riscv_top.core0_dmem_rdata[3] ,
+    \u_riscv_top.core0_dmem_rdata[2] ,
+    \u_riscv_top.core0_dmem_rdata[1] ,
+    \u_riscv_top.core0_dmem_rdata[0] }),
+    .core0_dmem_resp({\u_riscv_top.core0_dmem_resp[1] ,
+    \u_riscv_top.core0_dmem_resp[0] }),
+    .core0_dmem_wdata({\u_riscv_top.core0_dmem_wdata[31] ,
+    \u_riscv_top.core0_dmem_wdata[30] ,
+    \u_riscv_top.core0_dmem_wdata[29] ,
+    \u_riscv_top.core0_dmem_wdata[28] ,
+    \u_riscv_top.core0_dmem_wdata[27] ,
+    \u_riscv_top.core0_dmem_wdata[26] ,
+    \u_riscv_top.core0_dmem_wdata[25] ,
+    \u_riscv_top.core0_dmem_wdata[24] ,
+    \u_riscv_top.core0_dmem_wdata[23] ,
+    \u_riscv_top.core0_dmem_wdata[22] ,
+    \u_riscv_top.core0_dmem_wdata[21] ,
+    \u_riscv_top.core0_dmem_wdata[20] ,
+    \u_riscv_top.core0_dmem_wdata[19] ,
+    \u_riscv_top.core0_dmem_wdata[18] ,
+    \u_riscv_top.core0_dmem_wdata[17] ,
+    \u_riscv_top.core0_dmem_wdata[16] ,
+    \u_riscv_top.core0_dmem_wdata[15] ,
+    \u_riscv_top.core0_dmem_wdata[14] ,
+    \u_riscv_top.core0_dmem_wdata[13] ,
+    \u_riscv_top.core0_dmem_wdata[12] ,
+    \u_riscv_top.core0_dmem_wdata[11] ,
+    \u_riscv_top.core0_dmem_wdata[10] ,
+    \u_riscv_top.core0_dmem_wdata[9] ,
+    \u_riscv_top.core0_dmem_wdata[8] ,
+    \u_riscv_top.core0_dmem_wdata[7] ,
+    \u_riscv_top.core0_dmem_wdata[6] ,
+    \u_riscv_top.core0_dmem_wdata[5] ,
+    \u_riscv_top.core0_dmem_wdata[4] ,
+    \u_riscv_top.core0_dmem_wdata[3] ,
+    \u_riscv_top.core0_dmem_wdata[2] ,
+    \u_riscv_top.core0_dmem_wdata[1] ,
+    \u_riscv_top.core0_dmem_wdata[0] }),
+    .core0_dmem_width({\u_riscv_top.core0_dmem_width[1] ,
+    \u_riscv_top.core0_dmem_width[0] }),
+    .core0_imem_addr({\u_riscv_top.core0_imem_addr[31] ,
+    \u_riscv_top.core0_imem_addr[30] ,
+    \u_riscv_top.core0_imem_addr[29] ,
+    \u_riscv_top.core0_imem_addr[28] ,
+    \u_riscv_top.core0_imem_addr[27] ,
+    \u_riscv_top.core0_imem_addr[26] ,
+    \u_riscv_top.core0_imem_addr[25] ,
+    \u_riscv_top.core0_imem_addr[24] ,
+    \u_riscv_top.core0_imem_addr[23] ,
+    \u_riscv_top.core0_imem_addr[22] ,
+    \u_riscv_top.core0_imem_addr[21] ,
+    \u_riscv_top.core0_imem_addr[20] ,
+    \u_riscv_top.core0_imem_addr[19] ,
+    \u_riscv_top.core0_imem_addr[18] ,
+    \u_riscv_top.core0_imem_addr[17] ,
+    \u_riscv_top.core0_imem_addr[16] ,
+    \u_riscv_top.core0_imem_addr[15] ,
+    \u_riscv_top.core0_imem_addr[14] ,
+    \u_riscv_top.core0_imem_addr[13] ,
+    \u_riscv_top.core0_imem_addr[12] ,
+    \u_riscv_top.core0_imem_addr[11] ,
+    \u_riscv_top.core0_imem_addr[10] ,
+    \u_riscv_top.core0_imem_addr[9] ,
+    \u_riscv_top.core0_imem_addr[8] ,
+    \u_riscv_top.core0_imem_addr[7] ,
+    \u_riscv_top.core0_imem_addr[6] ,
+    \u_riscv_top.core0_imem_addr[5] ,
+    \u_riscv_top.core0_imem_addr[4] ,
+    \u_riscv_top.core0_imem_addr[3] ,
+    \u_riscv_top.core0_imem_addr[2] ,
+    \u_riscv_top.core0_imem_addr[1] ,
+    \u_riscv_top.core0_imem_addr[0] }),
+    .core0_imem_bl({\u_riscv_top.core0_imem_bl[2] ,
+    \u_riscv_top.core0_imem_bl[1] ,
+    \u_riscv_top.core0_imem_bl[0] }),
+    .core0_imem_rdata({\u_riscv_top.core0_imem_rdata[31] ,
+    \u_riscv_top.core0_imem_rdata[30] ,
+    \u_riscv_top.core0_imem_rdata[29] ,
+    \u_riscv_top.core0_imem_rdata[28] ,
+    \u_riscv_top.core0_imem_rdata[27] ,
+    \u_riscv_top.core0_imem_rdata[26] ,
+    \u_riscv_top.core0_imem_rdata[25] ,
+    \u_riscv_top.core0_imem_rdata[24] ,
+    \u_riscv_top.core0_imem_rdata[23] ,
+    \u_riscv_top.core0_imem_rdata[22] ,
+    \u_riscv_top.core0_imem_rdata[21] ,
+    \u_riscv_top.core0_imem_rdata[20] ,
+    \u_riscv_top.core0_imem_rdata[19] ,
+    \u_riscv_top.core0_imem_rdata[18] ,
+    \u_riscv_top.core0_imem_rdata[17] ,
+    \u_riscv_top.core0_imem_rdata[16] ,
+    \u_riscv_top.core0_imem_rdata[15] ,
+    \u_riscv_top.core0_imem_rdata[14] ,
+    \u_riscv_top.core0_imem_rdata[13] ,
+    \u_riscv_top.core0_imem_rdata[12] ,
+    \u_riscv_top.core0_imem_rdata[11] ,
+    \u_riscv_top.core0_imem_rdata[10] ,
+    \u_riscv_top.core0_imem_rdata[9] ,
+    \u_riscv_top.core0_imem_rdata[8] ,
+    \u_riscv_top.core0_imem_rdata[7] ,
+    \u_riscv_top.core0_imem_rdata[6] ,
+    \u_riscv_top.core0_imem_rdata[5] ,
+    \u_riscv_top.core0_imem_rdata[4] ,
+    \u_riscv_top.core0_imem_rdata[3] ,
+    \u_riscv_top.core0_imem_rdata[2] ,
+    \u_riscv_top.core0_imem_rdata[1] ,
+    \u_riscv_top.core0_imem_rdata[0] }),
+    .core0_imem_resp({\u_riscv_top.core0_imem_resp[1] ,
+    \u_riscv_top.core0_imem_resp[0] }),
+    .core0_irq_lines({\u_riscv_top.core0_irq_lines[31] ,
+    \u_riscv_top.core0_irq_lines[30] ,
+    \u_riscv_top.core0_irq_lines[29] ,
+    \u_riscv_top.core0_irq_lines[28] ,
+    \u_riscv_top.core0_irq_lines[27] ,
+    \u_riscv_top.core0_irq_lines[26] ,
+    \u_riscv_top.core0_irq_lines[25] ,
+    \u_riscv_top.core0_irq_lines[24] ,
+    \u_riscv_top.core0_irq_lines[23] ,
+    \u_riscv_top.core0_irq_lines[22] ,
+    \u_riscv_top.core0_irq_lines[21] ,
+    \u_riscv_top.core0_irq_lines[20] ,
+    \u_riscv_top.core0_irq_lines[19] ,
+    \u_riscv_top.core0_irq_lines[18] ,
+    \u_riscv_top.core0_irq_lines[17] ,
+    \u_riscv_top.core0_irq_lines[16] ,
+    \u_riscv_top.core0_irq_lines[15] ,
+    \u_riscv_top.core0_irq_lines[14] ,
+    \u_riscv_top.core0_irq_lines[13] ,
+    \u_riscv_top.core0_irq_lines[12] ,
+    \u_riscv_top.core0_irq_lines[11] ,
+    \u_riscv_top.core0_irq_lines[10] ,
+    \u_riscv_top.core0_irq_lines[9] ,
+    \u_riscv_top.core0_irq_lines[8] ,
+    \u_riscv_top.core0_irq_lines[7] ,
+    \u_riscv_top.core0_irq_lines[6] ,
+    \u_riscv_top.core0_irq_lines[5] ,
+    \u_riscv_top.core0_irq_lines[4] ,
+    \u_riscv_top.core0_irq_lines[3] ,
+    \u_riscv_top.core0_irq_lines[2] ,
+    \u_riscv_top.core0_irq_lines[1] ,
+    \u_riscv_top.core0_irq_lines[0] }),
+    .core0_timer_val({\u_riscv_top.core0_timer_val[63] ,
+    \u_riscv_top.core0_timer_val[62] ,
+    \u_riscv_top.core0_timer_val[61] ,
+    \u_riscv_top.core0_timer_val[60] ,
+    \u_riscv_top.core0_timer_val[59] ,
+    \u_riscv_top.core0_timer_val[58] ,
+    \u_riscv_top.core0_timer_val[57] ,
+    \u_riscv_top.core0_timer_val[56] ,
+    \u_riscv_top.core0_timer_val[55] ,
+    \u_riscv_top.core0_timer_val[54] ,
+    \u_riscv_top.core0_timer_val[53] ,
+    \u_riscv_top.core0_timer_val[52] ,
+    \u_riscv_top.core0_timer_val[51] ,
+    \u_riscv_top.core0_timer_val[50] ,
+    \u_riscv_top.core0_timer_val[49] ,
+    \u_riscv_top.core0_timer_val[48] ,
+    \u_riscv_top.core0_timer_val[47] ,
+    \u_riscv_top.core0_timer_val[46] ,
+    \u_riscv_top.core0_timer_val[45] ,
+    \u_riscv_top.core0_timer_val[44] ,
+    \u_riscv_top.core0_timer_val[43] ,
+    \u_riscv_top.core0_timer_val[42] ,
+    \u_riscv_top.core0_timer_val[41] ,
+    \u_riscv_top.core0_timer_val[40] ,
+    \u_riscv_top.core0_timer_val[39] ,
+    \u_riscv_top.core0_timer_val[38] ,
+    \u_riscv_top.core0_timer_val[37] ,
+    \u_riscv_top.core0_timer_val[36] ,
+    \u_riscv_top.core0_timer_val[35] ,
+    \u_riscv_top.core0_timer_val[34] ,
+    \u_riscv_top.core0_timer_val[33] ,
+    \u_riscv_top.core0_timer_val[32] ,
+    \u_riscv_top.core0_timer_val[31] ,
+    \u_riscv_top.core0_timer_val[30] ,
+    \u_riscv_top.core0_timer_val[29] ,
+    \u_riscv_top.core0_timer_val[28] ,
+    \u_riscv_top.core0_timer_val[27] ,
+    \u_riscv_top.core0_timer_val[26] ,
+    \u_riscv_top.core0_timer_val[25] ,
+    \u_riscv_top.core0_timer_val[24] ,
+    \u_riscv_top.core0_timer_val[23] ,
+    \u_riscv_top.core0_timer_val[22] ,
+    \u_riscv_top.core0_timer_val[21] ,
+    \u_riscv_top.core0_timer_val[20] ,
+    \u_riscv_top.core0_timer_val[19] ,
+    \u_riscv_top.core0_timer_val[18] ,
+    \u_riscv_top.core0_timer_val[17] ,
+    \u_riscv_top.core0_timer_val[16] ,
+    \u_riscv_top.core0_timer_val[15] ,
+    \u_riscv_top.core0_timer_val[14] ,
+    \u_riscv_top.core0_timer_val[13] ,
+    \u_riscv_top.core0_timer_val[12] ,
+    \u_riscv_top.core0_timer_val[11] ,
+    \u_riscv_top.core0_timer_val[10] ,
+    \u_riscv_top.core0_timer_val[9] ,
+    \u_riscv_top.core0_timer_val[8] ,
+    \u_riscv_top.core0_timer_val[7] ,
+    \u_riscv_top.core0_timer_val[6] ,
+    \u_riscv_top.core0_timer_val[5] ,
+    \u_riscv_top.core0_timer_val[4] ,
+    \u_riscv_top.core0_timer_val[3] ,
+    \u_riscv_top.core0_timer_val[2] ,
+    \u_riscv_top.core0_timer_val[1] ,
+    \u_riscv_top.core0_timer_val[0] }),
+    .core0_uid({\u_riscv_top.core0_uid[1] ,
+    \u_riscv_top.core0_uid[0] }),
+    .core1_debug({\u_riscv_top.core1_debug[48] ,
+    \u_riscv_top.core1_debug[47] ,
+    \u_riscv_top.core1_debug[46] ,
+    \u_riscv_top.core1_debug[45] ,
+    \u_riscv_top.core1_debug[44] ,
+    \u_riscv_top.core1_debug[43] ,
+    \u_riscv_top.core1_debug[42] ,
+    \u_riscv_top.core1_debug[41] ,
+    \u_riscv_top.core1_debug[40] ,
+    \u_riscv_top.core1_debug[39] ,
+    \u_riscv_top.core1_debug[38] ,
+    \u_riscv_top.core1_debug[37] ,
+    \u_riscv_top.core1_debug[36] ,
+    \u_riscv_top.core1_debug[35] ,
+    \u_riscv_top.core1_debug[34] ,
+    \u_riscv_top.core1_debug[33] ,
+    \u_riscv_top.core1_debug[32] ,
+    \u_riscv_top.core1_debug[31] ,
+    \u_riscv_top.core1_debug[30] ,
+    \u_riscv_top.core1_debug[29] ,
+    \u_riscv_top.core1_debug[28] ,
+    \u_riscv_top.core1_debug[27] ,
+    \u_riscv_top.core1_debug[26] ,
+    \u_riscv_top.core1_debug[25] ,
+    \u_riscv_top.core1_debug[24] ,
+    \u_riscv_top.core1_debug[23] ,
+    \u_riscv_top.core1_debug[22] ,
+    \u_riscv_top.core1_debug[21] ,
+    \u_riscv_top.core1_debug[20] ,
+    \u_riscv_top.core1_debug[19] ,
+    \u_riscv_top.core1_debug[18] ,
+    \u_riscv_top.core1_debug[17] ,
+    \u_riscv_top.core1_debug[16] ,
+    \u_riscv_top.core1_debug[15] ,
+    \u_riscv_top.core1_debug[14] ,
+    \u_riscv_top.core1_debug[13] ,
+    \u_riscv_top.core1_debug[12] ,
+    \u_riscv_top.core1_debug[11] ,
+    \u_riscv_top.core1_debug[10] ,
+    \u_riscv_top.core1_debug[9] ,
+    \u_riscv_top.core1_debug[8] ,
+    \u_riscv_top.core1_debug[7] ,
+    \u_riscv_top.core1_debug[6] ,
+    \u_riscv_top.core1_debug[5] ,
+    \u_riscv_top.core1_debug[4] ,
+    \u_riscv_top.core1_debug[3] ,
+    \u_riscv_top.core1_debug[2] ,
+    \u_riscv_top.core1_debug[1] ,
+    \u_riscv_top.core1_debug[0] }),
+    .core1_dmem_addr({\u_riscv_top.core1_dmem_addr[31] ,
+    \u_riscv_top.core1_dmem_addr[30] ,
+    \u_riscv_top.core1_dmem_addr[29] ,
+    \u_riscv_top.core1_dmem_addr[28] ,
+    \u_riscv_top.core1_dmem_addr[27] ,
+    \u_riscv_top.core1_dmem_addr[26] ,
+    \u_riscv_top.core1_dmem_addr[25] ,
+    \u_riscv_top.core1_dmem_addr[24] ,
+    \u_riscv_top.core1_dmem_addr[23] ,
+    \u_riscv_top.core1_dmem_addr[22] ,
+    \u_riscv_top.core1_dmem_addr[21] ,
+    \u_riscv_top.core1_dmem_addr[20] ,
+    \u_riscv_top.core1_dmem_addr[19] ,
+    \u_riscv_top.core1_dmem_addr[18] ,
+    \u_riscv_top.core1_dmem_addr[17] ,
+    \u_riscv_top.core1_dmem_addr[16] ,
+    \u_riscv_top.core1_dmem_addr[15] ,
+    \u_riscv_top.core1_dmem_addr[14] ,
+    \u_riscv_top.core1_dmem_addr[13] ,
+    \u_riscv_top.core1_dmem_addr[12] ,
+    \u_riscv_top.core1_dmem_addr[11] ,
+    \u_riscv_top.core1_dmem_addr[10] ,
+    \u_riscv_top.core1_dmem_addr[9] ,
+    \u_riscv_top.core1_dmem_addr[8] ,
+    \u_riscv_top.core1_dmem_addr[7] ,
+    \u_riscv_top.core1_dmem_addr[6] ,
+    \u_riscv_top.core1_dmem_addr[5] ,
+    \u_riscv_top.core1_dmem_addr[4] ,
+    \u_riscv_top.core1_dmem_addr[3] ,
+    \u_riscv_top.core1_dmem_addr[2] ,
+    \u_riscv_top.core1_dmem_addr[1] ,
+    \u_riscv_top.core1_dmem_addr[0] }),
+    .core1_dmem_rdata({\u_riscv_top.core1_dmem_rdata[31] ,
+    \u_riscv_top.core1_dmem_rdata[30] ,
+    \u_riscv_top.core1_dmem_rdata[29] ,
+    \u_riscv_top.core1_dmem_rdata[28] ,
+    \u_riscv_top.core1_dmem_rdata[27] ,
+    \u_riscv_top.core1_dmem_rdata[26] ,
+    \u_riscv_top.core1_dmem_rdata[25] ,
+    \u_riscv_top.core1_dmem_rdata[24] ,
+    \u_riscv_top.core1_dmem_rdata[23] ,
+    \u_riscv_top.core1_dmem_rdata[22] ,
+    \u_riscv_top.core1_dmem_rdata[21] ,
+    \u_riscv_top.core1_dmem_rdata[20] ,
+    \u_riscv_top.core1_dmem_rdata[19] ,
+    \u_riscv_top.core1_dmem_rdata[18] ,
+    \u_riscv_top.core1_dmem_rdata[17] ,
+    \u_riscv_top.core1_dmem_rdata[16] ,
+    \u_riscv_top.core1_dmem_rdata[15] ,
+    \u_riscv_top.core1_dmem_rdata[14] ,
+    \u_riscv_top.core1_dmem_rdata[13] ,
+    \u_riscv_top.core1_dmem_rdata[12] ,
+    \u_riscv_top.core1_dmem_rdata[11] ,
+    \u_riscv_top.core1_dmem_rdata[10] ,
+    \u_riscv_top.core1_dmem_rdata[9] ,
+    \u_riscv_top.core1_dmem_rdata[8] ,
+    \u_riscv_top.core1_dmem_rdata[7] ,
+    \u_riscv_top.core1_dmem_rdata[6] ,
+    \u_riscv_top.core1_dmem_rdata[5] ,
+    \u_riscv_top.core1_dmem_rdata[4] ,
+    \u_riscv_top.core1_dmem_rdata[3] ,
+    \u_riscv_top.core1_dmem_rdata[2] ,
+    \u_riscv_top.core1_dmem_rdata[1] ,
+    \u_riscv_top.core1_dmem_rdata[0] }),
+    .core1_dmem_resp({\u_riscv_top.core1_dmem_resp[1] ,
+    \u_riscv_top.core1_dmem_resp[0] }),
+    .core1_dmem_wdata({\u_riscv_top.core1_dmem_wdata[31] ,
+    \u_riscv_top.core1_dmem_wdata[30] ,
+    \u_riscv_top.core1_dmem_wdata[29] ,
+    \u_riscv_top.core1_dmem_wdata[28] ,
+    \u_riscv_top.core1_dmem_wdata[27] ,
+    \u_riscv_top.core1_dmem_wdata[26] ,
+    \u_riscv_top.core1_dmem_wdata[25] ,
+    \u_riscv_top.core1_dmem_wdata[24] ,
+    \u_riscv_top.core1_dmem_wdata[23] ,
+    \u_riscv_top.core1_dmem_wdata[22] ,
+    \u_riscv_top.core1_dmem_wdata[21] ,
+    \u_riscv_top.core1_dmem_wdata[20] ,
+    \u_riscv_top.core1_dmem_wdata[19] ,
+    \u_riscv_top.core1_dmem_wdata[18] ,
+    \u_riscv_top.core1_dmem_wdata[17] ,
+    \u_riscv_top.core1_dmem_wdata[16] ,
+    \u_riscv_top.core1_dmem_wdata[15] ,
+    \u_riscv_top.core1_dmem_wdata[14] ,
+    \u_riscv_top.core1_dmem_wdata[13] ,
+    \u_riscv_top.core1_dmem_wdata[12] ,
+    \u_riscv_top.core1_dmem_wdata[11] ,
+    \u_riscv_top.core1_dmem_wdata[10] ,
+    \u_riscv_top.core1_dmem_wdata[9] ,
+    \u_riscv_top.core1_dmem_wdata[8] ,
+    \u_riscv_top.core1_dmem_wdata[7] ,
+    \u_riscv_top.core1_dmem_wdata[6] ,
+    \u_riscv_top.core1_dmem_wdata[5] ,
+    \u_riscv_top.core1_dmem_wdata[4] ,
+    \u_riscv_top.core1_dmem_wdata[3] ,
+    \u_riscv_top.core1_dmem_wdata[2] ,
+    \u_riscv_top.core1_dmem_wdata[1] ,
+    \u_riscv_top.core1_dmem_wdata[0] }),
+    .core1_dmem_width({\u_riscv_top.core1_dmem_width[1] ,
+    \u_riscv_top.core1_dmem_width[0] }),
+    .core1_imem_addr({\u_riscv_top.core1_imem_addr[31] ,
+    \u_riscv_top.core1_imem_addr[30] ,
+    \u_riscv_top.core1_imem_addr[29] ,
+    \u_riscv_top.core1_imem_addr[28] ,
+    \u_riscv_top.core1_imem_addr[27] ,
+    \u_riscv_top.core1_imem_addr[26] ,
+    \u_riscv_top.core1_imem_addr[25] ,
+    \u_riscv_top.core1_imem_addr[24] ,
+    \u_riscv_top.core1_imem_addr[23] ,
+    \u_riscv_top.core1_imem_addr[22] ,
+    \u_riscv_top.core1_imem_addr[21] ,
+    \u_riscv_top.core1_imem_addr[20] ,
+    \u_riscv_top.core1_imem_addr[19] ,
+    \u_riscv_top.core1_imem_addr[18] ,
+    \u_riscv_top.core1_imem_addr[17] ,
+    \u_riscv_top.core1_imem_addr[16] ,
+    \u_riscv_top.core1_imem_addr[15] ,
+    \u_riscv_top.core1_imem_addr[14] ,
+    \u_riscv_top.core1_imem_addr[13] ,
+    \u_riscv_top.core1_imem_addr[12] ,
+    \u_riscv_top.core1_imem_addr[11] ,
+    \u_riscv_top.core1_imem_addr[10] ,
+    \u_riscv_top.core1_imem_addr[9] ,
+    \u_riscv_top.core1_imem_addr[8] ,
+    \u_riscv_top.core1_imem_addr[7] ,
+    \u_riscv_top.core1_imem_addr[6] ,
+    \u_riscv_top.core1_imem_addr[5] ,
+    \u_riscv_top.core1_imem_addr[4] ,
+    \u_riscv_top.core1_imem_addr[3] ,
+    \u_riscv_top.core1_imem_addr[2] ,
+    \u_riscv_top.core1_imem_addr[1] ,
+    \u_riscv_top.core1_imem_addr[0] }),
+    .core1_imem_bl({\u_riscv_top.core1_imem_bl[2] ,
+    \u_riscv_top.core1_imem_bl[1] ,
+    \u_riscv_top.core1_imem_bl[0] }),
+    .core1_imem_rdata({\u_riscv_top.core1_imem_rdata[31] ,
+    \u_riscv_top.core1_imem_rdata[30] ,
+    \u_riscv_top.core1_imem_rdata[29] ,
+    \u_riscv_top.core1_imem_rdata[28] ,
+    \u_riscv_top.core1_imem_rdata[27] ,
+    \u_riscv_top.core1_imem_rdata[26] ,
+    \u_riscv_top.core1_imem_rdata[25] ,
+    \u_riscv_top.core1_imem_rdata[24] ,
+    \u_riscv_top.core1_imem_rdata[23] ,
+    \u_riscv_top.core1_imem_rdata[22] ,
+    \u_riscv_top.core1_imem_rdata[21] ,
+    \u_riscv_top.core1_imem_rdata[20] ,
+    \u_riscv_top.core1_imem_rdata[19] ,
+    \u_riscv_top.core1_imem_rdata[18] ,
+    \u_riscv_top.core1_imem_rdata[17] ,
+    \u_riscv_top.core1_imem_rdata[16] ,
+    \u_riscv_top.core1_imem_rdata[15] ,
+    \u_riscv_top.core1_imem_rdata[14] ,
+    \u_riscv_top.core1_imem_rdata[13] ,
+    \u_riscv_top.core1_imem_rdata[12] ,
+    \u_riscv_top.core1_imem_rdata[11] ,
+    \u_riscv_top.core1_imem_rdata[10] ,
+    \u_riscv_top.core1_imem_rdata[9] ,
+    \u_riscv_top.core1_imem_rdata[8] ,
+    \u_riscv_top.core1_imem_rdata[7] ,
+    \u_riscv_top.core1_imem_rdata[6] ,
+    \u_riscv_top.core1_imem_rdata[5] ,
+    \u_riscv_top.core1_imem_rdata[4] ,
+    \u_riscv_top.core1_imem_rdata[3] ,
+    \u_riscv_top.core1_imem_rdata[2] ,
+    \u_riscv_top.core1_imem_rdata[1] ,
+    \u_riscv_top.core1_imem_rdata[0] }),
+    .core1_imem_resp({\u_riscv_top.core1_imem_resp[1] ,
+    \u_riscv_top.core1_imem_resp[0] }),
+    .core1_irq_lines({\u_riscv_top.core1_irq_lines[31] ,
+    \u_riscv_top.core1_irq_lines[30] ,
+    \u_riscv_top.core1_irq_lines[29] ,
+    \u_riscv_top.core1_irq_lines[28] ,
+    \u_riscv_top.core1_irq_lines[27] ,
+    \u_riscv_top.core1_irq_lines[26] ,
+    \u_riscv_top.core1_irq_lines[25] ,
+    \u_riscv_top.core1_irq_lines[24] ,
+    \u_riscv_top.core1_irq_lines[23] ,
+    \u_riscv_top.core1_irq_lines[22] ,
+    \u_riscv_top.core1_irq_lines[21] ,
+    \u_riscv_top.core1_irq_lines[20] ,
+    \u_riscv_top.core1_irq_lines[19] ,
+    \u_riscv_top.core1_irq_lines[18] ,
+    \u_riscv_top.core1_irq_lines[17] ,
+    \u_riscv_top.core1_irq_lines[16] ,
+    \u_riscv_top.core1_irq_lines[15] ,
+    \u_riscv_top.core1_irq_lines[14] ,
+    \u_riscv_top.core1_irq_lines[13] ,
+    \u_riscv_top.core1_irq_lines[12] ,
+    \u_riscv_top.core1_irq_lines[11] ,
+    \u_riscv_top.core1_irq_lines[10] ,
+    \u_riscv_top.core1_irq_lines[9] ,
+    \u_riscv_top.core1_irq_lines[8] ,
+    \u_riscv_top.core1_irq_lines[7] ,
+    \u_riscv_top.core1_irq_lines[6] ,
+    \u_riscv_top.core1_irq_lines[5] ,
+    \u_riscv_top.core1_irq_lines[4] ,
+    \u_riscv_top.core1_irq_lines[3] ,
+    \u_riscv_top.core1_irq_lines[2] ,
+    \u_riscv_top.core1_irq_lines[1] ,
+    \u_riscv_top.core1_irq_lines[0] }),
+    .core1_timer_val({\u_riscv_top.core1_timer_val[63] ,
+    \u_riscv_top.core1_timer_val[62] ,
+    \u_riscv_top.core1_timer_val[61] ,
+    \u_riscv_top.core1_timer_val[60] ,
+    \u_riscv_top.core1_timer_val[59] ,
+    \u_riscv_top.core1_timer_val[58] ,
+    \u_riscv_top.core1_timer_val[57] ,
+    \u_riscv_top.core1_timer_val[56] ,
+    \u_riscv_top.core1_timer_val[55] ,
+    \u_riscv_top.core1_timer_val[54] ,
+    \u_riscv_top.core1_timer_val[53] ,
+    \u_riscv_top.core1_timer_val[52] ,
+    \u_riscv_top.core1_timer_val[51] ,
+    \u_riscv_top.core1_timer_val[50] ,
+    \u_riscv_top.core1_timer_val[49] ,
+    \u_riscv_top.core1_timer_val[48] ,
+    \u_riscv_top.core1_timer_val[47] ,
+    \u_riscv_top.core1_timer_val[46] ,
+    \u_riscv_top.core1_timer_val[45] ,
+    \u_riscv_top.core1_timer_val[44] ,
+    \u_riscv_top.core1_timer_val[43] ,
+    \u_riscv_top.core1_timer_val[42] ,
+    \u_riscv_top.core1_timer_val[41] ,
+    \u_riscv_top.core1_timer_val[40] ,
+    \u_riscv_top.core1_timer_val[39] ,
+    \u_riscv_top.core1_timer_val[38] ,
+    \u_riscv_top.core1_timer_val[37] ,
+    \u_riscv_top.core1_timer_val[36] ,
+    \u_riscv_top.core1_timer_val[35] ,
+    \u_riscv_top.core1_timer_val[34] ,
+    \u_riscv_top.core1_timer_val[33] ,
+    \u_riscv_top.core1_timer_val[32] ,
+    \u_riscv_top.core1_timer_val[31] ,
+    \u_riscv_top.core1_timer_val[30] ,
+    \u_riscv_top.core1_timer_val[29] ,
+    \u_riscv_top.core1_timer_val[28] ,
+    \u_riscv_top.core1_timer_val[27] ,
+    \u_riscv_top.core1_timer_val[26] ,
+    \u_riscv_top.core1_timer_val[25] ,
+    \u_riscv_top.core1_timer_val[24] ,
+    \u_riscv_top.core1_timer_val[23] ,
+    \u_riscv_top.core1_timer_val[22] ,
+    \u_riscv_top.core1_timer_val[21] ,
+    \u_riscv_top.core1_timer_val[20] ,
+    \u_riscv_top.core1_timer_val[19] ,
+    \u_riscv_top.core1_timer_val[18] ,
+    \u_riscv_top.core1_timer_val[17] ,
+    \u_riscv_top.core1_timer_val[16] ,
+    \u_riscv_top.core1_timer_val[15] ,
+    \u_riscv_top.core1_timer_val[14] ,
+    \u_riscv_top.core1_timer_val[13] ,
+    \u_riscv_top.core1_timer_val[12] ,
+    \u_riscv_top.core1_timer_val[11] ,
+    \u_riscv_top.core1_timer_val[10] ,
+    \u_riscv_top.core1_timer_val[9] ,
+    \u_riscv_top.core1_timer_val[8] ,
+    \u_riscv_top.core1_timer_val[7] ,
+    \u_riscv_top.core1_timer_val[6] ,
+    \u_riscv_top.core1_timer_val[5] ,
+    \u_riscv_top.core1_timer_val[4] ,
+    \u_riscv_top.core1_timer_val[3] ,
+    \u_riscv_top.core1_timer_val[2] ,
+    \u_riscv_top.core1_timer_val[1] ,
+    \u_riscv_top.core1_timer_val[0] }),
+    .core1_uid({\u_riscv_top.core1_uid[1] ,
+    \u_riscv_top.core1_uid[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_debug_sel({\cfg_riscv_ctrl[9] ,
+    \cfg_riscv_ctrl[8] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .core_irq_lines_i({\u_riscv_top.irq_lines[31] ,
+    \u_riscv_top.irq_lines[30] ,
+    \u_riscv_top.irq_lines[29] ,
+    \u_riscv_top.irq_lines[28] ,
+    \u_riscv_top.irq_lines[27] ,
+    \u_riscv_top.irq_lines[26] ,
+    \u_riscv_top.irq_lines[25] ,
+    \u_riscv_top.irq_lines[24] ,
+    \u_riscv_top.irq_lines[23] ,
+    \u_riscv_top.irq_lines[22] ,
+    \u_riscv_top.irq_lines[21] ,
+    \u_riscv_top.irq_lines[20] ,
+    \u_riscv_top.irq_lines[19] ,
+    \u_riscv_top.irq_lines[18] ,
+    \u_riscv_top.irq_lines[17] ,
+    \u_riscv_top.irq_lines[16] ,
+    \u_riscv_top.irq_lines[15] ,
+    \u_riscv_top.irq_lines[14] ,
+    \u_riscv_top.irq_lines[13] ,
+    \u_riscv_top.irq_lines[12] ,
+    \u_riscv_top.irq_lines[11] ,
+    \u_riscv_top.irq_lines[10] ,
+    \u_riscv_top.irq_lines[9] ,
+    \u_riscv_top.irq_lines[8] ,
+    \u_riscv_top.irq_lines[7] ,
+    \u_riscv_top.irq_lines[6] ,
+    \u_riscv_top.irq_lines[5] ,
+    \u_riscv_top.irq_lines[4] ,
+    \u_riscv_top.irq_lines[3] ,
+    \u_riscv_top.irq_lines[2] ,
+    \u_riscv_top.irq_lines[1] ,
+    \u_riscv_top.irq_lines[0] }),
+    .fpu_dmem_addr({\u_riscv_top.fpu_dmem_addr[4] ,
+    \u_riscv_top.fpu_dmem_addr[3] ,
+    \u_riscv_top.fpu_dmem_addr[2] ,
+    \u_riscv_top.fpu_dmem_addr[1] ,
+    \u_riscv_top.fpu_dmem_addr[0] }),
+    .fpu_dmem_rdata({\u_riscv_top.fpu_dmem_rdata[31] ,
+    \u_riscv_top.fpu_dmem_rdata[30] ,
+    \u_riscv_top.fpu_dmem_rdata[29] ,
+    \u_riscv_top.fpu_dmem_rdata[28] ,
+    \u_riscv_top.fpu_dmem_rdata[27] ,
+    \u_riscv_top.fpu_dmem_rdata[26] ,
+    \u_riscv_top.fpu_dmem_rdata[25] ,
+    \u_riscv_top.fpu_dmem_rdata[24] ,
+    \u_riscv_top.fpu_dmem_rdata[23] ,
+    \u_riscv_top.fpu_dmem_rdata[22] ,
+    \u_riscv_top.fpu_dmem_rdata[21] ,
+    \u_riscv_top.fpu_dmem_rdata[20] ,
+    \u_riscv_top.fpu_dmem_rdata[19] ,
+    \u_riscv_top.fpu_dmem_rdata[18] ,
+    \u_riscv_top.fpu_dmem_rdata[17] ,
+    \u_riscv_top.fpu_dmem_rdata[16] ,
+    \u_riscv_top.fpu_dmem_rdata[15] ,
+    \u_riscv_top.fpu_dmem_rdata[14] ,
+    \u_riscv_top.fpu_dmem_rdata[13] ,
+    \u_riscv_top.fpu_dmem_rdata[12] ,
+    \u_riscv_top.fpu_dmem_rdata[11] ,
+    \u_riscv_top.fpu_dmem_rdata[10] ,
+    \u_riscv_top.fpu_dmem_rdata[9] ,
+    \u_riscv_top.fpu_dmem_rdata[8] ,
+    \u_riscv_top.fpu_dmem_rdata[7] ,
+    \u_riscv_top.fpu_dmem_rdata[6] ,
+    \u_riscv_top.fpu_dmem_rdata[5] ,
+    \u_riscv_top.fpu_dmem_rdata[4] ,
+    \u_riscv_top.fpu_dmem_rdata[3] ,
+    \u_riscv_top.fpu_dmem_rdata[2] ,
+    \u_riscv_top.fpu_dmem_rdata[1] ,
+    \u_riscv_top.fpu_dmem_rdata[0] }),
+    .fpu_dmem_resp({\u_riscv_top.fpu_dmem_resp[1] ,
+    \u_riscv_top.fpu_dmem_resp[0] }),
+    .fpu_dmem_wdata({\u_riscv_top.fpu_dmem_wdata[31] ,
+    \u_riscv_top.fpu_dmem_wdata[30] ,
+    \u_riscv_top.fpu_dmem_wdata[29] ,
+    \u_riscv_top.fpu_dmem_wdata[28] ,
+    \u_riscv_top.fpu_dmem_wdata[27] ,
+    \u_riscv_top.fpu_dmem_wdata[26] ,
+    \u_riscv_top.fpu_dmem_wdata[25] ,
+    \u_riscv_top.fpu_dmem_wdata[24] ,
+    \u_riscv_top.fpu_dmem_wdata[23] ,
+    \u_riscv_top.fpu_dmem_wdata[22] ,
+    \u_riscv_top.fpu_dmem_wdata[21] ,
+    \u_riscv_top.fpu_dmem_wdata[20] ,
+    \u_riscv_top.fpu_dmem_wdata[19] ,
+    \u_riscv_top.fpu_dmem_wdata[18] ,
+    \u_riscv_top.fpu_dmem_wdata[17] ,
+    \u_riscv_top.fpu_dmem_wdata[16] ,
+    \u_riscv_top.fpu_dmem_wdata[15] ,
+    \u_riscv_top.fpu_dmem_wdata[14] ,
+    \u_riscv_top.fpu_dmem_wdata[13] ,
+    \u_riscv_top.fpu_dmem_wdata[12] ,
+    \u_riscv_top.fpu_dmem_wdata[11] ,
+    \u_riscv_top.fpu_dmem_wdata[10] ,
+    \u_riscv_top.fpu_dmem_wdata[9] ,
+    \u_riscv_top.fpu_dmem_wdata[8] ,
+    \u_riscv_top.fpu_dmem_wdata[7] ,
+    \u_riscv_top.fpu_dmem_wdata[6] ,
+    \u_riscv_top.fpu_dmem_wdata[5] ,
+    \u_riscv_top.fpu_dmem_wdata[4] ,
+    \u_riscv_top.fpu_dmem_wdata[3] ,
+    \u_riscv_top.fpu_dmem_wdata[2] ,
+    \u_riscv_top.fpu_dmem_wdata[1] ,
+    \u_riscv_top.fpu_dmem_wdata[0] }),
+    .fpu_dmem_width({\u_riscv_top.fpu_dmem_width[1] ,
+    \u_riscv_top.fpu_dmem_width[0] }),
+    .riscv_debug({la_data_out[63],
+    la_data_out[62],
+    la_data_out[61],
+    la_data_out[60],
+    la_data_out[59],
+    la_data_out[58],
+    la_data_out[57],
+    la_data_out[56],
+    la_data_out[55],
+    la_data_out[54],
+    la_data_out[53],
+    la_data_out[52],
+    la_data_out[51],
+    la_data_out[50],
+    la_data_out[49],
+    la_data_out[48],
+    la_data_out[47],
+    la_data_out[46],
+    la_data_out[45],
+    la_data_out[44],
+    la_data_out[43],
+    la_data_out[42],
+    la_data_out[41],
+    la_data_out[40],
+    la_data_out[39],
+    la_data_out[38],
+    la_data_out[37],
+    la_data_out[36],
+    la_data_out[35],
+    la_data_out[34],
+    la_data_out[33],
+    la_data_out[32],
+    la_data_out[31],
+    la_data_out[30],
+    la_data_out[29],
+    la_data_out[28],
+    la_data_out[27],
+    la_data_out[26],
+    la_data_out[25],
+    la_data_out[24],
+    la_data_out[23],
+    la_data_out[22],
+    la_data_out[21],
+    la_data_out[20],
+    la_data_out[19],
+    la_data_out[18],
+    la_data_out[17],
+    la_data_out[16],
+    la_data_out[15],
+    la_data_out[14],
+    la_data_out[13],
+    la_data_out[12],
+    la_data_out[11],
+    la_data_out[10],
+    la_data_out[9],
+    la_data_out[8],
+    la_data_out[7],
+    la_data_out[6],
+    la_data_out[5],
+    la_data_out[4],
+    la_data_out[3],
+    la_data_out[2],
+    la_data_out[1],
+    la_data_out[0]}),
+    .sram0_addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .sram0_addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .sram0_din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .sram0_dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+    \u_riscv_top.sram0_dout0[27] ,
+    \u_riscv_top.sram0_dout0[26] ,
+    \u_riscv_top.sram0_dout0[25] ,
+    \u_riscv_top.sram0_dout0[24] ,
+    \u_riscv_top.sram0_dout0[23] ,
+    \u_riscv_top.sram0_dout0[22] ,
+    \u_riscv_top.sram0_dout0[21] ,
+    \u_riscv_top.sram0_dout0[20] ,
+    \u_riscv_top.sram0_dout0[19] ,
+    \u_riscv_top.sram0_dout0[18] ,
+    \u_riscv_top.sram0_dout0[17] ,
+    \u_riscv_top.sram0_dout0[16] ,
+    \u_riscv_top.sram0_dout0[15] ,
+    \u_riscv_top.sram0_dout0[14] ,
+    \u_riscv_top.sram0_dout0[13] ,
+    \u_riscv_top.sram0_dout0[12] ,
+    \u_riscv_top.sram0_dout0[11] ,
+    \u_riscv_top.sram0_dout0[10] ,
+    \u_riscv_top.sram0_dout0[9] ,
+    \u_riscv_top.sram0_dout0[8] ,
+    \u_riscv_top.sram0_dout0[7] ,
+    \u_riscv_top.sram0_dout0[6] ,
+    \u_riscv_top.sram0_dout0[5] ,
+    \u_riscv_top.sram0_dout0[4] ,
+    \u_riscv_top.sram0_dout0[3] ,
+    \u_riscv_top.sram0_dout0[2] ,
+    \u_riscv_top.sram0_dout0[1] ,
+    \u_riscv_top.sram0_dout0[0] }),
+    .sram0_dout1({\u_riscv_top.sram0_dout1[31] ,
+    \u_riscv_top.sram0_dout1[30] ,
+    \u_riscv_top.sram0_dout1[29] ,
+    \u_riscv_top.sram0_dout1[28] ,
+    \u_riscv_top.sram0_dout1[27] ,
+    \u_riscv_top.sram0_dout1[26] ,
+    \u_riscv_top.sram0_dout1[25] ,
+    \u_riscv_top.sram0_dout1[24] ,
+    \u_riscv_top.sram0_dout1[23] ,
+    \u_riscv_top.sram0_dout1[22] ,
+    \u_riscv_top.sram0_dout1[21] ,
+    \u_riscv_top.sram0_dout1[20] ,
+    \u_riscv_top.sram0_dout1[19] ,
+    \u_riscv_top.sram0_dout1[18] ,
+    \u_riscv_top.sram0_dout1[17] ,
+    \u_riscv_top.sram0_dout1[16] ,
+    \u_riscv_top.sram0_dout1[15] ,
+    \u_riscv_top.sram0_dout1[14] ,
+    \u_riscv_top.sram0_dout1[13] ,
+    \u_riscv_top.sram0_dout1[12] ,
+    \u_riscv_top.sram0_dout1[11] ,
+    \u_riscv_top.sram0_dout1[10] ,
+    \u_riscv_top.sram0_dout1[9] ,
+    \u_riscv_top.sram0_dout1[8] ,
+    \u_riscv_top.sram0_dout1[7] ,
+    \u_riscv_top.sram0_dout1[6] ,
+    \u_riscv_top.sram0_dout1[5] ,
+    \u_riscv_top.sram0_dout1[4] ,
+    \u_riscv_top.sram0_dout1[3] ,
+    \u_riscv_top.sram0_dout1[2] ,
+    \u_riscv_top.sram0_dout1[1] ,
+    \u_riscv_top.sram0_dout1[0] }),
+    .sram0_wmask0({\u_riscv_top.sram0_wmask0[3] ,
+    \u_riscv_top.sram0_wmask0[2] ,
+    \u_riscv_top.sram0_wmask0[1] ,
+    \u_riscv_top.sram0_wmask0[0] }));
+ ycr_intf \u_riscv_top.u_intf  (.cfg_bypass_dcache(\cfg_riscv_ctrl[11] ),
+    .cfg_bypass_icache(\cfg_riscv_ctrl[10] ),
+    .cfg_dcache_force_flush(\u_riscv_top.cfg_dcache_force_flush ),
+    .cfg_dcache_pfet_dis(\cfg_riscv_ctrl[6] ),
+    .cfg_icache_ntag_pfet_dis(\cfg_riscv_ctrl[5] ),
+    .cfg_icache_pfet_dis(\cfg_riscv_ctrl[4] ),
+    .core_clk(\u_riscv_top.core_clk_intf_skew ),
+    .core_clk_int(\u_riscv_top.core_clk_int[0] ),
+    .core_clk_skew(\u_riscv_top.core_clk_intf_skew ),
+    .core_dcache_cmd(\u_riscv_top.core_dcache_cmd ),
+    .core_dcache_req(\u_riscv_top.core_dcache_req ),
+    .core_dcache_req_ack(\u_riscv_top.core_dcache_req_ack ),
+    .core_dmem_cmd(\u_riscv_top.core_dmem_cmd ),
+    .core_dmem_req(\u_riscv_top.core_dmem_req ),
+    .core_dmem_req_ack(\u_riscv_top.core_dmem_req_ack ),
+    .core_icache_cmd(\u_riscv_top.core_icache_cmd ),
+    .core_icache_req(\u_riscv_top.core_icache_req ),
+    .core_icache_req_ack(\u_riscv_top.core_icache_req_ack ),
+    .cpu_intf_rst_n(\u_riscv_top.cpu_intf_rst_n ),
+    .dcache_mem_clk0(\u_riscv_top.dcache_mem_clk0 ),
+    .dcache_mem_clk1(\u_riscv_top.dcache_mem_clk1 ),
+    .dcache_mem_csb0(\u_riscv_top.dcache_mem_csb0 ),
+    .dcache_mem_csb1(\u_riscv_top.dcache_mem_csb1 ),
+    .dcache_mem_web0(\u_riscv_top.dcache_mem_web0 ),
+    .icache_mem_clk0(\u_riscv_top.icache_mem_clk0 ),
+    .icache_mem_clk1(\u_riscv_top.icache_mem_clk1 ),
+    .icache_mem_csb0(\u_riscv_top.icache_mem_csb0 ),
+    .icache_mem_csb1(\u_riscv_top.icache_mem_csb1 ),
+    .icache_mem_web0(\u_riscv_top.icache_mem_web0 ),
+    .pwrup_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .wb_clk(\u_riscv_top.wb_clk ),
+    .wb_dcache_ack_i(\u_riscv_top.wb_dcache_ack_i ),
+    .wb_dcache_bry_o(\u_riscv_top.wb_dcache_bry_o ),
+    .wb_dcache_cyc_o(\u_riscv_top.wb_dcache_cyc_o ),
+    .wb_dcache_err_i(\u_riscv_top.wb_dcache_err_i ),
+    .wb_dcache_lack_i(\u_riscv_top.wb_dcache_lack_i ),
+    .wb_dcache_stb_o(\u_riscv_top.wb_dcache_stb_o ),
+    .wb_dcache_we_o(\u_riscv_top.wb_dcache_we_o ),
+    .wb_icache_ack_i(\u_riscv_top.wb_icache_ack_i ),
+    .wb_icache_bry_o(\u_riscv_top.wb_icache_bry_o ),
+    .wb_icache_cyc_o(\u_riscv_top.wb_icache_cyc_o ),
+    .wb_icache_err_i(\u_riscv_top.wb_icache_err_i ),
+    .wb_icache_lack_i(\u_riscv_top.wb_icache_lack_i ),
+    .wb_icache_stb_o(\u_riscv_top.wb_icache_stb_o ),
+    .wb_icache_we_o(\u_riscv_top.wb_icache_we_o ),
+    .wb_rst_n(\u_riscv_top.pwrup_rst_n ),
+    .wbd_clk_int(\u_riscv_top.wbd_clk_int ),
+    .wbd_clk_skew(\u_riscv_top.wb_clk ),
+    .wbd_dmem_ack_i(\u_riscv_top.wbd_dmem_ack_i ),
+    .wbd_dmem_bry_o(\u_riscv_top.wbd_dmem_bry_o ),
+    .wbd_dmem_err_i(\u_riscv_top.wbd_dmem_err_i ),
+    .wbd_dmem_lack_i(\u_riscv_top.wbd_dmem_lack_i ),
+    .wbd_dmem_stb_o(\u_riscv_top.wbd_dmem_stb_o ),
+    .wbd_dmem_we_o(\u_riscv_top.wbd_dmem_we_o ),
+    .cfg_ccska({\u_riscv_top.cfg_ccska_riscv_intf[3] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[2] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[1] ,
+    \u_riscv_top.cfg_ccska_riscv_intf[0] }),
+    .cfg_sram_lphase({\cfg_riscv_ctrl[1] ,
+    \cfg_riscv_ctrl[0] }),
+    .cfg_wcska({\u_riscv_top.cfg_wcska_riscv_intf[3] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[2] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[1] ,
+    \u_riscv_top.cfg_wcska_riscv_intf[0] }),
+    .core_dcache_addr({\u_riscv_top.core_dcache_addr[31] ,
+    \u_riscv_top.core_dcache_addr[30] ,
+    \u_riscv_top.core_dcache_addr[29] ,
+    \u_riscv_top.core_dcache_addr[28] ,
+    \u_riscv_top.core_dcache_addr[27] ,
+    \u_riscv_top.core_dcache_addr[26] ,
+    \u_riscv_top.core_dcache_addr[25] ,
+    \u_riscv_top.core_dcache_addr[24] ,
+    \u_riscv_top.core_dcache_addr[23] ,
+    \u_riscv_top.core_dcache_addr[22] ,
+    \u_riscv_top.core_dcache_addr[21] ,
+    \u_riscv_top.core_dcache_addr[20] ,
+    \u_riscv_top.core_dcache_addr[19] ,
+    \u_riscv_top.core_dcache_addr[18] ,
+    \u_riscv_top.core_dcache_addr[17] ,
+    \u_riscv_top.core_dcache_addr[16] ,
+    \u_riscv_top.core_dcache_addr[15] ,
+    \u_riscv_top.core_dcache_addr[14] ,
+    \u_riscv_top.core_dcache_addr[13] ,
+    \u_riscv_top.core_dcache_addr[12] ,
+    \u_riscv_top.core_dcache_addr[11] ,
+    \u_riscv_top.core_dcache_addr[10] ,
+    \u_riscv_top.core_dcache_addr[9] ,
+    \u_riscv_top.core_dcache_addr[8] ,
+    \u_riscv_top.core_dcache_addr[7] ,
+    \u_riscv_top.core_dcache_addr[6] ,
+    \u_riscv_top.core_dcache_addr[5] ,
+    \u_riscv_top.core_dcache_addr[4] ,
+    \u_riscv_top.core_dcache_addr[3] ,
+    \u_riscv_top.core_dcache_addr[2] ,
+    \u_riscv_top.core_dcache_addr[1] ,
+    \u_riscv_top.core_dcache_addr[0] }),
+    .core_dcache_rdata({\u_riscv_top.core_dcache_rdata[31] ,
+    \u_riscv_top.core_dcache_rdata[30] ,
+    \u_riscv_top.core_dcache_rdata[29] ,
+    \u_riscv_top.core_dcache_rdata[28] ,
+    \u_riscv_top.core_dcache_rdata[27] ,
+    \u_riscv_top.core_dcache_rdata[26] ,
+    \u_riscv_top.core_dcache_rdata[25] ,
+    \u_riscv_top.core_dcache_rdata[24] ,
+    \u_riscv_top.core_dcache_rdata[23] ,
+    \u_riscv_top.core_dcache_rdata[22] ,
+    \u_riscv_top.core_dcache_rdata[21] ,
+    \u_riscv_top.core_dcache_rdata[20] ,
+    \u_riscv_top.core_dcache_rdata[19] ,
+    \u_riscv_top.core_dcache_rdata[18] ,
+    \u_riscv_top.core_dcache_rdata[17] ,
+    \u_riscv_top.core_dcache_rdata[16] ,
+    \u_riscv_top.core_dcache_rdata[15] ,
+    \u_riscv_top.core_dcache_rdata[14] ,
+    \u_riscv_top.core_dcache_rdata[13] ,
+    \u_riscv_top.core_dcache_rdata[12] ,
+    \u_riscv_top.core_dcache_rdata[11] ,
+    \u_riscv_top.core_dcache_rdata[10] ,
+    \u_riscv_top.core_dcache_rdata[9] ,
+    \u_riscv_top.core_dcache_rdata[8] ,
+    \u_riscv_top.core_dcache_rdata[7] ,
+    \u_riscv_top.core_dcache_rdata[6] ,
+    \u_riscv_top.core_dcache_rdata[5] ,
+    \u_riscv_top.core_dcache_rdata[4] ,
+    \u_riscv_top.core_dcache_rdata[3] ,
+    \u_riscv_top.core_dcache_rdata[2] ,
+    \u_riscv_top.core_dcache_rdata[1] ,
+    \u_riscv_top.core_dcache_rdata[0] }),
+    .core_dcache_resp({\u_riscv_top.core_dcache_resp[1] ,
+    \u_riscv_top.core_dcache_resp[0] }),
+    .core_dcache_wdata({\u_riscv_top.core_dcache_wdata[31] ,
+    \u_riscv_top.core_dcache_wdata[30] ,
+    \u_riscv_top.core_dcache_wdata[29] ,
+    \u_riscv_top.core_dcache_wdata[28] ,
+    \u_riscv_top.core_dcache_wdata[27] ,
+    \u_riscv_top.core_dcache_wdata[26] ,
+    \u_riscv_top.core_dcache_wdata[25] ,
+    \u_riscv_top.core_dcache_wdata[24] ,
+    \u_riscv_top.core_dcache_wdata[23] ,
+    \u_riscv_top.core_dcache_wdata[22] ,
+    \u_riscv_top.core_dcache_wdata[21] ,
+    \u_riscv_top.core_dcache_wdata[20] ,
+    \u_riscv_top.core_dcache_wdata[19] ,
+    \u_riscv_top.core_dcache_wdata[18] ,
+    \u_riscv_top.core_dcache_wdata[17] ,
+    \u_riscv_top.core_dcache_wdata[16] ,
+    \u_riscv_top.core_dcache_wdata[15] ,
+    \u_riscv_top.core_dcache_wdata[14] ,
+    \u_riscv_top.core_dcache_wdata[13] ,
+    \u_riscv_top.core_dcache_wdata[12] ,
+    \u_riscv_top.core_dcache_wdata[11] ,
+    \u_riscv_top.core_dcache_wdata[10] ,
+    \u_riscv_top.core_dcache_wdata[9] ,
+    \u_riscv_top.core_dcache_wdata[8] ,
+    \u_riscv_top.core_dcache_wdata[7] ,
+    \u_riscv_top.core_dcache_wdata[6] ,
+    \u_riscv_top.core_dcache_wdata[5] ,
+    \u_riscv_top.core_dcache_wdata[4] ,
+    \u_riscv_top.core_dcache_wdata[3] ,
+    \u_riscv_top.core_dcache_wdata[2] ,
+    \u_riscv_top.core_dcache_wdata[1] ,
+    \u_riscv_top.core_dcache_wdata[0] }),
+    .core_dcache_width({\u_riscv_top.core_dcache_width[1] ,
+    \u_riscv_top.core_dcache_width[0] }),
+    .core_dmem_addr({\u_riscv_top.core_dmem_addr[31] ,
+    \u_riscv_top.core_dmem_addr[30] ,
+    \u_riscv_top.core_dmem_addr[29] ,
+    \u_riscv_top.core_dmem_addr[28] ,
+    \u_riscv_top.core_dmem_addr[27] ,
+    \u_riscv_top.core_dmem_addr[26] ,
+    \u_riscv_top.core_dmem_addr[25] ,
+    \u_riscv_top.core_dmem_addr[24] ,
+    \u_riscv_top.core_dmem_addr[23] ,
+    \u_riscv_top.core_dmem_addr[22] ,
+    \u_riscv_top.core_dmem_addr[21] ,
+    \u_riscv_top.core_dmem_addr[20] ,
+    \u_riscv_top.core_dmem_addr[19] ,
+    \u_riscv_top.core_dmem_addr[18] ,
+    \u_riscv_top.core_dmem_addr[17] ,
+    \u_riscv_top.core_dmem_addr[16] ,
+    \u_riscv_top.core_dmem_addr[15] ,
+    \u_riscv_top.core_dmem_addr[14] ,
+    \u_riscv_top.core_dmem_addr[13] ,
+    \u_riscv_top.core_dmem_addr[12] ,
+    \u_riscv_top.core_dmem_addr[11] ,
+    \u_riscv_top.core_dmem_addr[10] ,
+    \u_riscv_top.core_dmem_addr[9] ,
+    \u_riscv_top.core_dmem_addr[8] ,
+    \u_riscv_top.core_dmem_addr[7] ,
+    \u_riscv_top.core_dmem_addr[6] ,
+    \u_riscv_top.core_dmem_addr[5] ,
+    \u_riscv_top.core_dmem_addr[4] ,
+    \u_riscv_top.core_dmem_addr[3] ,
+    \u_riscv_top.core_dmem_addr[2] ,
+    \u_riscv_top.core_dmem_addr[1] ,
+    \u_riscv_top.core_dmem_addr[0] }),
+    .core_dmem_bl({\u_riscv_top.core_dmem_bl[2] ,
+    \u_riscv_top.core_dmem_bl[1] ,
+    \u_riscv_top.core_dmem_bl[0] }),
+    .core_dmem_rdata({\u_riscv_top.core_dmem_rdata[31] ,
+    \u_riscv_top.core_dmem_rdata[30] ,
+    \u_riscv_top.core_dmem_rdata[29] ,
+    \u_riscv_top.core_dmem_rdata[28] ,
+    \u_riscv_top.core_dmem_rdata[27] ,
+    \u_riscv_top.core_dmem_rdata[26] ,
+    \u_riscv_top.core_dmem_rdata[25] ,
+    \u_riscv_top.core_dmem_rdata[24] ,
+    \u_riscv_top.core_dmem_rdata[23] ,
+    \u_riscv_top.core_dmem_rdata[22] ,
+    \u_riscv_top.core_dmem_rdata[21] ,
+    \u_riscv_top.core_dmem_rdata[20] ,
+    \u_riscv_top.core_dmem_rdata[19] ,
+    \u_riscv_top.core_dmem_rdata[18] ,
+    \u_riscv_top.core_dmem_rdata[17] ,
+    \u_riscv_top.core_dmem_rdata[16] ,
+    \u_riscv_top.core_dmem_rdata[15] ,
+    \u_riscv_top.core_dmem_rdata[14] ,
+    \u_riscv_top.core_dmem_rdata[13] ,
+    \u_riscv_top.core_dmem_rdata[12] ,
+    \u_riscv_top.core_dmem_rdata[11] ,
+    \u_riscv_top.core_dmem_rdata[10] ,
+    \u_riscv_top.core_dmem_rdata[9] ,
+    \u_riscv_top.core_dmem_rdata[8] ,
+    \u_riscv_top.core_dmem_rdata[7] ,
+    \u_riscv_top.core_dmem_rdata[6] ,
+    \u_riscv_top.core_dmem_rdata[5] ,
+    \u_riscv_top.core_dmem_rdata[4] ,
+    \u_riscv_top.core_dmem_rdata[3] ,
+    \u_riscv_top.core_dmem_rdata[2] ,
+    \u_riscv_top.core_dmem_rdata[1] ,
+    \u_riscv_top.core_dmem_rdata[0] }),
+    .core_dmem_resp({\u_riscv_top.core_dmem_resp[1] ,
+    \u_riscv_top.core_dmem_resp[0] }),
+    .core_dmem_wdata({\u_riscv_top.core_dmem_wdata[31] ,
+    \u_riscv_top.core_dmem_wdata[30] ,
+    \u_riscv_top.core_dmem_wdata[29] ,
+    \u_riscv_top.core_dmem_wdata[28] ,
+    \u_riscv_top.core_dmem_wdata[27] ,
+    \u_riscv_top.core_dmem_wdata[26] ,
+    \u_riscv_top.core_dmem_wdata[25] ,
+    \u_riscv_top.core_dmem_wdata[24] ,
+    \u_riscv_top.core_dmem_wdata[23] ,
+    \u_riscv_top.core_dmem_wdata[22] ,
+    \u_riscv_top.core_dmem_wdata[21] ,
+    \u_riscv_top.core_dmem_wdata[20] ,
+    \u_riscv_top.core_dmem_wdata[19] ,
+    \u_riscv_top.core_dmem_wdata[18] ,
+    \u_riscv_top.core_dmem_wdata[17] ,
+    \u_riscv_top.core_dmem_wdata[16] ,
+    \u_riscv_top.core_dmem_wdata[15] ,
+    \u_riscv_top.core_dmem_wdata[14] ,
+    \u_riscv_top.core_dmem_wdata[13] ,
+    \u_riscv_top.core_dmem_wdata[12] ,
+    \u_riscv_top.core_dmem_wdata[11] ,
+    \u_riscv_top.core_dmem_wdata[10] ,
+    \u_riscv_top.core_dmem_wdata[9] ,
+    \u_riscv_top.core_dmem_wdata[8] ,
+    \u_riscv_top.core_dmem_wdata[7] ,
+    \u_riscv_top.core_dmem_wdata[6] ,
+    \u_riscv_top.core_dmem_wdata[5] ,
+    \u_riscv_top.core_dmem_wdata[4] ,
+    \u_riscv_top.core_dmem_wdata[3] ,
+    \u_riscv_top.core_dmem_wdata[2] ,
+    \u_riscv_top.core_dmem_wdata[1] ,
+    \u_riscv_top.core_dmem_wdata[0] }),
+    .core_dmem_width({\u_riscv_top.core_dmem_width[1] ,
+    \u_riscv_top.core_dmem_width[0] }),
+    .core_icache_addr({\u_riscv_top.core_icache_addr[31] ,
+    \u_riscv_top.core_icache_addr[30] ,
+    \u_riscv_top.core_icache_addr[29] ,
+    \u_riscv_top.core_icache_addr[28] ,
+    \u_riscv_top.core_icache_addr[27] ,
+    \u_riscv_top.core_icache_addr[26] ,
+    \u_riscv_top.core_icache_addr[25] ,
+    \u_riscv_top.core_icache_addr[24] ,
+    \u_riscv_top.core_icache_addr[23] ,
+    \u_riscv_top.core_icache_addr[22] ,
+    \u_riscv_top.core_icache_addr[21] ,
+    \u_riscv_top.core_icache_addr[20] ,
+    \u_riscv_top.core_icache_addr[19] ,
+    \u_riscv_top.core_icache_addr[18] ,
+    \u_riscv_top.core_icache_addr[17] ,
+    \u_riscv_top.core_icache_addr[16] ,
+    \u_riscv_top.core_icache_addr[15] ,
+    \u_riscv_top.core_icache_addr[14] ,
+    \u_riscv_top.core_icache_addr[13] ,
+    \u_riscv_top.core_icache_addr[12] ,
+    \u_riscv_top.core_icache_addr[11] ,
+    \u_riscv_top.core_icache_addr[10] ,
+    \u_riscv_top.core_icache_addr[9] ,
+    \u_riscv_top.core_icache_addr[8] ,
+    \u_riscv_top.core_icache_addr[7] ,
+    \u_riscv_top.core_icache_addr[6] ,
+    \u_riscv_top.core_icache_addr[5] ,
+    \u_riscv_top.core_icache_addr[4] ,
+    \u_riscv_top.core_icache_addr[3] ,
+    \u_riscv_top.core_icache_addr[2] ,
+    \u_riscv_top.core_icache_addr[1] ,
+    \u_riscv_top.core_icache_addr[0] }),
+    .core_icache_bl({\u_riscv_top.core_icache_bl[2] ,
+    \u_riscv_top.core_icache_bl[1] ,
+    \u_riscv_top.core_icache_bl[0] }),
+    .core_icache_rdata({\u_riscv_top.core_icache_rdata[31] ,
+    \u_riscv_top.core_icache_rdata[30] ,
+    \u_riscv_top.core_icache_rdata[29] ,
+    \u_riscv_top.core_icache_rdata[28] ,
+    \u_riscv_top.core_icache_rdata[27] ,
+    \u_riscv_top.core_icache_rdata[26] ,
+    \u_riscv_top.core_icache_rdata[25] ,
+    \u_riscv_top.core_icache_rdata[24] ,
+    \u_riscv_top.core_icache_rdata[23] ,
+    \u_riscv_top.core_icache_rdata[22] ,
+    \u_riscv_top.core_icache_rdata[21] ,
+    \u_riscv_top.core_icache_rdata[20] ,
+    \u_riscv_top.core_icache_rdata[19] ,
+    \u_riscv_top.core_icache_rdata[18] ,
+    \u_riscv_top.core_icache_rdata[17] ,
+    \u_riscv_top.core_icache_rdata[16] ,
+    \u_riscv_top.core_icache_rdata[15] ,
+    \u_riscv_top.core_icache_rdata[14] ,
+    \u_riscv_top.core_icache_rdata[13] ,
+    \u_riscv_top.core_icache_rdata[12] ,
+    \u_riscv_top.core_icache_rdata[11] ,
+    \u_riscv_top.core_icache_rdata[10] ,
+    \u_riscv_top.core_icache_rdata[9] ,
+    \u_riscv_top.core_icache_rdata[8] ,
+    \u_riscv_top.core_icache_rdata[7] ,
+    \u_riscv_top.core_icache_rdata[6] ,
+    \u_riscv_top.core_icache_rdata[5] ,
+    \u_riscv_top.core_icache_rdata[4] ,
+    \u_riscv_top.core_icache_rdata[3] ,
+    \u_riscv_top.core_icache_rdata[2] ,
+    \u_riscv_top.core_icache_rdata[1] ,
+    \u_riscv_top.core_icache_rdata[0] }),
+    .core_icache_resp({\u_riscv_top.core_icache_resp[1] ,
+    \u_riscv_top.core_icache_resp[0] }),
+    .core_icache_width({\u_riscv_top.core_icache_width[1] ,
+    \u_riscv_top.core_icache_width[0] }),
+    .dcache_mem_addr0({\u_riscv_top.dcache_mem_addr0[8] ,
+    \u_riscv_top.dcache_mem_addr0[7] ,
+    \u_riscv_top.dcache_mem_addr0[6] ,
+    \u_riscv_top.dcache_mem_addr0[5] ,
+    \u_riscv_top.dcache_mem_addr0[4] ,
+    \u_riscv_top.dcache_mem_addr0[3] ,
+    \u_riscv_top.dcache_mem_addr0[2] ,
+    \u_riscv_top.dcache_mem_addr0[1] ,
+    \u_riscv_top.dcache_mem_addr0[0] }),
+    .dcache_mem_addr1({\u_riscv_top.dcache_mem_addr1[8] ,
+    \u_riscv_top.dcache_mem_addr1[7] ,
+    \u_riscv_top.dcache_mem_addr1[6] ,
+    \u_riscv_top.dcache_mem_addr1[5] ,
+    \u_riscv_top.dcache_mem_addr1[4] ,
+    \u_riscv_top.dcache_mem_addr1[3] ,
+    \u_riscv_top.dcache_mem_addr1[2] ,
+    \u_riscv_top.dcache_mem_addr1[1] ,
+    \u_riscv_top.dcache_mem_addr1[0] }),
+    .dcache_mem_din0({\u_riscv_top.dcache_mem_din0[31] ,
+    \u_riscv_top.dcache_mem_din0[30] ,
+    \u_riscv_top.dcache_mem_din0[29] ,
+    \u_riscv_top.dcache_mem_din0[28] ,
+    \u_riscv_top.dcache_mem_din0[27] ,
+    \u_riscv_top.dcache_mem_din0[26] ,
+    \u_riscv_top.dcache_mem_din0[25] ,
+    \u_riscv_top.dcache_mem_din0[24] ,
+    \u_riscv_top.dcache_mem_din0[23] ,
+    \u_riscv_top.dcache_mem_din0[22] ,
+    \u_riscv_top.dcache_mem_din0[21] ,
+    \u_riscv_top.dcache_mem_din0[20] ,
+    \u_riscv_top.dcache_mem_din0[19] ,
+    \u_riscv_top.dcache_mem_din0[18] ,
+    \u_riscv_top.dcache_mem_din0[17] ,
+    \u_riscv_top.dcache_mem_din0[16] ,
+    \u_riscv_top.dcache_mem_din0[15] ,
+    \u_riscv_top.dcache_mem_din0[14] ,
+    \u_riscv_top.dcache_mem_din0[13] ,
+    \u_riscv_top.dcache_mem_din0[12] ,
+    \u_riscv_top.dcache_mem_din0[11] ,
+    \u_riscv_top.dcache_mem_din0[10] ,
+    \u_riscv_top.dcache_mem_din0[9] ,
+    \u_riscv_top.dcache_mem_din0[8] ,
+    \u_riscv_top.dcache_mem_din0[7] ,
+    \u_riscv_top.dcache_mem_din0[6] ,
+    \u_riscv_top.dcache_mem_din0[5] ,
+    \u_riscv_top.dcache_mem_din0[4] ,
+    \u_riscv_top.dcache_mem_din0[3] ,
+    \u_riscv_top.dcache_mem_din0[2] ,
+    \u_riscv_top.dcache_mem_din0[1] ,
+    \u_riscv_top.dcache_mem_din0[0] }),
+    .dcache_mem_dout0({\u_riscv_top.dcache_mem_dout0[31] ,
+    \u_riscv_top.dcache_mem_dout0[30] ,
+    \u_riscv_top.dcache_mem_dout0[29] ,
+    \u_riscv_top.dcache_mem_dout0[28] ,
+    \u_riscv_top.dcache_mem_dout0[27] ,
+    \u_riscv_top.dcache_mem_dout0[26] ,
+    \u_riscv_top.dcache_mem_dout0[25] ,
+    \u_riscv_top.dcache_mem_dout0[24] ,
+    \u_riscv_top.dcache_mem_dout0[23] ,
+    \u_riscv_top.dcache_mem_dout0[22] ,
+    \u_riscv_top.dcache_mem_dout0[21] ,
+    \u_riscv_top.dcache_mem_dout0[20] ,
+    \u_riscv_top.dcache_mem_dout0[19] ,
+    \u_riscv_top.dcache_mem_dout0[18] ,
+    \u_riscv_top.dcache_mem_dout0[17] ,
+    \u_riscv_top.dcache_mem_dout0[16] ,
+    \u_riscv_top.dcache_mem_dout0[15] ,
+    \u_riscv_top.dcache_mem_dout0[14] ,
+    \u_riscv_top.dcache_mem_dout0[13] ,
+    \u_riscv_top.dcache_mem_dout0[12] ,
+    \u_riscv_top.dcache_mem_dout0[11] ,
+    \u_riscv_top.dcache_mem_dout0[10] ,
+    \u_riscv_top.dcache_mem_dout0[9] ,
+    \u_riscv_top.dcache_mem_dout0[8] ,
+    \u_riscv_top.dcache_mem_dout0[7] ,
+    \u_riscv_top.dcache_mem_dout0[6] ,
+    \u_riscv_top.dcache_mem_dout0[5] ,
+    \u_riscv_top.dcache_mem_dout0[4] ,
+    \u_riscv_top.dcache_mem_dout0[3] ,
+    \u_riscv_top.dcache_mem_dout0[2] ,
+    \u_riscv_top.dcache_mem_dout0[1] ,
+    \u_riscv_top.dcache_mem_dout0[0] }),
+    .dcache_mem_dout1({\u_riscv_top.dcache_mem_dout1[31] ,
+    \u_riscv_top.dcache_mem_dout1[30] ,
+    \u_riscv_top.dcache_mem_dout1[29] ,
+    \u_riscv_top.dcache_mem_dout1[28] ,
+    \u_riscv_top.dcache_mem_dout1[27] ,
+    \u_riscv_top.dcache_mem_dout1[26] ,
+    \u_riscv_top.dcache_mem_dout1[25] ,
+    \u_riscv_top.dcache_mem_dout1[24] ,
+    \u_riscv_top.dcache_mem_dout1[23] ,
+    \u_riscv_top.dcache_mem_dout1[22] ,
+    \u_riscv_top.dcache_mem_dout1[21] ,
+    \u_riscv_top.dcache_mem_dout1[20] ,
+    \u_riscv_top.dcache_mem_dout1[19] ,
+    \u_riscv_top.dcache_mem_dout1[18] ,
+    \u_riscv_top.dcache_mem_dout1[17] ,
+    \u_riscv_top.dcache_mem_dout1[16] ,
+    \u_riscv_top.dcache_mem_dout1[15] ,
+    \u_riscv_top.dcache_mem_dout1[14] ,
+    \u_riscv_top.dcache_mem_dout1[13] ,
+    \u_riscv_top.dcache_mem_dout1[12] ,
+    \u_riscv_top.dcache_mem_dout1[11] ,
+    \u_riscv_top.dcache_mem_dout1[10] ,
+    \u_riscv_top.dcache_mem_dout1[9] ,
+    \u_riscv_top.dcache_mem_dout1[8] ,
+    \u_riscv_top.dcache_mem_dout1[7] ,
+    \u_riscv_top.dcache_mem_dout1[6] ,
+    \u_riscv_top.dcache_mem_dout1[5] ,
+    \u_riscv_top.dcache_mem_dout1[4] ,
+    \u_riscv_top.dcache_mem_dout1[3] ,
+    \u_riscv_top.dcache_mem_dout1[2] ,
+    \u_riscv_top.dcache_mem_dout1[1] ,
+    \u_riscv_top.dcache_mem_dout1[0] }),
+    .dcache_mem_wmask0({\u_riscv_top.dcache_mem_wmask0[3] ,
+    \u_riscv_top.dcache_mem_wmask0[2] ,
+    \u_riscv_top.dcache_mem_wmask0[1] ,
+    \u_riscv_top.dcache_mem_wmask0[0] }),
+    .icache_mem_addr0({\u_riscv_top.icache_mem_addr0[8] ,
+    \u_riscv_top.icache_mem_addr0[7] ,
+    \u_riscv_top.icache_mem_addr0[6] ,
+    \u_riscv_top.icache_mem_addr0[5] ,
+    \u_riscv_top.icache_mem_addr0[4] ,
+    \u_riscv_top.icache_mem_addr0[3] ,
+    \u_riscv_top.icache_mem_addr0[2] ,
+    \u_riscv_top.icache_mem_addr0[1] ,
+    \u_riscv_top.icache_mem_addr0[0] }),
+    .icache_mem_addr1({\u_riscv_top.icache_mem_addr1[8] ,
+    \u_riscv_top.icache_mem_addr1[7] ,
+    \u_riscv_top.icache_mem_addr1[6] ,
+    \u_riscv_top.icache_mem_addr1[5] ,
+    \u_riscv_top.icache_mem_addr1[4] ,
+    \u_riscv_top.icache_mem_addr1[3] ,
+    \u_riscv_top.icache_mem_addr1[2] ,
+    \u_riscv_top.icache_mem_addr1[1] ,
+    \u_riscv_top.icache_mem_addr1[0] }),
+    .icache_mem_din0({\u_riscv_top.icache_mem_din0[31] ,
+    \u_riscv_top.icache_mem_din0[30] ,
+    \u_riscv_top.icache_mem_din0[29] ,
+    \u_riscv_top.icache_mem_din0[28] ,
+    \u_riscv_top.icache_mem_din0[27] ,
+    \u_riscv_top.icache_mem_din0[26] ,
+    \u_riscv_top.icache_mem_din0[25] ,
+    \u_riscv_top.icache_mem_din0[24] ,
+    \u_riscv_top.icache_mem_din0[23] ,
+    \u_riscv_top.icache_mem_din0[22] ,
+    \u_riscv_top.icache_mem_din0[21] ,
+    \u_riscv_top.icache_mem_din0[20] ,
+    \u_riscv_top.icache_mem_din0[19] ,
+    \u_riscv_top.icache_mem_din0[18] ,
+    \u_riscv_top.icache_mem_din0[17] ,
+    \u_riscv_top.icache_mem_din0[16] ,
+    \u_riscv_top.icache_mem_din0[15] ,
+    \u_riscv_top.icache_mem_din0[14] ,
+    \u_riscv_top.icache_mem_din0[13] ,
+    \u_riscv_top.icache_mem_din0[12] ,
+    \u_riscv_top.icache_mem_din0[11] ,
+    \u_riscv_top.icache_mem_din0[10] ,
+    \u_riscv_top.icache_mem_din0[9] ,
+    \u_riscv_top.icache_mem_din0[8] ,
+    \u_riscv_top.icache_mem_din0[7] ,
+    \u_riscv_top.icache_mem_din0[6] ,
+    \u_riscv_top.icache_mem_din0[5] ,
+    \u_riscv_top.icache_mem_din0[4] ,
+    \u_riscv_top.icache_mem_din0[3] ,
+    \u_riscv_top.icache_mem_din0[2] ,
+    \u_riscv_top.icache_mem_din0[1] ,
+    \u_riscv_top.icache_mem_din0[0] }),
+    .icache_mem_dout1({\u_riscv_top.icache_mem_dout1[31] ,
+    \u_riscv_top.icache_mem_dout1[30] ,
+    \u_riscv_top.icache_mem_dout1[29] ,
+    \u_riscv_top.icache_mem_dout1[28] ,
+    \u_riscv_top.icache_mem_dout1[27] ,
+    \u_riscv_top.icache_mem_dout1[26] ,
+    \u_riscv_top.icache_mem_dout1[25] ,
+    \u_riscv_top.icache_mem_dout1[24] ,
+    \u_riscv_top.icache_mem_dout1[23] ,
+    \u_riscv_top.icache_mem_dout1[22] ,
+    \u_riscv_top.icache_mem_dout1[21] ,
+    \u_riscv_top.icache_mem_dout1[20] ,
+    \u_riscv_top.icache_mem_dout1[19] ,
+    \u_riscv_top.icache_mem_dout1[18] ,
+    \u_riscv_top.icache_mem_dout1[17] ,
+    \u_riscv_top.icache_mem_dout1[16] ,
+    \u_riscv_top.icache_mem_dout1[15] ,
+    \u_riscv_top.icache_mem_dout1[14] ,
+    \u_riscv_top.icache_mem_dout1[13] ,
+    \u_riscv_top.icache_mem_dout1[12] ,
+    \u_riscv_top.icache_mem_dout1[11] ,
+    \u_riscv_top.icache_mem_dout1[10] ,
+    \u_riscv_top.icache_mem_dout1[9] ,
+    \u_riscv_top.icache_mem_dout1[8] ,
+    \u_riscv_top.icache_mem_dout1[7] ,
+    \u_riscv_top.icache_mem_dout1[6] ,
+    \u_riscv_top.icache_mem_dout1[5] ,
+    \u_riscv_top.icache_mem_dout1[4] ,
+    \u_riscv_top.icache_mem_dout1[3] ,
+    \u_riscv_top.icache_mem_dout1[2] ,
+    \u_riscv_top.icache_mem_dout1[1] ,
+    \u_riscv_top.icache_mem_dout1[0] }),
+    .icache_mem_wmask0({\u_riscv_top.icache_mem_wmask0[3] ,
+    \u_riscv_top.icache_mem_wmask0[2] ,
+    \u_riscv_top.icache_mem_wmask0[1] ,
+    \u_riscv_top.icache_mem_wmask0[0] }),
+    .wb_dcache_adr_o({\u_riscv_top.wb_dcache_adr_o[31] ,
+    \u_riscv_top.wb_dcache_adr_o[30] ,
+    \u_riscv_top.wb_dcache_adr_o[29] ,
+    \u_riscv_top.wb_dcache_adr_o[28] ,
+    \u_riscv_top.wb_dcache_adr_o[27] ,
+    \u_riscv_top.wb_dcache_adr_o[26] ,
+    \u_riscv_top.wb_dcache_adr_o[25] ,
+    \u_riscv_top.wb_dcache_adr_o[24] ,
+    \u_riscv_top.wb_dcache_adr_o[23] ,
+    \u_riscv_top.wb_dcache_adr_o[22] ,
+    \u_riscv_top.wb_dcache_adr_o[21] ,
+    \u_riscv_top.wb_dcache_adr_o[20] ,
+    \u_riscv_top.wb_dcache_adr_o[19] ,
+    \u_riscv_top.wb_dcache_adr_o[18] ,
+    \u_riscv_top.wb_dcache_adr_o[17] ,
+    \u_riscv_top.wb_dcache_adr_o[16] ,
+    \u_riscv_top.wb_dcache_adr_o[15] ,
+    \u_riscv_top.wb_dcache_adr_o[14] ,
+    \u_riscv_top.wb_dcache_adr_o[13] ,
+    \u_riscv_top.wb_dcache_adr_o[12] ,
+    \u_riscv_top.wb_dcache_adr_o[11] ,
+    \u_riscv_top.wb_dcache_adr_o[10] ,
+    \u_riscv_top.wb_dcache_adr_o[9] ,
+    \u_riscv_top.wb_dcache_adr_o[8] ,
+    \u_riscv_top.wb_dcache_adr_o[7] ,
+    \u_riscv_top.wb_dcache_adr_o[6] ,
+    \u_riscv_top.wb_dcache_adr_o[5] ,
+    \u_riscv_top.wb_dcache_adr_o[4] ,
+    \u_riscv_top.wb_dcache_adr_o[3] ,
+    \u_riscv_top.wb_dcache_adr_o[2] ,
+    \u_riscv_top.wb_dcache_adr_o[1] ,
+    \u_riscv_top.wb_dcache_adr_o[0] }),
+    .wb_dcache_bl_o({\u_riscv_top.wb_dcache_bl_o[9] ,
+    \u_riscv_top.wb_dcache_bl_o[8] ,
+    \u_riscv_top.wb_dcache_bl_o[7] ,
+    \u_riscv_top.wb_dcache_bl_o[6] ,
+    \u_riscv_top.wb_dcache_bl_o[5] ,
+    \u_riscv_top.wb_dcache_bl_o[4] ,
+    \u_riscv_top.wb_dcache_bl_o[3] ,
+    \u_riscv_top.wb_dcache_bl_o[2] ,
+    \u_riscv_top.wb_dcache_bl_o[1] ,
+    \u_riscv_top.wb_dcache_bl_o[0] }),
+    .wb_dcache_dat_i({\u_riscv_top.wb_dcache_dat_i[31] ,
+    \u_riscv_top.wb_dcache_dat_i[30] ,
+    \u_riscv_top.wb_dcache_dat_i[29] ,
+    \u_riscv_top.wb_dcache_dat_i[28] ,
+    \u_riscv_top.wb_dcache_dat_i[27] ,
+    \u_riscv_top.wb_dcache_dat_i[26] ,
+    \u_riscv_top.wb_dcache_dat_i[25] ,
+    \u_riscv_top.wb_dcache_dat_i[24] ,
+    \u_riscv_top.wb_dcache_dat_i[23] ,
+    \u_riscv_top.wb_dcache_dat_i[22] ,
+    \u_riscv_top.wb_dcache_dat_i[21] ,
+    \u_riscv_top.wb_dcache_dat_i[20] ,
+    \u_riscv_top.wb_dcache_dat_i[19] ,
+    \u_riscv_top.wb_dcache_dat_i[18] ,
+    \u_riscv_top.wb_dcache_dat_i[17] ,
+    \u_riscv_top.wb_dcache_dat_i[16] ,
+    \u_riscv_top.wb_dcache_dat_i[15] ,
+    \u_riscv_top.wb_dcache_dat_i[14] ,
+    \u_riscv_top.wb_dcache_dat_i[13] ,
+    \u_riscv_top.wb_dcache_dat_i[12] ,
+    \u_riscv_top.wb_dcache_dat_i[11] ,
+    \u_riscv_top.wb_dcache_dat_i[10] ,
+    \u_riscv_top.wb_dcache_dat_i[9] ,
+    \u_riscv_top.wb_dcache_dat_i[8] ,
+    \u_riscv_top.wb_dcache_dat_i[7] ,
+    \u_riscv_top.wb_dcache_dat_i[6] ,
+    \u_riscv_top.wb_dcache_dat_i[5] ,
+    \u_riscv_top.wb_dcache_dat_i[4] ,
+    \u_riscv_top.wb_dcache_dat_i[3] ,
+    \u_riscv_top.wb_dcache_dat_i[2] ,
+    \u_riscv_top.wb_dcache_dat_i[1] ,
+    \u_riscv_top.wb_dcache_dat_i[0] }),
+    .wb_dcache_dat_o({\u_riscv_top.wb_dcache_dat_o[31] ,
+    \u_riscv_top.wb_dcache_dat_o[30] ,
+    \u_riscv_top.wb_dcache_dat_o[29] ,
+    \u_riscv_top.wb_dcache_dat_o[28] ,
+    \u_riscv_top.wb_dcache_dat_o[27] ,
+    \u_riscv_top.wb_dcache_dat_o[26] ,
+    \u_riscv_top.wb_dcache_dat_o[25] ,
+    \u_riscv_top.wb_dcache_dat_o[24] ,
+    \u_riscv_top.wb_dcache_dat_o[23] ,
+    \u_riscv_top.wb_dcache_dat_o[22] ,
+    \u_riscv_top.wb_dcache_dat_o[21] ,
+    \u_riscv_top.wb_dcache_dat_o[20] ,
+    \u_riscv_top.wb_dcache_dat_o[19] ,
+    \u_riscv_top.wb_dcache_dat_o[18] ,
+    \u_riscv_top.wb_dcache_dat_o[17] ,
+    \u_riscv_top.wb_dcache_dat_o[16] ,
+    \u_riscv_top.wb_dcache_dat_o[15] ,
+    \u_riscv_top.wb_dcache_dat_o[14] ,
+    \u_riscv_top.wb_dcache_dat_o[13] ,
+    \u_riscv_top.wb_dcache_dat_o[12] ,
+    \u_riscv_top.wb_dcache_dat_o[11] ,
+    \u_riscv_top.wb_dcache_dat_o[10] ,
+    \u_riscv_top.wb_dcache_dat_o[9] ,
+    \u_riscv_top.wb_dcache_dat_o[8] ,
+    \u_riscv_top.wb_dcache_dat_o[7] ,
+    \u_riscv_top.wb_dcache_dat_o[6] ,
+    \u_riscv_top.wb_dcache_dat_o[5] ,
+    \u_riscv_top.wb_dcache_dat_o[4] ,
+    \u_riscv_top.wb_dcache_dat_o[3] ,
+    \u_riscv_top.wb_dcache_dat_o[2] ,
+    \u_riscv_top.wb_dcache_dat_o[1] ,
+    \u_riscv_top.wb_dcache_dat_o[0] }),
+    .wb_dcache_sel_o({\u_riscv_top.wb_dcache_sel_o[3] ,
+    \u_riscv_top.wb_dcache_sel_o[2] ,
+    \u_riscv_top.wb_dcache_sel_o[1] ,
+    \u_riscv_top.wb_dcache_sel_o[0] }),
+    .wb_icache_adr_o({\u_riscv_top.wb_icache_adr_o[31] ,
+    \u_riscv_top.wb_icache_adr_o[30] ,
+    \u_riscv_top.wb_icache_adr_o[29] ,
+    \u_riscv_top.wb_icache_adr_o[28] ,
+    \u_riscv_top.wb_icache_adr_o[27] ,
+    \u_riscv_top.wb_icache_adr_o[26] ,
+    \u_riscv_top.wb_icache_adr_o[25] ,
+    \u_riscv_top.wb_icache_adr_o[24] ,
+    \u_riscv_top.wb_icache_adr_o[23] ,
+    \u_riscv_top.wb_icache_adr_o[22] ,
+    \u_riscv_top.wb_icache_adr_o[21] ,
+    \u_riscv_top.wb_icache_adr_o[20] ,
+    \u_riscv_top.wb_icache_adr_o[19] ,
+    \u_riscv_top.wb_icache_adr_o[18] ,
+    \u_riscv_top.wb_icache_adr_o[17] ,
+    \u_riscv_top.wb_icache_adr_o[16] ,
+    \u_riscv_top.wb_icache_adr_o[15] ,
+    \u_riscv_top.wb_icache_adr_o[14] ,
+    \u_riscv_top.wb_icache_adr_o[13] ,
+    \u_riscv_top.wb_icache_adr_o[12] ,
+    \u_riscv_top.wb_icache_adr_o[11] ,
+    \u_riscv_top.wb_icache_adr_o[10] ,
+    \u_riscv_top.wb_icache_adr_o[9] ,
+    \u_riscv_top.wb_icache_adr_o[8] ,
+    \u_riscv_top.wb_icache_adr_o[7] ,
+    \u_riscv_top.wb_icache_adr_o[6] ,
+    \u_riscv_top.wb_icache_adr_o[5] ,
+    \u_riscv_top.wb_icache_adr_o[4] ,
+    \u_riscv_top.wb_icache_adr_o[3] ,
+    \u_riscv_top.wb_icache_adr_o[2] ,
+    \u_riscv_top.wb_icache_adr_o[1] ,
+    \u_riscv_top.wb_icache_adr_o[0] }),
+    .wb_icache_bl_o({\u_riscv_top.wb_icache_bl_o[9] ,
+    \u_riscv_top.wb_icache_bl_o[8] ,
+    \u_riscv_top.wb_icache_bl_o[7] ,
+    \u_riscv_top.wb_icache_bl_o[6] ,
+    \u_riscv_top.wb_icache_bl_o[5] ,
+    \u_riscv_top.wb_icache_bl_o[4] ,
+    \u_riscv_top.wb_icache_bl_o[3] ,
+    \u_riscv_top.wb_icache_bl_o[2] ,
+    \u_riscv_top.wb_icache_bl_o[1] ,
+    \u_riscv_top.wb_icache_bl_o[0] }),
+    .wb_icache_dat_i({\u_riscv_top.wb_icache_dat_i[31] ,
+    \u_riscv_top.wb_icache_dat_i[30] ,
+    \u_riscv_top.wb_icache_dat_i[29] ,
+    \u_riscv_top.wb_icache_dat_i[28] ,
+    \u_riscv_top.wb_icache_dat_i[27] ,
+    \u_riscv_top.wb_icache_dat_i[26] ,
+    \u_riscv_top.wb_icache_dat_i[25] ,
+    \u_riscv_top.wb_icache_dat_i[24] ,
+    \u_riscv_top.wb_icache_dat_i[23] ,
+    \u_riscv_top.wb_icache_dat_i[22] ,
+    \u_riscv_top.wb_icache_dat_i[21] ,
+    \u_riscv_top.wb_icache_dat_i[20] ,
+    \u_riscv_top.wb_icache_dat_i[19] ,
+    \u_riscv_top.wb_icache_dat_i[18] ,
+    \u_riscv_top.wb_icache_dat_i[17] ,
+    \u_riscv_top.wb_icache_dat_i[16] ,
+    \u_riscv_top.wb_icache_dat_i[15] ,
+    \u_riscv_top.wb_icache_dat_i[14] ,
+    \u_riscv_top.wb_icache_dat_i[13] ,
+    \u_riscv_top.wb_icache_dat_i[12] ,
+    \u_riscv_top.wb_icache_dat_i[11] ,
+    \u_riscv_top.wb_icache_dat_i[10] ,
+    \u_riscv_top.wb_icache_dat_i[9] ,
+    \u_riscv_top.wb_icache_dat_i[8] ,
+    \u_riscv_top.wb_icache_dat_i[7] ,
+    \u_riscv_top.wb_icache_dat_i[6] ,
+    \u_riscv_top.wb_icache_dat_i[5] ,
+    \u_riscv_top.wb_icache_dat_i[4] ,
+    \u_riscv_top.wb_icache_dat_i[3] ,
+    \u_riscv_top.wb_icache_dat_i[2] ,
+    \u_riscv_top.wb_icache_dat_i[1] ,
+    \u_riscv_top.wb_icache_dat_i[0] }),
+    .wb_icache_sel_o({\u_riscv_top.wb_icache_sel_o[3] ,
+    \u_riscv_top.wb_icache_sel_o[2] ,
+    \u_riscv_top.wb_icache_sel_o[1] ,
+    \u_riscv_top.wb_icache_sel_o[0] }),
+    .wbd_dmem_adr_o({\u_riscv_top.wbd_dmem_adr_o[31] ,
+    \u_riscv_top.wbd_dmem_adr_o[30] ,
+    \u_riscv_top.wbd_dmem_adr_o[29] ,
+    \u_riscv_top.wbd_dmem_adr_o[28] ,
+    \u_riscv_top.wbd_dmem_adr_o[27] ,
+    \u_riscv_top.wbd_dmem_adr_o[26] ,
+    \u_riscv_top.wbd_dmem_adr_o[25] ,
+    \u_riscv_top.wbd_dmem_adr_o[24] ,
+    \u_riscv_top.wbd_dmem_adr_o[23] ,
+    \u_riscv_top.wbd_dmem_adr_o[22] ,
+    \u_riscv_top.wbd_dmem_adr_o[21] ,
+    \u_riscv_top.wbd_dmem_adr_o[20] ,
+    \u_riscv_top.wbd_dmem_adr_o[19] ,
+    \u_riscv_top.wbd_dmem_adr_o[18] ,
+    \u_riscv_top.wbd_dmem_adr_o[17] ,
+    \u_riscv_top.wbd_dmem_adr_o[16] ,
+    \u_riscv_top.wbd_dmem_adr_o[15] ,
+    \u_riscv_top.wbd_dmem_adr_o[14] ,
+    \u_riscv_top.wbd_dmem_adr_o[13] ,
+    \u_riscv_top.wbd_dmem_adr_o[12] ,
+    \u_riscv_top.wbd_dmem_adr_o[11] ,
+    \u_riscv_top.wbd_dmem_adr_o[10] ,
+    \u_riscv_top.wbd_dmem_adr_o[9] ,
+    \u_riscv_top.wbd_dmem_adr_o[8] ,
+    \u_riscv_top.wbd_dmem_adr_o[7] ,
+    \u_riscv_top.wbd_dmem_adr_o[6] ,
+    \u_riscv_top.wbd_dmem_adr_o[5] ,
+    \u_riscv_top.wbd_dmem_adr_o[4] ,
+    \u_riscv_top.wbd_dmem_adr_o[3] ,
+    \u_riscv_top.wbd_dmem_adr_o[2] ,
+    \u_riscv_top.wbd_dmem_adr_o[1] ,
+    \u_riscv_top.wbd_dmem_adr_o[0] }),
+    .wbd_dmem_bl_o({\u_riscv_top.wbd_dmem_bl_o[2] ,
+    \u_riscv_top.wbd_dmem_bl_o[1] ,
+    \u_riscv_top.wbd_dmem_bl_o[0] }),
+    .wbd_dmem_dat_i({\u_riscv_top.wbd_dmem_dat_i[31] ,
+    \u_riscv_top.wbd_dmem_dat_i[30] ,
+    \u_riscv_top.wbd_dmem_dat_i[29] ,
+    \u_riscv_top.wbd_dmem_dat_i[28] ,
+    \u_riscv_top.wbd_dmem_dat_i[27] ,
+    \u_riscv_top.wbd_dmem_dat_i[26] ,
+    \u_riscv_top.wbd_dmem_dat_i[25] ,
+    \u_riscv_top.wbd_dmem_dat_i[24] ,
+    \u_riscv_top.wbd_dmem_dat_i[23] ,
+    \u_riscv_top.wbd_dmem_dat_i[22] ,
+    \u_riscv_top.wbd_dmem_dat_i[21] ,
+    \u_riscv_top.wbd_dmem_dat_i[20] ,
+    \u_riscv_top.wbd_dmem_dat_i[19] ,
+    \u_riscv_top.wbd_dmem_dat_i[18] ,
+    \u_riscv_top.wbd_dmem_dat_i[17] ,
+    \u_riscv_top.wbd_dmem_dat_i[16] ,
+    \u_riscv_top.wbd_dmem_dat_i[15] ,
+    \u_riscv_top.wbd_dmem_dat_i[14] ,
+    \u_riscv_top.wbd_dmem_dat_i[13] ,
+    \u_riscv_top.wbd_dmem_dat_i[12] ,
+    \u_riscv_top.wbd_dmem_dat_i[11] ,
+    \u_riscv_top.wbd_dmem_dat_i[10] ,
+    \u_riscv_top.wbd_dmem_dat_i[9] ,
+    \u_riscv_top.wbd_dmem_dat_i[8] ,
+    \u_riscv_top.wbd_dmem_dat_i[7] ,
+    \u_riscv_top.wbd_dmem_dat_i[6] ,
+    \u_riscv_top.wbd_dmem_dat_i[5] ,
+    \u_riscv_top.wbd_dmem_dat_i[4] ,
+    \u_riscv_top.wbd_dmem_dat_i[3] ,
+    \u_riscv_top.wbd_dmem_dat_i[2] ,
+    \u_riscv_top.wbd_dmem_dat_i[1] ,
+    \u_riscv_top.wbd_dmem_dat_i[0] }),
+    .wbd_dmem_dat_o({\u_riscv_top.wbd_dmem_dat_o[31] ,
+    \u_riscv_top.wbd_dmem_dat_o[30] ,
+    \u_riscv_top.wbd_dmem_dat_o[29] ,
+    \u_riscv_top.wbd_dmem_dat_o[28] ,
+    \u_riscv_top.wbd_dmem_dat_o[27] ,
+    \u_riscv_top.wbd_dmem_dat_o[26] ,
+    \u_riscv_top.wbd_dmem_dat_o[25] ,
+    \u_riscv_top.wbd_dmem_dat_o[24] ,
+    \u_riscv_top.wbd_dmem_dat_o[23] ,
+    \u_riscv_top.wbd_dmem_dat_o[22] ,
+    \u_riscv_top.wbd_dmem_dat_o[21] ,
+    \u_riscv_top.wbd_dmem_dat_o[20] ,
+    \u_riscv_top.wbd_dmem_dat_o[19] ,
+    \u_riscv_top.wbd_dmem_dat_o[18] ,
+    \u_riscv_top.wbd_dmem_dat_o[17] ,
+    \u_riscv_top.wbd_dmem_dat_o[16] ,
+    \u_riscv_top.wbd_dmem_dat_o[15] ,
+    \u_riscv_top.wbd_dmem_dat_o[14] ,
+    \u_riscv_top.wbd_dmem_dat_o[13] ,
+    \u_riscv_top.wbd_dmem_dat_o[12] ,
+    \u_riscv_top.wbd_dmem_dat_o[11] ,
+    \u_riscv_top.wbd_dmem_dat_o[10] ,
+    \u_riscv_top.wbd_dmem_dat_o[9] ,
+    \u_riscv_top.wbd_dmem_dat_o[8] ,
+    \u_riscv_top.wbd_dmem_dat_o[7] ,
+    \u_riscv_top.wbd_dmem_dat_o[6] ,
+    \u_riscv_top.wbd_dmem_dat_o[5] ,
+    \u_riscv_top.wbd_dmem_dat_o[4] ,
+    \u_riscv_top.wbd_dmem_dat_o[3] ,
+    \u_riscv_top.wbd_dmem_dat_o[2] ,
+    \u_riscv_top.wbd_dmem_dat_o[1] ,
+    \u_riscv_top.wbd_dmem_dat_o[0] }),
+    .wbd_dmem_sel_o({\u_riscv_top.wbd_dmem_sel_o[3] ,
+    \u_riscv_top.wbd_dmem_sel_o[2] ,
+    \u_riscv_top.wbd_dmem_sel_o[1] ,
+    \u_riscv_top.wbd_dmem_sel_o[0] }));
+ sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb (.csb0(\u_riscv_top.sram0_csb0 ),
+    .csb1(\u_riscv_top.sram0_csb1 ),
+    .web0(\u_riscv_top.sram0_web0 ),
+    .clk0(\u_riscv_top.sram0_clk0 ),
+    .clk1(\u_riscv_top.sram0_clk1 ),
+    .vccd1(vccd1),
+    .vssd1(vssd1),
+    .addr0({\u_riscv_top.sram0_addr0[8] ,
+    \u_riscv_top.sram0_addr0[7] ,
+    \u_riscv_top.sram0_addr0[6] ,
+    \u_riscv_top.sram0_addr0[5] ,
+    \u_riscv_top.sram0_addr0[4] ,
+    \u_riscv_top.sram0_addr0[3] ,
+    \u_riscv_top.sram0_addr0[2] ,
+    \u_riscv_top.sram0_addr0[1] ,
+    \u_riscv_top.sram0_addr0[0] }),
+    .addr1({\u_riscv_top.sram0_addr1[8] ,
+    \u_riscv_top.sram0_addr1[7] ,
+    \u_riscv_top.sram0_addr1[6] ,
+    \u_riscv_top.sram0_addr1[5] ,
+    \u_riscv_top.sram0_addr1[4] ,
+    \u_riscv_top.sram0_addr1[3] ,
+    \u_riscv_top.sram0_addr1[2] ,
+    \u_riscv_top.sram0_addr1[1] ,
+    \u_riscv_top.sram0_addr1[0] }),
+    .din0({\u_riscv_top.sram0_din0[31] ,
+    \u_riscv_top.sram0_din0[30] ,
+    \u_riscv_top.sram0_din0[29] ,
+    \u_riscv_top.sram0_din0[28] ,
+    \u_riscv_top.sram0_din0[27] ,
+    \u_riscv_top.sram0_din0[26] ,
+    \u_riscv_top.sram0_din0[25] ,
+    \u_riscv_top.sram0_din0[24] ,
+    \u_riscv_top.sram0_din0[23] ,
+    \u_riscv_top.sram0_din0[22] ,
+    \u_riscv_top.sram0_din0[21] ,
+    \u_riscv_top.sram0_din0[20] ,
+    \u_riscv_top.sram0_din0[19] ,
+    \u_riscv_top.sram0_din0[18] ,
+    \u_riscv_top.sram0_din0[17] ,
+    \u_riscv_top.sram0_din0[16] ,
+    \u_riscv_top.sram0_din0[15] ,
+    \u_riscv_top.sram0_din0[14] ,
+    \u_riscv_top.sram0_din0[13] ,
+    \u_riscv_top.sram0_din0[12] ,
+    \u_riscv_top.sram0_din0[11] ,
+    \u_riscv_top.sram0_din0[10] ,
+    \u_riscv_top.sram0_din0[9] ,
+    \u_riscv_top.sram0_din0[8] ,
+    \u_riscv_top.sram0_din0[7] ,
+    \u_riscv_top.sram0_din0[6] ,
+    \u_riscv_top.sram0_din0[5] ,
+    \u_riscv_top.sram0_din0[4] ,
+    \u_riscv_top.sram0_din0[3] ,
+    \u_riscv_top.sram0_din0[2] ,
+    \u_riscv_top.sram0_din0[1] ,
+    \u_riscv_top.sram0_din0[0] }),
+    .dout0({\u_riscv_top.sram0_dout0[31] ,
+    \u_riscv_top.sram0_dout0[30] ,
+    \u_riscv_top.sram0_dout0[29] ,
+    \u_riscv_top.sram0_dout0[28] ,
+