AES/FPU Power Hook up fix + Pinmux Resync
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e1f03c7..b9e53fb 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -74,7 +74,7 @@
$::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/ycr2_iconnect.v \
$::env(DESIGN_DIR)/../../verilog/gl/dg_pll.v \
- $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
$::env(DESIGN_DIR)/../../verilog/gl/dac_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/aes_top.v \
$::env(DESIGN_DIR)/../../verilog/gl/fpu_wrapper.v \
@@ -180,8 +180,8 @@
u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1,\
u_4x8bit_dac vdda1 vssa1 vccd1 vssd1,\
- u_aes vdda1 vssa1 vccd1 vssd1,\
- u_fpu vdda1 vssa1 vccd1 vssd1
+ u_aes vccd1 vssd1 vccd1 vssd1,\
+ u_fpu vccd1 vssd1 vccd1 vssd1
"
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 6bda236..75cd3e9 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@
begin
// Run in Fast Sim Mode
`ifdef GL
- force u_top.u_wb_host._10673_.Q= 1'b1;
+ force u_top.u_wb_host._10252_.Q= 1'b1;
`else
force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1;
`endif
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 2865bda..4f74553 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -219,6 +219,24 @@
fork
begin
$display("##########################################################");
+ $display("Step-0,Monitor: Checking the chip signature :");
+ $display("###################################################");
+ test_id = 0;
+ test_step = 0;
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
+ if(test_fail == 1) begin
+ $display("ERROR: Step-0,Monitor: Checking the chip signature - FAILED");
+ end else begin
+ $display("STATUS: Step-0,Monitor: Checking the chip signature - PASSED");
+ $display("##########################################################");
+ end
+
+ $display("##########################################################");
$display("Step-1, Checking the Strap Loading");
test_id = 1;
for(i = 0; i < 16; i = i+1) begin
@@ -510,25 +528,6 @@
$display("##########################################################");
end
- $display("##########################################################");
- $display("Step-11,Monitor: Checking the chip signature :");
- $display("###################################################");
- test_id = 11;
- test_step = 14;
- // Remove Wb/PinMux Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
-
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,CHIP_SIGNATURE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,CHIP_RELEASE_DATE);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,CHIP_REVISION);
- if(test_fail == 1) begin
- $display("ERROR: Step-11,Monitor: Checking the chip signature - FAILED");
- end else begin
- $display("STATUS: Step-11,Monitor: Checking the chip signature - PASSED");
-
- $display("##########################################################");
-
- end
end
begin
repeat (500000) @(posedge clock);
@@ -668,7 +667,7 @@
input real exp_period;
begin
`ifdef GL
- force clock_mon = u_top.u_wb_host._09635_.Q;
+ force clock_mon = u_top.u_wb_host._10366_.Q;
`else
force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
`endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 59e8b61..d7c52cc 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -222,6 +222,8 @@
#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
+$(USER_PROJECT_VERILOG)/gl/aes_top.v
+$(USER_PROJECT_VERILOG)/gl/fpu_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index adb39ff..3b11f4f 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,9 +4,9 @@
// ASCI Representation of RISC = 32'h8273_8343
parameter CHIP_SIGNATURE = 32'h8273_8343;
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h2711_2022;
+parameter CHIP_RELEASE_DATE = 32'h2811_2022;
// Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION = 32'h0006_0000;
+parameter CHIP_REVISION = 32'h0006_1000;
parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_1000_1000_1110_1000_0100;
parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_1000_0111_1110;
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f7b53fa..fc2e8b8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -13,7 +13,7 @@
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
//
//////////////////////////////////////////////////////////////////////
//// ////
@@ -289,7 +289,10 @@
//// cpu_clk will be feed through wb_interconnect for ////
//// buffering purpose ////
//// 6.0 Nov 27, 2022, Dinesh A ////
-//// MPW-7 Timing clean setup
+//// MPW-7 Timing clean setup ////
+//// 6.1 Nov 28, 2022, Dinesh A ////
+//// Power Hook up connectivity issue for ////
+//// aes,fpu,bus repeater is fixed ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -1240,8 +1243,8 @@
*************************************************/
aes_top u_aes (
`ifdef USE_POWER_PINS
- .vccd1 (vdda1 ),
- .vssd1 (vssa1 ),
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
`endif
.mclk (cpu_clk_aes ),
@@ -1266,8 +1269,8 @@
*************************************************/
fpu_wrapper u_fpu (
`ifdef USE_POWER_PINS
- .vccd1 (vdda1 ),
- .vssd1 (vssa1 ),
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
`endif
.mclk (cpu_clk_fpu ),
