k
diff --git a/openlane/matrix_multiply/config.json b/openlane/matrix_multiply/config.json
new file mode 100644
index 0000000..367234a
--- /dev/null
+++ b/openlane/matrix_multiply/config.json
@@ -0,0 +1,50 @@
+{
+ "DESIGN_NAME": "matrix_multiply",
+ "DESIGN_IS_CORE": 0,
+ "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/matrix_multiply.v"],
+ "CLOCK_PERIOD": 30,
+ "CLOCK_PORT": "clk",
+ "CLOCK_NET": "clk",
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 400 400",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.45,
+ "VDD_NETS": ["vccd1"],
+ "GND_NETS": ["vssd1"],
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_CVC": 0,
+ "PL_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
+ "PL_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+ "GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT": 80,
+ "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.8,
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "RT_MAX_LAYER": "met4",
+ "scl::sky130_fd_sc_hd": {
+ "CLOCK_PERIOD": 30
+ },
+ "scl::sky130_fd_sc_hdll": {
+ "CLOCK_PERIOD": 20
+ },
+ "scl::sky130_fd_sc_hs": {
+ "CLOCK_PERIOD": 8
+ },
+ "scl::sky130_fd_sc_ls": {
+ "CLOCK_PERIOD": 10,
+ "SYNTH_MAX_FANOUT": 5
+ },
+ "scl::sky130_fd_sc_ms": {
+ "CLOCK_PERIOD": 10
+ }
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "CLOCK_PERIOD": 24.0,
+ "FP_CORE_UTIL": 40,
+ "RT_MAX_LAYER": "Metal4",
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+
+ }
+}
diff --git a/openlane/matrix_multiply/pin_order.cfg b/openlane/matrix_multiply/pin_order.cfg
new file mode 100644
index 0000000..9af1ddd
--- /dev/null
+++ b/openlane/matrix_multiply/pin_order.cfg
@@ -0,0 +1,13 @@
+
+#S
+in.*
+ou.*
+clken
+rst
+#N
+io_.*
+reset.*
+execute.*
+clk.*
+sel_.*
+
