commit | f0c8a864d867812ae17dda22b0ae7f2108700eb0 | [log] [tgz] |
---|---|---|
author | Ruige <295054118@whut.edu.cn> | Thu Nov 24 21:48:13 2022 +0800 |
committer | Ruige <295054118@whut.edu.cn> | Thu Nov 24 21:48:13 2022 +0800 |
tree | 0e11035f9238cb743b2fa2d9a3a039f81dc8bdad | |
parent | 5ec6d70dea1ec1b3288778649be316a77d2ef9b4 [diff] |
submit for Rift2310 Signed-off-by: Ruige <295054118@whut.edu.cn>
This is a simple version of Rift2Core. Commit: b95a1555aeb79d975e8b273d412f0e6df42d0322 (Almost...)
The configuration is as followed:
class Rift2310 extends Config((site, here, up) => { case RiftParamsKey => RiftSetting( hasL2 = true, hasDebugger = true, hasPreFetch = false, hasuBTB = false, ftChn = 4, rnChn = 1, opChn = 1, wbChn = 1, cm_chn = 1, pmpNum = 0, regNum = 34, hpmNum = 0, l1BeatBits = 64, memBeatBits = 64, tlbEntry = 2, l1DW = 128, ifetchParameters = IFParameters( uBTB_entry = 4, btb_cl = 4, bim_cl = 8, ras_dp = 4, ), icacheParameters = IcacheParameters( bk = 1, cb = 1, cl = 2, ), dcacheParameters = DcacheParameters( bk = 1, cb = 1, cl = 2, sbEntry = 2, stEntry = 2, ), dptEntry = 2, fpuNum = 0, mulNum = 1, isMinArea = true, isLowPower = false, ) })