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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-034

Rift2Core: Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

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Branches

  1. 676140c final gds oasis by Jeff DiCorpo · 1 year, 11 months ago main
  2. 489fa09 resubmission of rift2Fake by Ruige · 2 years ago
  3. 3f2d7c3 Update Makefile by Jeff DiCorpo · 2 years ago
  4. cfb7c9a Merge pull request #200 from efabless/jeffdi-patch-1 by Jeff DiCorpo · 2 years ago
  5. 6ef5d79 Update index.rst by Jeff DiCorpo · 2 years ago

Caravel User Project: Rift2Chip 2330

Attention

A Fake Code “LFSR16” and “Multiplier”is Uploaded.

LFSR

A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. A IO can lock the LFSR, it will be connect to a switch.

Multiplier

A Multiplier in Rift2Core is instance in 32-bits Mode. All ports are connected to la. It's Boot4-WallceTree Multiplier.

Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

RiftCore is the previous version of Rift2Core in Verilog.

Rift To Go

Download Pre-compile Version Here, the newest status is as follows:

VersionTestDhrystoneCoreMark
Rift-2300N/AN/AN/A
Rift-2310N/AN/AN/A
Rift-2320N/AN/AN/A
Rift-2330
Rift-2340
Rift-2350
Rift-2360
Rift-2370
Rift-2380
Rift-2390

API

Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules.

Search the provided API in the Scala Doc.

API Here

Wiki

Wiki in Chinese

Wiki in English(Comming Soon!)

Micro-Architecture

FrontEnd

FrontEnd

BackEnd

BackEnd