| commit | 676140cae62b43eb75d58d256b0c3531beacd2c3 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 11:46:35 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 11:46:35 2022 -0800 |
| tree | b8691aee027b9b8505a2628d3ff1287030c1a429 | |
| parent | 489fa09e052067d288a25c835fcae67ec90d79a5 [diff] |
final gds oasis
A Fake Code “LFSR16” and “Multiplier”is Uploaded.
A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. A IO can lock the LFSR, it will be connect to a switch.
Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.
RiftCore is the previous version of Rift2Core in Verilog.
Download Pre-compile Version Here, the newest status is as follows:
| Version | Test | Dhrystone | CoreMark |
|---|---|---|---|
| Rift-2300 | N/A | N/A | N/A |
| Rift-2310 | N/A | N/A | N/A |
| Rift-2320 | N/A | N/A | N/A |
| Rift-2330 |  |  |  |
| Rift-2340 |  |  |  |
| Rift-2350 |  |  |  |
| Rift-2360 |  |  |  |
| Rift-2370 |  |  |  |
| Rift-2380 |  |  |  |
| Rift-2390 |  |  |  |
Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules.
Search the provided API in the Scala Doc.
Wiki in English(Comming Soon!)
