|author||Ruige <firstname.lastname@example.org>||Mon Nov 21 21:31:31 2022 +0800|
|committer||Ruige <email@example.com>||Mon Nov 21 21:31:31 2022 +0800|
resubmission of rift2Fake
A Fake Code “LFSR16” and “Multiplier”is Uploaded.
A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. A IO can lock the LFSR, it will be connect to a switch.
Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.
RiftCore is the previous version of Rift2Core in Verilog.
Download Pre-compile Version Here, the newest status is as follows:
Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules.
Search the provided API in the Scala Doc.
Wiki in English(Comming Soon!)