commit	489fa09e052067d288a25c835fcae67ec90d79a5	[log] [tgz]
author	Ruige <295054118@whut.edu.cn>	Mon Nov 21 21:31:31 2022 +0800
committer	Ruige <295054118@whut.edu.cn>	Mon Nov 21 21:31:31 2022 +0800
tree	4a4f148c96f4ee3945493bc1df72b270482351d5
parent	3f2d7c3ed02a001d422a868cac7f187b4566a7f4 [diff]

resubmission of rift2Fake

Makefile[diff]
README.md[diff]
def/rift2Wrap.def[Added - diff]
def/user_project_wrapper.def[diff]
gds/rift2Wrap.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
lef/rift2Wrap.lef[Added - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[diff]
mag/rift2Wrap.mag[Added - diff]
mag/user_project_wrapper.mag[diff]
maglef/user_project_wrapper.mag[diff]
openlane/rift2Fake/config.json[Added - diff]
openlane/rift2Fake/config.tcl.BK[Added - diff]
openlane/rift2Fake/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[diff]
signoff/user_project_wrapper/OPENLANE_VERSION[diff]
signoff/user_project_wrapper/PDK_SOURCES[diff]
spi/lvs/rift2Wrap.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/gl/rift2Wrap.nl.v[Added - diff]
verilog/gl/rift2Wrap.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/Multiplier.v[Added - diff]
verilog/rtl/Sky130BLFSR.v[Added - diff]
verilog/rtl/rift2Fake.v[Added - diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

32 files changed

tree: 4a4f148c96f4ee3945493bc1df72b270482351d5

README.md

Caravel User Project: Rift2Chip 2330

Attention

A Fake Code “LFSR16” and “Multiplier”is Uploaded.

LFSR

A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. A IO can lock the LFSR, it will be connect to a switch.

Multiplier

A Multiplier in Rift2Core is instance in 32-bits Mode. All ports are connected to la. It's Boot4-WallceTree Multiplier.

Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

RiftCore is the previous version of Rift2Core in Verilog.

Rift To Go

Download Pre-compile Version Here, the newest status is as follows:

Version	Test	Dhrystone	CoreMark
Rift-2300	N/A	N/A	N/A
Rift-2310	N/A	N/A	N/A
Rift-2320	N/A	N/A	N/A
Rift-2330
Rift-2340
Rift-2350
Rift-2360
Rift-2370
Rift-2380
Rift-2390

API

Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules.

Search the provided API in the Scala Doc.

Wiki

Wiki in Chinese

Wiki in English(Comming Soon!)

Micro-Architecture

FrontEnd

FrontEnd

BackEnd

BackEnd