| commit | 3def96a8c8ec6e66376e22f013cd6296e57859c8 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Sun Aug 22 17:49:55 2021 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Sun Aug 22 17:49:55 2021 -0400 |
| tree | 4b0c41f2aa3bc126d12e943edf76c95b72afb571 | |
| parent | 610ad9ab1653119b2d2f0d463792d0ae46e960b5 [diff] |
Updated with various corrections. There are now three testbenches, adding one which exercises the LUT programming write, load, and read cycles; and one which exercises the full array programming and tests the LUT core cell functions, applying data to the array through the logic analyzer, and reading data from the array.
| :exclamation: Important Note |
|---|
Refer to README for this sample project documentation.
Digital design for Caravel (user_project_wrapper)
This chip is a pure asynchronous cellular automaton. Each cell has four inputs from N, S, E, W and generates four outputs to N, S, E, W. Each cell can be configured for any boolean function of the four inputs.
Outputs on the periphery (or some selection thereof) are passed to the chip GPIO. Inputs may also come from the chip periphery; choice of input or output is programmable like the cell boolean function.
All inputs and outputs may be channeled through the logic analyzer to set or grab the entire state of the system.
The logic analyzer may also be used to program the cell functions.
This can be used in a loop with an evolutionary algorithm to tune the chip functions to achieve a specific behavior.
Most of the core circuitry is straightforward. The total number of cells is parameterized, so that the largest number of cells that will fit in the caravel user project space can be determined.