tree 4b0c41f2aa3bc126d12e943edf76c95b72afb571
parent 610ad9ab1653119b2d2f0d463792d0ae46e960b5
author Tim Edwards <tim@opencircuitdesign.com> 1629668995 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1629668995 -0400

Updated with various corrections.  There are now three testbenches,
adding one which exercises the LUT programming write, load, and
read cycles;  and one which exercises the full array programming
and tests the LUT core cell functions, applying data to the array
through the logic analyzer, and reading data from the array.