tree: 2988fdf1cbb5e527296b3f5e2ea01cf4ba3e92f5 [path history] [tgz]
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

Caravel Analog User

License CI Caravan Build


This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.


Refer to README for this sample project documentation. ~