commit 975e81cdf1f3996839e00ebd22606c9ff18b8c71
author Ali Imran <59641896+ALI11-2000@users.noreply.github.com> Sun Aug 14 21:21:21 2022 +0500
committer GitHub <noreply@github.com> Sun Aug 14 21:21:21 2022 +0500
tree 7fc8d5ff002c1a6ac24264651de1aae196ebff62
parent 1b7a1b715507e8a1b8d1b1148d923a450a27a70a

SRAM Updated

verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v

diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 79721fb..e07ecae 100644
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -108,11 +108,6 @@
         if (!csb1_reg)

            dout1 <=  mem[addr1_reg];

       end

-

-      initial begin

-        $display("Reading Memory");

-        $readmemh("imem.hex", mem);

-      end

     

     endmodule

     
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