diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 79721fb..e07ecae 100644
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -108,11 +108,6 @@
         if (!csb1_reg)
            dout1 <=  mem[addr1_reg];
       end
-
-      initial begin
-        $display("Reading Memory");
-        $readmemh("imem.hex", mem);
-      end
     
     endmodule
     
\ No newline at end of file