/*============================================================================ | |
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point | |
Arithmetic Package, Release 1, by John R. Hauser. | |
Copyright 2019 The Regents of the University of California. All rights | |
reserved. | |
Redistribution and use in source and binary forms, with or without | |
modification, are permitted provided that the following conditions are met: | |
1. Redistributions of source code must retain the above copyright notice, | |
this list of conditions, and the following disclaimer. | |
2. Redistributions in binary form must reproduce the above copyright notice, | |
this list of conditions, and the following disclaimer in the documentation | |
and/or other materials provided with the distribution. | |
3. Neither the name of the University nor the names of its contributors may | |
be used to endorse or promote products derived from this software without | |
specific prior written permission. | |
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY | |
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE | |
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY | |
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
=============================================================================*/ | |
/*---------------------------------------------------------------------------- | |
*----------------------------------------------------------------------------*/ | |
module | |
compareRecFN#(parameter expWidth = 3, parameter sigWidth = 3) ( | |
input [(expWidth + sigWidth):0] a, | |
input [(expWidth + sigWidth):0] b, | |
input signaling, | |
output lt, | |
output eq, | |
output gt, | |
output unordered, | |
output [4:0] exceptionFlags | |
); | |
/*------------------------------------------------------------------------ | |
*------------------------------------------------------------------------*/ | |
wire isNaNA, isInfA, isZeroA, signA; | |
wire signed [(expWidth + 1):0] sExpA; | |
wire [sigWidth:0] sigA; | |
recFNToRawFN#(expWidth, sigWidth) | |
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA); | |
wire isSigNaNA; | |
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA); | |
wire isNaNB, isInfB, isZeroB, signB; | |
wire signed [(expWidth + 1):0] sExpB; | |
wire [sigWidth:0] sigB; | |
recFNToRawFN#(expWidth, sigWidth) | |
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB); | |
wire isSigNaNB; | |
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB); | |
/*------------------------------------------------------------------------ | |
*------------------------------------------------------------------------*/ | |
wire ordered = !isNaNA && !isNaNB; | |
wire bothInfs = isInfA && isInfB; | |
wire bothZeros = isZeroA && isZeroB; | |
wire eqExps = (sExpA == sExpB); | |
wire common_ltMags = (sExpA < sExpB) || (eqExps && (sigA < sigB)); | |
wire common_eqMags = eqExps && (sigA == sigB); | |
wire ordered_lt = | |
!bothZeros | |
&& ((signA && !signB) | |
|| (!bothInfs | |
&& ((signA && !common_ltMags && !common_eqMags) | |
|| (!signB && common_ltMags)))); | |
wire ordered_eq = | |
bothZeros || ((signA == signB) && (bothInfs || common_eqMags)); | |
/*------------------------------------------------------------------------ | |
*------------------------------------------------------------------------*/ | |
wire invalid = isSigNaNA || isSigNaNB || (signaling && !ordered); | |
assign lt = ordered && ordered_lt; | |
assign eq = ordered && ordered_eq; | |
assign gt = ordered && !ordered_lt && !ordered_eq; | |
assign unordered = !ordered; | |
assign exceptionFlags = {invalid, 4'b0}; | |
endmodule | |