Add configuration files
diff --git a/.gitignore b/.gitignore
index 04edfb0..66b3d34 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,4 @@
*.lst
*.vcd
*.gtkw
+*~
diff --git a/openlane/trainable_nn/config.json b/openlane/trainable_nn/config.json
new file mode 100644
index 0000000..20a4d6c
--- /dev/null
+++ b/openlane/trainable_nn/config.json
@@ -0,0 +1,49 @@
+{
+ "DESIGN_NAME": "trainable_nn",
+ "DESIGN_IS_CORE": 0,
+ "VERILOG_FILES": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/rtl/config.v",
+ "dir::../../verilog/rtl/macros.v",
+ "dir::../../verilog/rtl/math.v",
+ "dir::../../verilog/rtl/actfn.v",
+ "dir::../../verilog/rtl/neuron.v",
+ "dir::../../verilog/rtl/network.v",
+ "dir::../../verilog/rtl/interface.v",
+ "dir::../../verilog/rtl/trainable_nn.v"
+ ],
+ "CLOCK_PERIOD": 100,
+ "CLOCK_PORT": "wb_clk_i",
+ "CLOCK_NET": "i_nn.clk",
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 900 1200",
+ "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.25,
+ "VDD_NETS": ["vccd1"],
+ "GND_NETS": ["vssd1"],
+ "DIODE_INSERTION_STRATEGY": 4,
+ "RUN_CVC": 1,
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "RT_MAX_LAYER": "met4",
+ "scl::sky130_fd_sc_hd": {
+ },
+ "scl::sky130_fd_sc_hdll": {
+ },
+ "scl::sky130_fd_sc_hs": {
+ },
+ "scl::sky130_fd_sc_ls": {
+ "SYNTH_MAX_FANOUT": 5
+ },
+ "scl::sky130_fd_sc_ms": {
+ }
+ },
+ "pdk::gf180mcuC": {
+ "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+ "FP_CORE_UTIL": 40,
+ "RT_MAX_LAYER": "Metal4",
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+ }
+}
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/trainable_nn/pin_order.cfg
similarity index 100%
rename from openlane/user_proj_example/pin_order.cfg
rename to openlane/trainable_nn/pin_order.cfg
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
deleted file mode 100644
index 370d74c..0000000
--- a/openlane/user_proj_example/config.json
+++ /dev/null
@@ -1,45 +0,0 @@
-{
- "DESIGN_NAME": "user_proj_example",
- "DESIGN_IS_CORE": 0,
- "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "CLOCK_PERIOD": 10,
- "CLOCK_PORT": "wb_clk_i",
- "CLOCK_NET": "counter.clk",
- "FP_SIZING": "absolute",
- "DIE_AREA": "0 0 900 600",
- "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
- "PL_BASIC_PLACEMENT": 0,
- "PL_TARGET_DENSITY": 0.55,
- "VDD_NETS": ["vccd1"],
- "GND_NETS": ["vssd1"],
- "DIODE_INSERTION_STRATEGY": 4,
- "RUN_CVC": 1,
- "pdk::sky130*": {
- "FP_CORE_UTIL": 45,
- "RT_MAX_LAYER": "met4",
- "scl::sky130_fd_sc_hd": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hdll": {
- "CLOCK_PERIOD": 10
- },
- "scl::sky130_fd_sc_hs": {
- "CLOCK_PERIOD": 8
- },
- "scl::sky130_fd_sc_ls": {
- "CLOCK_PERIOD": 10,
- "SYNTH_MAX_FANOUT": 5
- },
- "scl::sky130_fd_sc_ms": {
- "CLOCK_PERIOD": 10
- }
- },
- "pdk::gf180mcuC": {
- "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
- "CLOCK_PERIOD": 24.0,
- "FP_CORE_UTIL": 40,
- "RT_MAX_LAYER": "Metal4",
- "SYNTH_MAX_FANOUT": 4,
- "PL_TARGET_DENSITY": 0.45
- }
-}
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 22a00ee..3013ccd 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,14 +1,24 @@
{
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
- "CLOCK_PERIOD": 10,
+ "CLOCK_PERIOD": 100,
"CLOCK_PORT": "user_clock2",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
- "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
- "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
- "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+ "VERILOG_FILES_BLACKBOX": [
+ "dir::../../verilog/rtl/defines.v",
+ "dir::../../verilog/rtl/config.v",
+ "dir::../../verilog/rtl/macros.v",
+ "dir::../../verilog/rtl/math.v",
+ "dir::../../verilog/rtl/actfn.v",
+ "dir::../../verilog/rtl/neuron.v",
+ "dir::../../verilog/rtl/network.v",
+ "dir::../../verilog/rtl/interface.v",
+ "dir::../../verilog/rtl/trainable_nn.v"
+ ],
+ "EXTRA_LEFS": "dir::../../lef/trainable_nn.lef",
+ "EXTRA_GDS_FILES": "dir::../../gds/trainable_nn.gds",
"FP_PDN_CHECK_NODES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..6c19166 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+mprj 910 1060 N
