| { |
| "DESIGN_NAME": "trainable_nn", |
| "DESIGN_IS_CORE": 0, |
| "VERILOG_FILES": [ |
| "dir::../../verilog/rtl/defines.v", |
| "dir::../../verilog/rtl/config.v", |
| "dir::../../verilog/rtl/macros.v", |
| "dir::../../verilog/rtl/math.v", |
| "dir::../../verilog/rtl/actfn.v", |
| "dir::../../verilog/rtl/neuron.v", |
| "dir::../../verilog/rtl/network.v", |
| "dir::../../verilog/rtl/interface.v", |
| "dir::../../verilog/rtl/trainable_nn.v" |
| ], |
| "CLOCK_PERIOD": 100, |
| "CLOCK_PORT": "wb_clk_i", |
| "CLOCK_NET": "i_nn.clk", |
| "FP_SIZING": "absolute", |
| "DIE_AREA": "0 0 900 1200", |
| "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", |
| "PL_BASIC_PLACEMENT": 0, |
| "PL_TARGET_DENSITY": 0.25, |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| "DIODE_INSERTION_STRATEGY": 4, |
| "RUN_CVC": 1, |
| "pdk::sky130*": { |
| "FP_CORE_UTIL": 45, |
| "RT_MAX_LAYER": "met4", |
| "scl::sky130_fd_sc_hd": { |
| }, |
| "scl::sky130_fd_sc_hdll": { |
| }, |
| "scl::sky130_fd_sc_hs": { |
| }, |
| "scl::sky130_fd_sc_ls": { |
| "SYNTH_MAX_FANOUT": 5 |
| }, |
| "scl::sky130_fd_sc_ms": { |
| } |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| "FP_CORE_UTIL": 40, |
| "RT_MAX_LAYER": "Metal4", |
| "SYNTH_MAX_FANOUT": 4, |
| "PL_TARGET_DENSITY": 0.45 |
| } |
| } |