added schematics
diff --git a/xschem/.user_analog_project_wrapper.sch.swp b/xschem/.user_analog_project_wrapper.sch.swp new file mode 100644 index 0000000..a3fc269 --- /dev/null +++ b/xschem/.user_analog_project_wrapper.sch.swp Binary files differ
diff --git a/xschem/.user_analog_project_wrapper.spice.swp b/xschem/.user_analog_project_wrapper.spice.swp new file mode 100644 index 0000000..e3635ee --- /dev/null +++ b/xschem/.user_analog_project_wrapper.spice.swp Binary files differ
diff --git a/xschem/.user_analog_project_wrapper.sym.swp b/xschem/.user_analog_project_wrapper.sym.swp new file mode 100644 index 0000000..d80c7f3 --- /dev/null +++ b/xschem/.user_analog_project_wrapper.sym.swp Binary files differ
diff --git a/xschem/1T1R.sch b/xschem/1T1R.sch new file mode 100755 index 0000000..54aebef --- /dev/null +++ b/xschem/1T1R.sch
@@ -0,0 +1,38 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 310 -340 310 -300 { +lab=row} +N 310 -240 310 -200 { +lab=#net1} +N 310 -170 380 -170 { +lab=body} +N 220 -170 270 -170 { +lab=WL} +N 310 -140 310 -100 { +lab=col} +C {devices/iopin.sym} 225 -170 2 0 {name=p3 lab=WL} +C {devices/iopin.sym} 375 -170 0 0 {name=p4 lab=body} +C {devices/iopin.sym} 310 -340 3 0 {name=p2 lab=row} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 290 -170 0 0 {name=M1 +L=0.5 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 310 -100 1 0 {name=p1 lab=col} +C {sky130_fd_pr/reram.sym} 310 -270 0 0 {name=R1 +model=reram_reram_cell +mult=1 +spiceprefix=X}
diff --git a/xschem/1T1R.sym b/xschem/1T1R.sym new file mode 100755 index 0000000..e71ab74 --- /dev/null +++ b/xschem/1T1R.sym
@@ -0,0 +1,24 @@ +v {xschem version=3.0.0 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=X1"} + +T {@symname} -36 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=row dir=inout } +L 7 130 -30 150 -30 {} +T {row} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=WL dir=inout } +L 7 130 -10 150 -10 {} +T {WL} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=body dir=inout } +L 7 130 10 150 10 {} +T {body} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=col dir=inout } +L 7 130 30 150 30 {} +T {col} 125 26 0 1 0.2 0.2 {}
diff --git a/xschem/1T1R_16x16.sch b/xschem/1T1R_16x16.sch new file mode 100755 index 0000000..6fffad0 --- /dev/null +++ b/xschem/1T1R_16x16.sch
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diff --git a/xschem/1T1R_16x16.sym b/xschem/1T1R_16x16.sym new file mode 100755 index 0000000..e737958 --- /dev/null +++ b/xschem/1T1R_16x16.sym
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{name=body dir=inout } +B 5 147.5 77.5 152.5 82.5 {name=WL1 dir=inout } +B 5 147.5 97.5 152.5 102.5 {name=row1 dir=inout } +B 5 147.5 117.5 152.5 122.5 {name=WL0 dir=inout } +B 5 147.5 137.5 152.5 142.5 {name=row0 dir=inout } +B 5 147.5 197.5 152.5 202.5 {name=col14 dir=inout } +B 5 147.5 177.5 152.5 182.5 {name=col15 dir=inout } +B 5 147.5 357.5 152.5 362.5 {name=col6 dir=inout } +B 5 147.5 337.5 152.5 342.5 {name=col7 dir=inout } +B 5 147.5 397.5 152.5 402.5 {name=col4 dir=inout } +B 5 147.5 257.5 152.5 262.5 {name=col11 dir=inout } +B 5 147.5 377.5 152.5 382.5 {name=col5 dir=inout } +B 5 147.5 317.5 152.5 322.5 {name=col8 dir=inout } +B 5 147.5 297.5 152.5 302.5 {name=col9 dir=inout } +B 5 147.5 437.5 152.5 442.5 {name=col2 dir=inout } +B 5 147.5 277.5 152.5 282.5 {name=col10 dir=inout } +B 5 147.5 217.5 152.5 222.5 {name=col13 dir=inout } +B 5 147.5 237.5 152.5 242.5 {name=col12 dir=inout } +B 5 147.5 417.5 152.5 422.5 {name=col3 dir=inout } +B 5 147.5 477.5 152.5 482.5 {name=col0 dir=inout } +B 5 147.5 457.5 152.5 462.5 {name=col1 dir=inout } +T {@symname} -63 -6 0 0 0.3 0.3 {} +T {@name} 135 -502 0 0 0.2 0.2 {} +T {WL15} 125 -484 0 1 0.2 0.2 {} +T {row15} 125 -464 0 1 0.2 0.2 {} +T {WL14} 125 -444 0 1 0.2 0.2 {} +T {row14} 125 -424 0 1 0.2 0.2 {} +T {WL13} 125 -404 0 1 0.2 0.2 {} +T {row13} 125 -384 0 1 0.2 0.2 {} +T {WL12} 125 -364 0 1 0.2 0.2 {} +T {row12} 125 -344 0 1 0.2 0.2 {} +T {WL11} 125 -324 0 1 0.2 0.2 {} +T {row11} 125 -304 0 1 0.2 0.2 {} +T {WL10} 125 -284 0 1 0.2 0.2 {} +T {row10} 125 -264 0 1 0.2 0.2 {} +T {WL9} 125 -244 0 1 0.2 0.2 {} +T {row9} 125 -224 0 1 0.2 0.2 {} +T {WL8} 125 -204 0 1 0.2 0.2 {} +T {row8} 125 -184 0 1 0.2 0.2 {} +T {WL7} 125 -164 0 1 0.2 0.2 {} +T {row7} 125 -144 0 1 0.2 0.2 {} +T {WL6} 125 -124 0 1 0.2 0.2 {} +T {row6} 125 -104 0 1 0.2 0.2 {} +T {WL5} 125 -84 0 1 0.2 0.2 {} +T {row5} 125 -64 0 1 0.2 0.2 {} +T {WL4} 125 -44 0 1 0.2 0.2 {} +T {row4} 125 -24 0 1 0.2 0.2 {} +T {WL3} 125 -4 0 1 0.2 0.2 {} +T {row3} 125 16 0 1 0.2 0.2 {} +T {WL2} 125 36 0 1 0.2 0.2 {} +T {row2} 125 56 0 1 0.2 0.2 {} +T {body} 125 156 0 1 0.2 0.2 {} +T {WL1} 125 76 0 1 0.2 0.2 {} +T {row1} 125 96 0 1 0.2 0.2 {} +T {WL0} 125 116 0 1 0.2 0.2 {} +T {row0} 125 136 0 1 0.2 0.2 {} +T {col14} 125 196 0 1 0.2 0.2 {} +T {col15} 125 176 0 1 0.2 0.2 {} +T {col6} 125 356 0 1 0.2 0.2 {} +T {col7} 125 336 0 1 0.2 0.2 {} +T {col4} 125 396 0 1 0.2 0.2 {} +T {col11} 125 256 0 1 0.2 0.2 {} +T {col5} 125 376 0 1 0.2 0.2 {} +T {col8} 125 316 0 1 0.2 0.2 {} +T {col9} 125 296 0 1 0.2 0.2 {} +T {col2} 125 436 0 1 0.2 0.2 {} +T {col10} 125 276 0 1 0.2 0.2 {} +T {col13} 125 216 0 1 0.2 0.2 {} +T {col12} 125 236 0 1 0.2 0.2 {} +T {col3} 125 416 0 1 0.2 0.2 {} +T {col0} 125 476 0 1 0.2 0.2 {} +T {col1} 125 456 0 1 0.2 0.2 {}
diff --git a/xschem/1T1R_2x2.sch b/xschem/1T1R_2x2.sch new file mode 100755 index 0000000..ac68870 --- /dev/null +++ b/xschem/1T1R_2x2.sch
@@ -0,0 +1,91 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 480 -220 500 -220 { +lab=col1} +N 480 -220 480 -80 { +lab=col1} +N 480 -80 500 -80 { +lab=col1} +N 460 -60 500 -60 { +lab=body} +N 460 -200 500 -200 { +lab=body} +N 50 -220 70 -220 { +lab=col0} +N 50 -220 50 -80 { +lab=col0} +N 50 -80 70 -80 { +lab=col0} +N 30 -60 70 -60 { +lab=body} +N 30 -200 30 -60 { +lab=body} +N 30 -200 70 -200 { +lab=body} +N 430 -40 500 -40 { +lab=WL0} +N 70 -40 430 -40 { +lab=WL0} +N 0 -40 70 -40 { +lab=WL0} +N 70 -20 500 -20 { +lab=row0} +N 0 -20 70 -20 { +lab=row0} +N 70 -160 500 -160 { +lab=row1} +N 10 -160 70 -160 { +lab=row1} +N 70 -180 500 -180 { +lab=WL1} +N 10 -180 70 -180 { +lab=WL1} +N 0 -160 10 -160 { +lab=row1} +N 0 -180 10 -180 { +lab=WL1} +N 0 -200 30 -200 { +lab=body} +N -40 -160 0 -160 { +lab=row1} +N -40 -180 0 -180 { +lab=WL1} +N -40 -20 0 -20 { +lab=row0} +N -40 -40 0 -40 { +lab=WL0} +N -40 -200 0 -200 { +lab=body} +N 50 0 50 40 { +lab=col0} +N 50 -80 50 0 { +lab=col0} +N 480 0 480 40 { +lab=col1} +N 480 -80 480 0 { +lab=col1} +N 70 -60 460 -60 { +lab=body} +N 70 -200 460 -200 { +lab=body} +C {/Volumes/export/isn/soumil/ReRAM_sky130_files/1T1R.sym} 650 -190 2 0 {name=X1} +C {/Volumes/export/isn/soumil/ReRAM_sky130_files/1T1R.sym} 650 -50 2 0 {name=X2} +C {/Volumes/export/isn/soumil/ReRAM_sky130_files/1T1R.sym} 220 -50 2 0 {name=X3} +C {/Volumes/export/isn/soumil/ReRAM_sky130_files/1T1R.sym} 220 -190 2 0 {name=X4} +C {devices/iopin.sym} -40 -160 2 0 {name=p1 lab=row1} +C {devices/iopin.sym} -40 -180 2 0 {name=p2 lab=WL1} +C {devices/iopin.sym} -40 -20 2 0 {name=p3 lab=row0 + +} +C {devices/iopin.sym} -40 -40 2 0 {name=p4 lab=WL0} +C {devices/iopin.sym} -40 -200 2 0 {name=p5 lab=body} +C {devices/iopin.sym} 50 40 1 0 {name=p6 lab=col0 + +} +C {devices/iopin.sym} 480 40 1 0 {name=p7 lab=col1 + +}
diff --git a/xschem/1T1R_2x2.sym b/xschem/1T1R_2x2.sym new file mode 100755 index 0000000..3c65816 --- /dev/null +++ b/xschem/1T1R_2x2.sym
@@ -0,0 +1,32 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -54 -6 0 0 0.3 0.3 {} +T {@name} 135 -82 0 0 0.2 0.2 {} +L 4 -130 -70 130 -70 {} +L 4 -130 70 130 70 {} +L 4 -130 -70 -130 70 {} +L 4 130 -70 130 70 {} +B 5 147.5 -62.5 152.5 -57.5 {name=body dir=inout } +L 7 130 -60 150 -60 {} +T {body} 125 -64 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=WL1 dir=inout } +L 7 130 -40 150 -40 {} +T {WL1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=row1 dir=inout } +L 7 130 -20 150 -20 {} +T {row1} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=WL0 dir=inout } +L 7 130 0 150 0 {} +T {WL0} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=row0 dir=inout } +L 7 130 20 150 20 {} +T {row0} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=col1 dir=inout } +L 7 130 40 150 40 {} +T {col1} 125 36 0 1 0.2 0.2 {} +B 5 147.5 57.5 152.5 62.5 {name=col0 dir=inout } +L 7 130 60 150 60 {} +T {col0} 125 56 0 1 0.2 0.2 {}
diff --git a/xschem/WL_driver.sch b/xschem/WL_driver.sch new file mode 100755 index 0000000..4b9ba39 --- /dev/null +++ b/xschem/WL_driver.sch
@@ -0,0 +1,40 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 490 -120 580 -120 { +lab=#net1} +N 490 -160 530 -160 { +lab=vccd1} +N 490 -140 530 -140 { +lab=vssd1} +N 120 -160 190 -160 { +lab=WL} +N 120 -140 190 -140 { +lab=SEL} +N 880 -60 940 -60 { +lab=WL_out} +N 880 -80 940 -80 { +lab=#net2} +N 880 -100 920 -100 { +lab=vccd1} +N 880 -120 920 -120 { +lab=vdda1} +N 880 -40 920 -40 { +lab=vssd1} +C {level_up_shifter_2x.sym} 730 -80 0 0 {name=x1} +C {and.sym} 340 -140 0 0 {name=x2} +C {devices/iopin.sym} 240 -280 2 0 {name=p53 lab=vccd1} +C {devices/iopin.sym} 240 -300 2 0 {name=p1 lab=vdda1} +C {devices/iopin.sym} 240 -260 2 0 {name=p2 lab=vssd1} +C {devices/lab_pin.sym} 530 -140 0 1 {name=l26 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 530 -160 0 1 {name=l25 sig_type=std_logic lab=vccd1} +C {devices/ipin.sym} 120 -160 2 1 {name=p3 lab=WL} +C {devices/ipin.sym} 120 -140 2 1 {name=p16 lab=SEL} +C {devices/noconn.sym} 940 -80 0 1 {name=l96} +C {devices/opin.sym} 940 -60 2 1 {name=p4 lab=WL_out} +C {devices/lab_pin.sym} 920 -100 0 1 {name=l1 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 920 -120 0 1 {name=l2 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 920 -40 0 1 {name=l3 sig_type=std_logic lab=vssd1}
diff --git a/xschem/WL_driver.sym b/xschem/WL_driver.sym new file mode 100755 index 0000000..1f764f0 --- /dev/null +++ b/xschem/WL_driver.sym
@@ -0,0 +1,30 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -58.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=vdda1 dir=inout } +L 7 130 -30 150 -30 {} +T {vdda1} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=vccd1 dir=inout } +L 7 130 -10 150 -10 {} +T {vccd1} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=vssd1 dir=inout } +L 7 130 10 150 10 {} +T {vssd1} 125 6 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=WL dir=in } +L 4 -150 -30 -130 -30 {} +T {WL} -125 -34 0 0 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=SEL dir=in } +L 4 -150 -10 -130 -10 {} +T {SEL} -125 -14 0 0 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=WL_out dir=out } +L 4 130 30 150 30 {} +T {WL_out} 125 26 0 1 0.2 0.2 {}
diff --git a/xschem/WL_drivers_16x1.sch b/xschem/WL_drivers_16x1.sch new file mode 100755 index 0000000..89ec134 --- /dev/null +++ b/xschem/WL_drivers_16x1.sch
@@ -0,0 +1,313 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 100 -70 160 -70 { +lab=SEL} +N 460 -90 520 -90 { +lab=vdda1} +N 460 -70 520 -70 { +lab=vccd1} +N 460 -50 520 -50 { +lab=vssd1} +N 460 -30 520 -30 { +lab=WL_out0} +N 100 -230 160 -230 { +lab=WL1} +N 100 -210 160 -210 { +lab=SEL} +N 460 -230 520 -230 { +lab=vdda1} +N 460 -210 520 -210 { +lab=vccd1} +N 460 -190 520 -190 { +lab=vssd1} +N 460 -170 520 -170 { +lab=WL_out1} +N 100 -380 160 -380 { +lab=WL2} +N 100 -360 160 -360 { +lab=SEL} +N 460 -380 520 -380 { +lab=vdda1} +N 460 -360 520 -360 { +lab=vccd1} +N 460 -340 520 -340 { +lab=vssd1} +N 460 -320 520 -320 { +lab=WL_out2} +N 100 -520 160 -520 { +lab=WL3} +N 100 -500 160 -500 { +lab=SEL} +N 450 -520 510 -520 { +lab=vdda1} +N 450 -500 510 -500 { +lab=vccd1} +N 450 -480 510 -480 { +lab=vssd1} +N 450 -460 510 -460 { +lab=WL_out3} +N 90 -660 150 -660 { +lab=WL4} +N 90 -640 150 -640 { +lab=SEL} +N 450 -660 510 -660 { +lab=vdda1} +N 450 -640 510 -640 { +lab=vccd1} +N 450 -620 510 -620 { +lab=vssd1} +N 450 -600 510 -600 { +lab=WL_out4} +N 90 -800 150 -800 { +lab=WL5} +N 90 -780 150 -780 { +lab=SEL} +N 450 -800 510 -800 { +lab=vdda1} +N 450 -780 510 -780 { +lab=vccd1} +N 450 -760 510 -760 { +lab=vssd1} +N 450 -740 510 -740 { +lab=WL_out5} +N 90 -950 150 -950 { +lab=WL6} +N 90 -930 150 -930 { +lab=SEL} +N 450 -950 510 -950 { +lab=vdda1} +N 450 -930 510 -930 { +lab=vccd1} +N 450 -910 510 -910 { +lab=vssd1} +N 450 -890 510 -890 { +lab=WL_out6} +N 90 -1090 150 -1090 { +lab=WL7} +N 90 -1070 150 -1070 { +lab=SEL} +N 450 -1090 510 -1090 { +lab=vdda1} +N 450 -1070 510 -1070 { +lab=vccd1} +N 450 -1050 510 -1050 { +lab=vssd1} +N 450 -1030 510 -1030 { +lab=WL_out7} +N 90 -1230 150 -1230 { +lab=WL8} +N 90 -1210 150 -1210 { +lab=SEL} +N 450 -1230 510 -1230 { +lab=vdda1} +N 450 -1210 510 -1210 { +lab=vccd1} +N 450 -1190 510 -1190 { +lab=vssd1} +N 450 -1170 510 -1170 { +lab=WL_out8} +N 90 -1370 150 -1370 { +lab=WL9} +N 90 -1350 150 -1350 { +lab=SEL} +N 450 -1370 510 -1370 { +lab=vdda1} +N 450 -1350 510 -1350 { +lab=vccd1} +N 450 -1330 510 -1330 { +lab=vssd1} +N 450 -1310 510 -1310 { +lab=WL_out9} +N 90 -1520 150 -1520 { +lab=WL10} +N 90 -1500 150 -1500 { +lab=SEL} +N 450 -1520 510 -1520 { +lab=vdda1} +N 450 -1500 510 -1500 { +lab=vccd1} +N 450 -1480 510 -1480 { +lab=vssd1} +N 450 -1460 510 -1460 { +lab=WL_out10} +N 90 -1660 150 -1660 { +lab=WL11} +N 90 -1640 150 -1640 { +lab=SEL} +N 450 -1660 510 -1660 { +lab=vdda1} +N 450 -1640 510 -1640 { +lab=vccd1} +N 450 -1620 510 -1620 { +lab=vssd1} +N 450 -1600 510 -1600 { +lab=WL_out11} +N 80 -1800 140 -1800 { +lab=WL12} +N 80 -1780 140 -1780 { +lab=SEL} +N 440 -1800 500 -1800 { +lab=vdda1} +N 440 -1780 500 -1780 { +lab=vccd1} +N 440 -1760 500 -1760 { +lab=vssd1} +N 440 -1740 500 -1740 { +lab=WL_out12} +N 80 -1940 140 -1940 { +lab=WL13} +N 80 -1920 140 -1920 { +lab=SEL} +N 440 -1940 500 -1940 { +lab=vdda1} +N 440 -1920 500 -1920 { +lab=vccd1} +N 440 -1900 500 -1900 { +lab=vssd1} +N 440 -1880 500 -1880 { +lab=WL_out13} +N 80 -2090 140 -2090 { +lab=WL14} +N 80 -2070 140 -2070 { +lab=SEL} +N 440 -2090 500 -2090 { +lab=vdda1} +N 440 -2070 500 -2070 { +lab=vccd1} +N 440 -2050 500 -2050 { +lab=vssd1} +N 440 -2030 500 -2030 { +lab=WL_out14} +N 80 -2230 140 -2230 { +lab=WL15} +N 80 -2210 140 -2210 { +lab=SEL} +N 440 -2230 500 -2230 { +lab=vdda1} +N 440 -2210 500 -2210 { +lab=vccd1} +N 440 -2190 500 -2190 { +lab=vssd1} +N 440 -2170 500 -2170 { +lab=WL_out15} +N 100 -90 160 -90 { +lab=WL0} +C {WL_driver.sym} 310 -60 0 0 {name=x1} +C {devices/ipin.sym} 100 -90 2 1 {name=p49 lab=WL0} +C {devices/ipin.sym} 100 -70 2 1 {name=p1 lab=SEL} +C {devices/lab_pin.sym} 520 -50 0 1 {name=l50 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 520 -90 0 1 {name=l51 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 520 -70 0 1 {name=l1 sig_type=std_logic lab=vccd1} +C {devices/iopin.sym} 90 -2400 2 0 {name=p2 lab=vdda1} +C {devices/iopin.sym} 90 -2380 2 0 {name=p3 lab=vccd1} +C {devices/iopin.sym} 90 -2360 2 0 {name=p4 lab=vssd1} +C {devices/opin.sym} 520 -30 2 1 {name=p5 lab=WL_out0} +C {WL_driver.sym} 310 -200 0 0 {name=x2} +C {WL_driver.sym} 310 -350 0 0 {name=x3} +C {WL_driver.sym} 310 -490 0 0 {name=x4} +C {WL_driver.sym} 300 -630 0 0 {name=x5} +C {WL_driver.sym} 300 -770 0 0 {name=x6} +C {WL_driver.sym} 300 -920 0 0 {name=x7} +C {WL_driver.sym} 300 -1060 0 0 {name=x8} +C {WL_driver.sym} 300 -1200 0 0 {name=x9} +C {WL_driver.sym} 300 -1340 0 0 {name=x10} +C {WL_driver.sym} 300 -1490 0 0 {name=x11} +C {WL_driver.sym} 300 -1630 0 0 {name=x12} +C {WL_driver.sym} 290 -1770 0 0 {name=x13} +C {WL_driver.sym} 290 -1910 0 0 {name=x14} +C {WL_driver.sym} 290 -2060 0 0 {name=x15} +C {WL_driver.sym} 290 -2200 0 0 {name=x16} +C {devices/lab_pin.sym} 520 -190 0 1 {name=l2 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 520 -230 0 1 {name=l3 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 520 -210 0 1 {name=l4 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 520 -170 2 1 {name=p8 lab=WL_out1} +C {devices/ipin.sym} 100 -380 2 1 {name=p9 lab=WL2} +C {devices/lab_pin.sym} 520 -340 0 1 {name=l5 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 520 -380 0 1 {name=l6 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 520 -360 0 1 {name=l7 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 520 -320 2 1 {name=p11 lab=WL_out2} +C {devices/lab_pin.sym} 100 -360 0 0 {name=l8 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 100 -210 0 0 {name=l9 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 100 -230 2 1 {name=p6 lab=WL1} +C {devices/lab_pin.sym} 510 -480 0 1 {name=l10 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -520 0 1 {name=l11 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -500 0 1 {name=l12 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -460 2 1 {name=p7 lab=WL_out3} +C {devices/ipin.sym} 90 -660 2 1 {name=p10 lab=WL4} +C {devices/lab_pin.sym} 510 -620 0 1 {name=l13 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -660 0 1 {name=l14 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -640 0 1 {name=l15 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -600 2 1 {name=p12 lab=WL_out4} +C {devices/lab_pin.sym} 90 -640 0 0 {name=l16 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 100 -500 0 0 {name=l17 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 100 -520 2 1 {name=p13 lab=WL3} +C {devices/ipin.sym} 90 -800 2 1 {name=p14 lab=WL5} +C {devices/lab_pin.sym} 510 -760 0 1 {name=l18 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -800 0 1 {name=l19 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -780 0 1 {name=l20 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -740 2 1 {name=p15 lab=WL_out5} +C {devices/lab_pin.sym} 90 -780 0 0 {name=l21 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -950 2 1 {name=p16 lab=WL6} +C {devices/lab_pin.sym} 510 -910 0 1 {name=l22 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -950 0 1 {name=l23 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -930 0 1 {name=l24 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -890 2 1 {name=p17 lab=WL_out6} +C {devices/lab_pin.sym} 90 -930 0 0 {name=l25 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -1090 2 1 {name=p18 lab=WL7} +C {devices/lab_pin.sym} 510 -1050 0 1 {name=l26 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -1090 0 1 {name=l27 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -1070 0 1 {name=l28 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -1030 2 1 {name=p19 lab=WL_out7} +C {devices/lab_pin.sym} 90 -1070 0 0 {name=l29 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -1230 2 1 {name=p20 lab=WL8} +C {devices/lab_pin.sym} 510 -1190 0 1 {name=l30 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -1230 0 1 {name=l31 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -1210 0 1 {name=l32 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -1170 2 1 {name=p21 lab=WL_out8} +C {devices/lab_pin.sym} 90 -1210 0 0 {name=l33 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -1370 2 1 {name=p22 lab=WL9} +C {devices/lab_pin.sym} 510 -1330 0 1 {name=l34 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -1370 0 1 {name=l35 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -1350 0 1 {name=l36 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -1310 2 1 {name=p23 lab=WL_out9} +C {devices/lab_pin.sym} 90 -1350 0 0 {name=l37 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -1520 2 1 {name=p24 lab=WL10} +C {devices/lab_pin.sym} 510 -1480 0 1 {name=l38 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -1520 0 1 {name=l39 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -1500 0 1 {name=l40 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -1460 2 1 {name=p25 lab=WL_out10} +C {devices/lab_pin.sym} 90 -1500 0 0 {name=l41 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 90 -1660 2 1 {name=p26 lab=WL11} +C {devices/lab_pin.sym} 510 -1620 0 1 {name=l42 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 510 -1660 0 1 {name=l43 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 510 -1640 0 1 {name=l44 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 510 -1600 2 1 {name=p27 lab=WL_out11} +C {devices/lab_pin.sym} 90 -1640 0 0 {name=l45 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 80 -1800 2 1 {name=p28 lab=WL12} +C {devices/lab_pin.sym} 500 -1760 0 1 {name=l46 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 500 -1800 0 1 {name=l47 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 500 -1780 0 1 {name=l48 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 500 -1740 2 1 {name=p29 lab=WL_out12} +C {devices/lab_pin.sym} 80 -1780 0 0 {name=l49 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 80 -1940 2 1 {name=p30 lab=WL13} +C {devices/lab_pin.sym} 500 -1900 0 1 {name=l52 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 500 -1940 0 1 {name=l53 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 500 -1920 0 1 {name=l54 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 500 -1880 2 1 {name=p31 lab=WL_out13} +C {devices/lab_pin.sym} 80 -1920 0 0 {name=l55 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 80 -2090 2 1 {name=p32 lab=WL14} +C {devices/lab_pin.sym} 500 -2050 0 1 {name=l56 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 500 -2090 0 1 {name=l57 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 500 -2070 0 1 {name=l58 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 500 -2030 2 1 {name=p33 lab=WL_out14} +C {devices/lab_pin.sym} 80 -2070 0 0 {name=l59 sig_type=std_logic lab=SEL} +C {devices/ipin.sym} 80 -2230 2 1 {name=p34 lab=WL15} +C {devices/lab_pin.sym} 500 -2190 0 1 {name=l60 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 500 -2230 0 1 {name=l61 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 500 -2210 0 1 {name=l62 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 500 -2170 2 1 {name=p35 lab=WL_out15} +C {devices/lab_pin.sym} 80 -2210 0 0 {name=l63 sig_type=std_logic lab=SEL}
diff --git a/xschem/WL_drivers_16x1.sym b/xschem/WL_drivers_16x1.sym new file mode 100755 index 0000000..65039a3 --- /dev/null +++ b/xschem/WL_drivers_16x1.sym
@@ -0,0 +1,120 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -85.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -202 0 0 0.2 0.2 {} +L 4 -130 -190 130 -190 {} +L 4 -130 190 130 190 {} +L 4 -130 -190 -130 190 {} +L 4 130 -190 130 190 {} +B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout } +L 7 130 -180 150 -180 {} +T {vdda1} 125 -184 0 1 0.2 0.2 {} +B 5 147.5 -162.5 152.5 -157.5 {name=vccd1 dir=inout } +L 7 130 -160 150 -160 {} +T {vccd1} 125 -164 0 1 0.2 0.2 {} +B 5 147.5 -142.5 152.5 -137.5 {name=vssd1 dir=inout } +L 7 130 -140 150 -140 {} +T {vssd1} 125 -144 0 1 0.2 0.2 {} +B 5 -152.5 -182.5 -147.5 -177.5 {name=WL15 dir=in } +L 4 -150 -180 -130 -180 {} +T {WL15} -125 -184 0 0 0.2 0.2 {} +B 5 147.5 -122.5 152.5 -117.5 {name=WL_out15 dir=out } +L 4 130 -120 150 -120 {} +T {WL_out15} 125 -124 0 1 0.2 0.2 {} +B 5 -152.5 -162.5 -147.5 -157.5 {name=WL14 dir=in } +L 4 -150 -160 -130 -160 {} +T {WL14} -125 -164 0 0 0.2 0.2 {} +B 5 147.5 -102.5 152.5 -97.5 {name=WL_out14 dir=out } +L 4 130 -100 150 -100 {} +T {WL_out14} 125 -104 0 1 0.2 0.2 {} +B 5 -152.5 -142.5 -147.5 -137.5 {name=WL13 dir=in } +L 4 -150 -140 -130 -140 {} +T {WL13} -125 -144 0 0 0.2 0.2 {} +B 5 147.5 -82.5 152.5 -77.5 {name=WL_out13 dir=out } +L 4 130 -80 150 -80 {} +T {WL_out13} 125 -84 0 1 0.2 0.2 {} +B 5 -152.5 -122.5 -147.5 -117.5 {name=WL12 dir=in } +L 4 -150 -120 -130 -120 {} +T {WL12} -125 -124 0 0 0.2 0.2 {} +B 5 147.5 -62.5 152.5 -57.5 {name=WL_out12 dir=out } +L 4 130 -60 150 -60 {} +T {WL_out12} 125 -64 0 1 0.2 0.2 {} +B 5 -152.5 -102.5 -147.5 -97.5 {name=WL11 dir=in } +L 4 -150 -100 -130 -100 {} +T {WL11} -125 -104 0 0 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=WL_out11 dir=out } +L 4 130 -40 150 -40 {} +T {WL_out11} 125 -44 0 1 0.2 0.2 {} +B 5 -152.5 -82.5 -147.5 -77.5 {name=WL10 dir=in } +L 4 -150 -80 -130 -80 {} +T {WL10} -125 -84 0 0 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=WL_out10 dir=out } +L 4 130 -20 150 -20 {} +T {WL_out10} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -62.5 -147.5 -57.5 {name=WL9 dir=in } +L 4 -150 -60 -130 -60 {} +T {WL9} -125 -64 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=WL_out9 dir=out } +L 4 130 0 150 0 {} +T {WL_out9} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=WL8 dir=in } +L 4 -150 -40 -130 -40 {} +T {WL8} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=WL_out8 dir=out } +L 4 130 20 150 20 {} +T {WL_out8} 125 16 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=WL7 dir=in } +L 4 -150 -20 -130 -20 {} +T {WL7} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=WL_out7 dir=out } +L 4 130 40 150 40 {} +T {WL_out7} 125 36 0 1 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=WL6 dir=in } +L 4 -150 0 -130 0 {} +T {WL6} -125 -4 0 0 0.2 0.2 {} +B 5 147.5 57.5 152.5 62.5 {name=WL_out6 dir=out } +L 4 130 60 150 60 {} +T {WL_out6} 125 56 0 1 0.2 0.2 {} +B 5 -152.5 17.5 -147.5 22.5 {name=WL5 dir=in } +L 4 -150 20 -130 20 {} +T {WL5} -125 16 0 0 0.2 0.2 {} +B 5 147.5 77.5 152.5 82.5 {name=WL_out5 dir=out } +L 4 130 80 150 80 {} +T {WL_out5} 125 76 0 1 0.2 0.2 {} +B 5 -152.5 37.5 -147.5 42.5 {name=WL4 dir=in } +L 4 -150 40 -130 40 {} +T {WL4} -125 36 0 0 0.2 0.2 {} +B 5 147.5 97.5 152.5 102.5 {name=WL_out4 dir=out } +L 4 130 100 150 100 {} +T {WL_out4} 125 96 0 1 0.2 0.2 {} +B 5 -152.5 57.5 -147.5 62.5 {name=WL3 dir=in } +L 4 -150 60 -130 60 {} +T {WL3} -125 56 0 0 0.2 0.2 {} +B 5 147.5 117.5 152.5 122.5 {name=WL_out3 dir=out } +L 4 130 120 150 120 {} +T {WL_out3} 125 116 0 1 0.2 0.2 {} +B 5 -152.5 77.5 -147.5 82.5 {name=WL2 dir=in } +L 4 -150 80 -130 80 {} +T {WL2} -125 76 0 0 0.2 0.2 {} +B 5 147.5 137.5 152.5 142.5 {name=WL_out2 dir=out } +L 4 130 140 150 140 {} +T {WL_out2} 125 136 0 1 0.2 0.2 {} +B 5 -152.5 97.5 -147.5 102.5 {name=WL1 dir=in } +L 4 -150 100 -130 100 {} +T {WL1} -125 96 0 0 0.2 0.2 {} +B 5 147.5 157.5 152.5 162.5 {name=WL_out1 dir=out } +L 4 130 160 150 160 {} +T {WL_out1} 125 156 0 1 0.2 0.2 {} +B 5 -152.5 117.5 -147.5 122.5 {name=WL0 dir=in } +L 4 -150 120 -130 120 {} +T {WL0} -125 116 0 0 0.2 0.2 {} +B 5 -152.5 137.5 -147.5 142.5 {name=SEL dir=in } +L 4 -150 140 -130 140 {} +T {SEL} -125 136 0 0 0.2 0.2 {} +B 5 147.5 177.5 152.5 182.5 {name=WL_out0 dir=out } +L 4 130 180 150 180 {} +T {WL_out0} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch deleted file mode 100644 index d9b605c..0000000 --- a/xschem/analog_wrapper_tb.sch +++ /dev/null
@@ -1,76 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -N 300 -290 510 -290 { lab=#net1} -N 590 -290 590 -250 { lab=#net1} -N 300 -250 430 -250 { lab=GND} -N 510 -250 510 -150 { lab=GND} -N 510 -150 780 -150 { lab=GND} -N 780 -190 780 -150 { lab=GND} -N 690 -190 690 -150 { lab=GND} -N 590 -190 590 -150 { lab=GND} -N 300 -210 400 -210 { lab=#net2} -N 480 -270 480 -210 { lab=#net2} -N 480 -270 690 -270 { lab=#net2} -N 690 -270 690 -250 { lab=#net2} -N 300 10 450 10 { lab=#net3} -N 850 -270 850 0 { lab=io_analog[4]} -N 780 -270 850 -270 { lab=io_analog[4]} -N 780 -270 780 -250 { lab=io_analog[4]} -N 300 30 470 30 { lab=#net4} -N 300 50 410 50 { lab=#net5} -N 530 10 660 10 { lab=io_analog[10:0]} -N 510 -290 590 -290 { lab=#net1} -N 430 -250 510 -250 { lab=GND} -N 400 -210 480 -210 { lab=#net2} -N 460 10 530 10 { lab=io_analog[10:0]} -N 670 0 850 -0 { lab=io_analog[4]} -N 300 -270 400 -270 { lab=#net8} -N 300 -230 400 -230 { lab=#net9} -N 300 -190 400 -190 { lab=#net10} -N 300 -190 400 -190 { lab=#net10} -N 300 -170 400 -170 { lab=#net11} -N 290 -150 390 -150 { lab=#net12} -N 290 -130 390 -130 { lab=#net13} -N 290 -110 390 -110 { lab=#net14} -N 300 -90 400 -90 { lab=#net15} -N 300 -10 400 -10 { lab=#net16} -N 300 70 400 70 { lab=#net17} -N -60 -290 -0 -290 { lab=#net18} -N -60 -270 0 -270 { lab=#net19} -N -60 -250 0 -250 { lab=#net20} -N -60 -230 0 -230 { lab=#net21} -N -60 -210 0 -210 { lab=#net22} -N -60 -210 0 -210 { lab=#net22} -N -60 -190 0 -190 { lab=#net23} -N -60 -190 0 -190 { lab=#net23} -N -60 -170 0 -170 { lab=#net24} -N -60 -150 0 -150 { lab=#net25} -N -60 -130 0 -130 { lab=#net26} -N -60 -110 0 -110 { lab=#net27} -N -60 -90 0 -90 { lab=#net28} -N -60 -70 0 -70 { lab=#net29} -N -60 -50 0 -50 { lab=#net30} -N 300 -70 400 -70 {} -N 300 -50 400 -50 {} -N 300 -30 400 -30 {} -C {user_analog_project_wrapper.sym} 150 -110 0 0 {name=x1} -C {devices/vsource.sym} 590 -220 0 0 {name=V1 value="PWL(0.0 0 400u 0 5.4m 3.3)"} -C {devices/vsource.sym} 690 -220 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3 1.8)"} -C {devices/vsource.sym} 780 -220 0 0 {name=V3 value="PWL(0.0 0 100u 0 5m 3.3)"} -C {devices/bus_connect.sym} 660 10 1 1 {name=l1 lab=io_analog[4]} -C {devices/gnd.sym} 730 -150 0 0 {name=l2 lab=GND} -C {devices/lab_pin.sym} 570 10 0 0 {name=l12 sig_type=std_logic lab=io_analog[10:0]} -C {devices/code.sym} 920 -130 0 0 {name=TT_MODELS only_toplevel=false -format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt -.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"} -C {devices/code_shown.sym} 1100 -130 0 0 {name=s1 -only_toplevel=false -value=".control -tran 10u 20m -plot V(\\"io_out[11]\\") V(\\"io_out[12]\\") V(\\"io_out[15]\\") V(\\"io_out[16]\\") -+ V(\\"gpio_analog[3]\\") V(\\"gpio_analog[7]\\") -.endc"}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice deleted file mode 100644 index 523a509..0000000 --- a/xschem/analog_wrapper_tb.spice +++ /dev/null
@@ -1,283 +0,0 @@ -**.subckt analog_wrapper_tb -x1 net1 net6 GND net7 net2 net8 net9 net10 net16 net17 net18 net19 net20 net21[3] net21[2] net21[1] -+ net21[0] net22[31] net22[30] net22[29] net22[28] net22[27] net22[26] net22[25] net22[24] net22[23] net22[22] -+ net22[21] net22[20] net22[19] net22[18] net22[17] net22[16] net22[15] net22[14] net22[13] net22[12] net22[11] -+ net22[10] net22[9] net22[8] net22[7] net22[6] net22[5] net22[4] net22[3] net22[2] net22[1] net22[0] net23[31] -+ net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22] net23[21] net23[20] -+ net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11] net23[10] net23[9] -+ net23[8] net23[7] net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net11 net12[31] net12[30] -+ net12[29] net12[28] net12[27] net12[26] net12[25] net12[24] net12[23] net12[22] net12[21] net12[20] net12[19] -+ net12[18] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10] net12[9] net12[8] -+ net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net24[127] net24[126] net24[125] -+ net24[124] net24[123] net24[122] net24[121] net24[120] net24[119] net24[118] net24[117] net24[116] net24[115] -+ net24[114] net24[113] net24[112] net24[111] net24[110] net24[109] net24[108] net24[107] net24[106] net24[105] -+ net24[104] net24[103] net24[102] net24[101] net24[100] net24[99] net24[98] net24[97] net24[96] net24[95] -+ net24[94] net24[93] net24[92] net24[91] net24[90] net24[89] net24[88] net24[87] net24[86] net24[85] net24[84] -+ net24[83] net24[82] net24[81] net24[80] net24[79] net24[78] net24[77] net24[76] net24[75] net24[74] net24[73] -+ net24[72] net24[71] net24[70] net24[69] net24[68] net24[67] net24[66] net24[65] net24[64] net24[63] net24[62] -+ net24[61] net24[60] net24[59] net24[58] net24[57] net24[56] net24[55] net24[54] net24[53] net24[52] net24[51] -+ net24[50] net24[49] net24[48] net24[47] net24[46] net24[45] net24[44] net24[43] net24[42] net24[41] net24[40] -+ net24[39] net24[38] net24[37] net24[36] net24[35] net24[34] net24[33] net24[32] net24[31] net24[30] net24[29] -+ net24[28] net24[27] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20] net24[19] net24[18] -+ net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9] net24[8] net24[7] -+ net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net13[127] net13[126] net13[125] net13[124] -+ net13[123] net13[122] net13[121] net13[120] net13[119] net13[118] net13[117] net13[116] net13[115] net13[114] -+ net13[113] net13[112] net13[111] net13[110] net13[109] net13[108] net13[107] net13[106] net13[105] net13[104] -+ net13[103] net13[102] net13[101] net13[100] net13[99] net13[98] net13[97] net13[96] net13[95] net13[94] -+ net13[93] net13[92] net13[91] net13[90] net13[89] net13[88] net13[87] net13[86] net13[85] net13[84] net13[83] -+ net13[82] net13[81] net13[80] net13[79] net13[78] net13[77] net13[76] net13[75] net13[74] net13[73] net13[72] -+ net13[71] net13[70] net13[69] net13[68] net13[67] net13[66] net13[65] net13[64] net13[63] net13[62] net13[61] -+ net13[60] net13[59] net13[58] net13[57] net13[56] net13[55] net13[54] net13[53] net13[52] net13[51] net13[50] -+ net13[49] net13[48] net13[47] net13[46] net13[45] net13[44] net13[43] net13[42] net13[41] net13[40] net13[39] -+ net13[38] net13[37] net13[36] net13[35] net13[34] net13[33] net13[32] net13[31] net13[30] net13[29] net13[28] -+ net13[27] net13[26] net13[25] net13[24] net13[23] net13[22] net13[21] net13[20] net13[19] net13[18] net13[17] -+ net13[16] net13[15] net13[14] net13[13] net13[12] net13[11] net13[10] net13[9] net13[8] net13[7] net13[6] -+ net13[5] net13[4] net13[3] net13[2] net13[1] net13[0] net25[127] net25[126] net25[125] net25[124] net25[123] -+ net25[122] net25[121] net25[120] net25[119] net25[118] net25[117] net25[116] net25[115] net25[114] net25[113] -+ net25[112] net25[111] net25[110] net25[109] net25[108] net25[107] net25[106] net25[105] net25[104] net25[103] -+ net25[102] net25[101] net25[100] net25[99] net25[98] net25[97] net25[96] net25[95] net25[94] net25[93] -+ net25[92] net25[91] net25[90] net25[89] net25[88] net25[87] net25[86] net25[85] net25[84] net25[83] net25[82] -+ net25[81] net25[80] net25[79] net25[78] net25[77] net25[76] net25[75] net25[74] net25[73] net25[72] net25[71] -+ net25[70] net25[69] net25[68] net25[67] net25[66] net25[65] net25[64] net25[63] net25[62] net25[61] net25[60] -+ net25[59] net25[58] net25[57] net25[56] net25[55] net25[54] net25[53] net25[52] net25[51] net25[50] net25[49] -+ net25[48] net25[47] net25[46] net25[45] net25[44] net25[43] net25[42] net25[41] net25[40] net25[39] net25[38] -+ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27] -+ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16] -+ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5] -+ net25[4] net25[3] net25[2] net25[1] net25[0] net26[26] net26[25] net26[24] net26[23] net26[22] net26[21] -+ net26[20] net26[19] net26[18] net26[17] net26[16] net26[15] net26[14] net26[13] net26[12] net26[11] net26[10] -+ net26[9] net26[8] net26[7] net26[6] net26[5] net26[4] net26[3] net26[2] net26[1] net26[0] net27[26] -+ net27[25] net27[24] net27[23] net27[22] net27[21] net27[20] net27[19] net27[18] net27[17] net27[16] net27[15] -+ net27[14] net27[13] net27[12] net27[11] net27[10] net27[9] net27[8] net27[7] net27[6] net27[5] net27[4] -+ net27[3] net27[2] net27[1] net27[0] net29[26] net29[25] net29[24] net29[23] net29[22] net29[21] net29[20] -+ net29[19] net29[18] net29[17] net29[16] net29[15] net29[14] net29[13] net29[12] net29[11] net29[10] net29[9] -+ net29[8] net29[7] net29[6] net29[5] net29[4] net29[3] net29[2] net29[1] net29[0] net30[26] net30[25] -+ net30[24] net30[23] net30[22] net30[21] net30[20] net30[19] net30[18] net30[17] net30[16] net30[15] net30[14] -+ net30[13] net30[12] net30[11] net30[10] net30[9] net30[8] net30[7] net30[6] net30[5] net30[4] net30[3] -+ net30[2] net30[1] net30[0] net31[17] net31[16] net31[15] net31[14] net31[13] net31[12] net31[11] net31[10] -+ net31[9] net31[8] net31[7] net31[6] net31[5] net31[4] net31[3] net31[2] net31[1] net31[0] net14[17] -+ net14[16] net14[15] net14[14] net14[13] net14[12] net14[11] net14[10] net14[9] net14[8] net14[7] net14[6] -+ net14[5] net14[4] net14[3] net14[2] net14[1] net14[0] net3[10] net3[9] net3[8] net3[7] net3[6] net3[5] -+ net3[4] net3[3] net3[2] net3[1] net3[0] net4[2] net4[1] net4[0] net5[2] net5[1] net5[0] net28 net15[2] -+ net15[1] net15[0] user_analog_project_wrapper -V1 net1 GND PWL(0.0 0 400u 0 5.4m 3.3) -V2 net2 GND PWL(0.0 0 300u 0 5.3 1.8) -V3 io_analog[4] GND PWL(0.0 0 100u 0 5m 3.3) -**** begin user architecture code -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 10u 20m -plot V("io_out[11]") V("io_out[12]") V("io_out[15]") V("io_out[16]") V("gpio_analog[3]") -+ V("gpio_analog[7]") -.endc - -**** end user architecture code -**.ends - -* expanding symbol: user_analog_project_wrapper.sym # of pins=32 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch -.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i -+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31] -+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23] -+ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15] -+ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7] -+ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31] -+ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23] -+ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15] -+ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7] -+ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o -+ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24] -+ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16] -+ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8] -+ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0] -+ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121] -+ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114] -+ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107] -+ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100] -+ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93] -+ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86] -+ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79] -+ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72] -+ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65] -+ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58] -+ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51] -+ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44] -+ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37] -+ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30] -+ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23] -+ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16] -+ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9] -+ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1] -+ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123] -+ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117] -+ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111] -+ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105] -+ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98] -+ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91] -+ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84] -+ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77] -+ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70] -+ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63] -+ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56] -+ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49] -+ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42] -+ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35] -+ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28] -+ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21] -+ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14] -+ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7] -+ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] -+ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] -+ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] -+ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] -+ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] -+ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] -+ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] -+ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] -+ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] -+ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] -+ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] -+ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] -+ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] -+ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] -+ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] -+ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22] -+ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11] -+ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0] -+ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] -+ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] -+ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] -+ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21] -+ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11] -+ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] -+ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] -+ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] -+ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] -+ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] -+ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] -+ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] -+ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] -+ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] -+ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] -+ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2 -+ user_irq[2] user_irq[1] user_irq[0] -*.iopin vdda1 -*.iopin vdda2 -*.iopin vssa1 -*.iopin vssa2 -*.iopin vccd1 -*.iopin vccd2 -*.iopin vssd1 -*.iopin vssd2 -*.ipin wb_clk_i -*.ipin wb_rst_i -*.ipin wbs_stb_i -*.ipin wbs_cyc_i -*.ipin wbs_we_i -*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0] -*.ipin -*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0] -*.ipin -*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] -*.opin wbs_ack_o -*.opin -*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0] -*.ipin -*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0] -*.opin -*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0] -*.ipin -*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0] -*.ipin -*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] -*.ipin user_clock2 -*.opin -*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0] -*.opin -*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0] -*.iopin -*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0] -*.iopin -*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0] -*.iopin -*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] -*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] -*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0] -*.opin user_irq[2],user_irq[1],user_irq[0] -*.ipin -*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0] -x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por -x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por -R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=11 L=0.25 m=1 -R8 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=0.56 L=0.49 m=1 -R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=0.56 L=0.31 m=1 -R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=0.56 L=0.58 m=1 -R12 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=0.56 L=0.6 m=1 -.ends - - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end
diff --git a/xschem/and.sch b/xschem/and.sch new file mode 100755 index 0000000..823a96b --- /dev/null +++ b/xschem/and.sch
@@ -0,0 +1,167 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 200 -190 200 -160 { +lab=#net1} +N 130 -360 130 -330 { +lab=vccd1} +N 130 -390 130 -360 { +lab=vccd1} +N 50 -330 90 -330 { +lab=A} +N 290 -360 290 -330 { +lab=vccd1} +N 290 -390 290 -360 { +lab=vccd1} +N 330 -330 370 -330 { +lab=B} +N 180 -270 290 -270 { +lab=#net2} +N 290 -300 290 -270 { +lab=#net2} +N 130 -390 290 -390 { +lab=vccd1} +N 130 -270 180 -270 { +lab=#net2} +N 130 -300 130 -270 { +lab=#net2} +N 200 -220 270 -220 { +lab=VSUBS} +N 200 -130 200 -100 { +lab=VSUBS} +N 200 -100 200 -70 { +lab=VSUBS} +N 110 -130 160 -130 { +lab=B} +N 110 -220 160 -220 { +lab=A} +N 200 -270 200 -250 { +lab=#net2} +N 200 -260 440 -260 { +lab=#net2} +N 490 -290 490 -240 { +lab=OUT} +N 490 -350 490 -320 { +lab=vccd1} +N 490 -210 490 -180 { +lab=#net3} +N 490 -180 490 -140 { +lab=#net3} +N 450 -320 450 -210 { +lab=#net2} +N 440 -260 450 -260 { +lab=#net2} +N 490 -400 490 -350 { +lab=vccd1} +N 490 -260 570 -260 { +lab=OUT} +C {sky130_fd_pr/nfet_01v8.sym} 180 -220 0 0 {name=M24 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 110 -330 0 0 {name=M22 +L=0.15 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 310 -330 0 1 {name=M1 +L=0.15 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {devices/lab_pin.sym} 210 -390 1 0 {name=l6 sig_type=std_logic lab=vccd1 +} +C {devices/lab_pin.sym} 270 -220 2 0 {name=l1 sig_type=std_logic lab=VSUBS +} +C {sky130_fd_pr/nfet_01v8.sym} 180 -130 0 0 {name=M2 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {devices/lab_pin.sym} 200 -70 3 0 {name=l2 sig_type=std_logic lab=VSUBS +} +C {devices/lab_pin.sym} 50 -330 0 0 {name=l3 sig_type=std_logic lab=A +} +C {devices/lab_pin.sym} 370 -330 0 1 {name=l4 sig_type=std_logic lab=B +} +C {devices/lab_pin.sym} 110 -220 0 0 {name=l5 sig_type=std_logic lab=A +} +C {devices/lab_pin.sym} 110 -130 0 0 {name=l7 sig_type=std_logic lab=B +} +C {sky130_fd_pr/nfet_01v8.sym} 470 -210 0 0 {name=M3 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 470 -320 0 0 {name=M4 +L=0.15 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {devices/lab_pin.sym} 490 -400 1 0 {name=l8 sig_type=std_logic lab=vccd1 +} +C {devices/ipin.sym} 80 -520 0 0 {name=p1 lab=A} +C {devices/ipin.sym} 80 -500 0 0 {name=p2 lab=B} +C {devices/iopin.sym} 80 -580 2 0 {name=p3 lab=vccd1} +C {devices/iopin.sym} 80 -560 2 0 {name=p4 lab=VSUBS} +C {devices/opin.sym} 570 -260 0 0 {name=p5 lab=OUT} +C {devices/lab_pin.sym} 490 -140 3 0 {name=l9 sig_type=std_logic lab=VSUBS +}
diff --git a/xschem/and.sym b/xschem/and.sym new file mode 100755 index 0000000..6697483 --- /dev/null +++ b/xschem/and.sym
@@ -0,0 +1,27 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -31.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +B 5 147.5 -22.5 152.5 -17.5 {name=vccd1 dir=inout } +L 7 130 -20 150 -20 {} +T {vccd1} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=VSUBS dir=inout } +L 7 130 0 150 0 {} +T {VSUBS} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=A dir=in } +L 4 -150 -20 -130 -20 {} +T {A} -125 -24 0 0 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=B dir=in } +L 4 -150 0 -130 0 {} +T {B} -125 -4 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=OUT dir=out } +L 4 130 20 150 20 {} +T {OUT} 125 16 0 1 0.2 0.2 {}
diff --git a/xschem/and2_4.sym b/xschem/and2_4.sym new file mode 100644 index 0000000..000c043 --- /dev/null +++ b/xschem/and2_4.sym
@@ -0,0 +1,40 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +function2="0 1 &" +format="@name @@A @@B @VGND @VNB @VPB @VPWR @@X @prefix\\\\and2_4" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -60 -20 -30 -20 {} +L 4 -60 20 -30 20 {} +L 4 -30 -30 -30 30 {} +L 4 -30 30 5 30 {} +L 4 -30 -30 5 -30 {} +L 4 35 0 60 0 {} +B 5 -62.5 -22.5 -57.5 -17.5 {name=A dir=in goto=2 propag=2 } +B 5 -62.5 17.5 -57.5 22.5 {name=B dir=in goto=2 propag=2 } +B 5 57.5 -2.5 62.5 2.5 {name=X dir=out } +A 4 5 0 30 270 180 {} +T {@name} -28.75 -5 0 0 0.2 0.2 {} +T {@symname} -25 -45 0 0 0.2 0.2 {} +T {A} -55 -34 0 0 0.2 0.2 {} +T {B} -55 6 0 0 0.2 0.2 {} +T {X} 55 -14 0 1 0.2 0.2 {}
diff --git a/xschem/and4_4.sym b/xschem/and4_4.sym new file mode 100644 index 0000000..f28f02a --- /dev/null +++ b/xschem/and4_4.sym
@@ -0,0 +1,54 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +function4="0 1 2 3 & & &" +format="@name @@A @@B @@C @@D @VGND @VNB @VPB @VPWR @@X @prefix\\\\and4_4" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -60 -60 -40 -60 {} +L 4 -60 -20 -45 -20 {} +L 4 -30 -30 -30 30 {} +L 4 -30 30 5 30 {} +L 4 -30 -30 5 -30 {} +L 4 35 0 60 0 {} +L 4 -60 60 -40 60 {} +L 4 -40 25 -40 60 {} +L 4 -40 25 -30 25 {} +L 4 -40 -60 -40 -25 {} +L 4 -40 -25 -30 -25 {} +L 4 -60 20 -45 20 {} +L 4 -45 10 -45 20 {} +L 4 -45 10 -30 10 {} +L 4 -45 -20 -45 -10 {} +L 4 -45 -10 -30 -10 {} +B 5 -62.5 -62.5 -57.5 -57.5 {name=A dir=in goto=4 propag=4 } +B 5 -62.5 -22.5 -57.5 -17.5 {name=B dir=in goto=4 propag=4 } +B 5 -62.5 17.5 -57.5 22.5 {name=C dir=in goto=4 propag=4 } +B 5 -62.5 57.5 -57.5 62.5 {name=D dir=in goto=4 propag=4 } +B 5 57.5 -2.5 62.5 2.5 {name=X dir=out } +A 4 5 0 30 270 180 {} +T {D} -55 46 0 0 0.2 0.2 {} +T {@name} -28.75 -5 0 0 0.2 0.2 {} +T {@symname} -25 -45 0 0 0.2 0.2 {} +T {A} -55 -74 0 0 0.2 0.2 {} +T {B} -55 -34 0 0 0.2 0.2 {} +T {X} 55 -14 0 1 0.2 0.2 {} +T {C} -55 6 0 0 0.2 0.2 {}
diff --git a/xschem/and_level_up_shifter_x4.sch b/xschem/and_level_up_shifter_x4.sch new file mode 100755 index 0000000..f31c867 --- /dev/null +++ b/xschem/and_level_up_shifter_x4.sch
@@ -0,0 +1,40 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 430 -110 520 -110 { +lab=#net1} +N 430 -150 470 -150 { +lab=vccd1} +N 430 -130 470 -130 { +lab=vssd1} +N 60 -150 130 -150 { +lab=WL} +N 60 -130 130 -130 { +lab=SEL} +N 820 -50 880 -50 { +lab=out} +N 820 -70 880 -70 { +lab=outb} +N 820 -90 860 -90 { +lab=vccd1} +N 820 -110 860 -110 { +lab=vdda1} +N 820 -30 860 -30 { +lab=vssd1} +C {and.sym} 280 -130 0 0 {name=x2} +C {devices/iopin.sym} 180 -270 2 0 {name=p53 lab=vccd1} +C {devices/iopin.sym} 180 -290 2 0 {name=p1 lab=vdda1} +C {devices/iopin.sym} 180 -250 2 0 {name=p2 lab=vssd1} +C {devices/lab_pin.sym} 470 -130 0 1 {name=l26 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 470 -150 0 1 {name=l25 sig_type=std_logic lab=vccd1} +C {devices/ipin.sym} 60 -150 2 1 {name=p3 lab=in} +C {devices/ipin.sym} 60 -130 2 1 {name=p16 lab=SEL} +C {devices/opin.sym} 880 -50 2 1 {name=p4 lab=out} +C {devices/lab_pin.sym} 860 -90 0 1 {name=l1 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 860 -110 0 1 {name=l2 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 860 -30 0 1 {name=l3 sig_type=std_logic lab=vssd1} +C {level_up_shifter_x4.sym} 670 -70 0 0 {name=x3} +C {devices/opin.sym} 880 -70 2 1 {name=p5 lab=outb}
diff --git a/xschem/and_level_up_shifter_x4.sym b/xschem/and_level_up_shifter_x4.sym new file mode 100755 index 0000000..b358da6 --- /dev/null +++ b/xschem/and_level_up_shifter_x4.sym
@@ -0,0 +1,33 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -121.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 147.5 -42.5 152.5 -37.5 {name=vdda1 dir=inout } +L 7 130 -40 150 -40 {} +T {vdda1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=vccd1 dir=inout } +L 7 130 -20 150 -20 {} +T {vccd1} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=vssd1 dir=inout } +L 7 130 0 150 0 {} +T {vssd1} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=in dir=in } +L 4 -150 -40 -130 -40 {} +T {in} -125 -44 0 0 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=SEL dir=in } +L 4 -150 -20 -130 -20 {} +T {SEL} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=outb dir=out } +L 4 130 20 150 20 {} +T {outb} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=out dir=out } +L 4 130 40 150 40 {} +T {out} 125 36 0 1 0.2 0.2 {}
diff --git a/xschem/and_pair.sch b/xschem/and_pair.sch new file mode 100755 index 0000000..bb1684a --- /dev/null +++ b/xschem/and_pair.sch
@@ -0,0 +1,44 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 110 -190 230 -190 { +lab=SEL} +N 140 -190 140 -70 { +lab=SEL} +N 140 -70 230 -70 { +lab=SEL} +N 90 -190 110 -190 { +lab=SEL} +N 200 -210 230 -210 { +lab=A} +N 200 -90 230 -90 { +lab=B} +N 530 -210 590 -210 { +lab=vccd1} +N 530 -190 590 -190 { +lab=VSUBS} +N 530 -170 590 -170 { +lab=OUT_A} +N 530 -70 590 -70 { +lab=#net1} +N 530 -50 590 -50 { +lab=OUT_B} +N 530 -90 590 -90 { +lab=vccd1} +C {and.sym} 380 -190 0 0 {name=x1} +C {and.sym} 380 -70 0 0 {name=x2} +C {devices/ipin.sym} 90 -190 0 0 {name=p1 lab=SEL} +C {devices/ipin.sym} 200 -210 0 0 {name=p2 lab=A} +C {devices/ipin.sym} 200 -90 0 0 {name=p3 lab=B} +C {devices/iopin.sym} 80 -320 2 0 {name=p4 lab=vccd1} +C {devices/iopin.sym} 80 -300 2 0 {name=p5 lab=VSUBS +} +C {devices/lab_pin.sym} 590 -210 2 0 {name=l9 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 590 -190 0 1 {name=l2 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 590 -90 2 0 {name=l1 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 590 -170 0 0 {name=p6 lab=OUT_A} +C {devices/opin.sym} 590 -50 0 0 {name=p7 lab=OUT_B} +C {devices/lab_pin.sym} 590 -70 0 1 {name=l3 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/and_pair.sym b/xschem/and_pair.sym new file mode 100755 index 0000000..b269b68 --- /dev/null +++ b/xschem/and_pair.sym
@@ -0,0 +1,33 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -54 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +B 5 147.5 -32.5 152.5 -27.5 {name=vccd1 dir=inout } +L 7 130 -30 150 -30 {} +T {vccd1} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=VSUBS dir=inout } +L 7 130 -10 150 -10 {} +T {VSUBS} 125 -14 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=A dir=in } +L 4 -150 -30 -130 -30 {} +T {A} -125 -34 0 0 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=SEL dir=in } +L 4 -150 -10 -130 -10 {} +T {SEL} -125 -14 0 0 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=OUT_A dir=out } +L 4 130 10 150 10 {} +T {OUT_A} 125 6 0 1 0.2 0.2 {} +B 5 -152.5 7.5 -147.5 12.5 {name=B dir=in } +L 4 -150 10 -130 10 {} +T {B} -125 6 0 0 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=OUT_B dir=out } +L 4 130 30 150 30 {} +T {OUT_B} 125 26 0 1 0.2 0.2 {}
diff --git a/xschem/buf_4.sym b/xschem/buf_4.sym new file mode 100644 index 0000000..03c5cc0 --- /dev/null +++ b/xschem/buf_4.sym
@@ -0,0 +1,36 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +function1="0" +format="@name @@A @VGND @VNB @VPB @VPWR @@X @prefix\\\\buf_4" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -20 -20 -20 20 {} +L 4 -20 -20 20 0 {} +L 4 -20 20 20 0 {} +L 4 20 0 40 0 {} +L 4 -40 0 -20 0 {} +B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in goto=1 propag=1 } +B 5 37.5 -2.5 42.5 2.5 {name=X dir=out } +T {A} -35 -14 0 0 0.2 0.2 {} +T {X} 35 -14 0 1 0.2 0.2 {} +T {@name} 2.5 15 0 0 0.2 0.2 {} +T {@symname} -7.5 -25 0 0 0.2 0.2 {}
diff --git a/xschem/col_driver_big.sch b/xschem/col_driver_big.sch new file mode 100755 index 0000000..2190f0b --- /dev/null +++ b/xschem/col_driver_big.sch
@@ -0,0 +1,131 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 730 -350 790 -350 { +lab=A} +N 730 -160 790 -160 { +lab=B} +N 1090 -270 1140 -270 { +lab=VSUBS} +N 1090 -80 1140 -80 { +lab=VSUBS} +N 1090 -350 1140 -350 { +lab=vdda1} +N 1090 -160 1140 -160 { +lab=vdda1} +N 1090 -330 1140 -330 { +lab=vccd1} +N 1090 -140 1140 -140 { +lab=vccd1} +N 1090 -310 1140 -310 { +lab=Ab_3.3} +N 1090 -290 1140 -290 { +lab=A_3.3} +N 1090 -120 1140 -120 { +lab=Bb_3.3} +N 1090 -100 1140 -100 { +lab=B_3.3} +N 1350 -230 1400 -230 { +lab=Ab_3.3} +N 1350 -210 1400 -210 { +lab=B_3.3} +N 1350 -190 1400 -190 { +lab=A_3.3} +N 1350 -170 1400 -170 { +lab=Bb_3.3} +N 1700 -230 1750 -230 { +lab=vdda1} +N 1700 -210 1750 -210 { +lab=VSUBS} +N 2240 -260 2340 -260 { +lab=col} +N 2240 -240 2340 -240 { +lab=vdda1} +N 2240 -220 2340 -220 { +lab=VSUBS} +N 1700 -130 1750 -130 { +lab=SWcminus} +N 2240 -200 2340 -200 { +lab=SWcminus} +N 1700 -170 1750 -170 { +lab=SWref} +N 1700 -190 1750 -190 { +lab=SWrefb} +N 2240 -160 2340 -160 { +lab=SWrefb} +N 2240 -180 2340 -180 { +lab=SWref} +N 2240 -140 2340 -140 { +lab=SWcplus} +N 1700 -150 1750 -150 { +lab=SWcplus} +N 2240 -120 2340 -120 { +lab=Vcplus} +N 2240 -100 2340 -100 { +lab=Vcminus} +N 2240 -80 2340 -80 { +lab=Vref} +N 160 -250 230 -250 { +lab=LA_B} +N 160 -290 230 -290 { +lab=LA_A} +N 160 -270 230 -270 { +lab=SEL} +N 530 -290 580 -290 { +lab=vccd1} +N 530 -270 580 -270 { +lab=VSUBS} +N 530 -250 580 -250 { +lab=A} +N 530 -230 580 -230 { +lab=B} +C {level_up_shifter_x4.sym} 940 -310 0 0 {name=x1} +C {level_up_shifter_x4.sym} 940 -120 0 0 {name=x2} +C {devices/iopin.sym} 140 -420 2 0 {name=p53 lab=vccd1} +C {devices/iopin.sym} 140 -440 2 0 {name=p1 lab=vdda1} +C {devices/iopin.sym} 140 -400 2 0 {name=p2 lab=VSUBS} +C {devices/lab_pin.sym} 1140 -350 0 1 {name=l117 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1140 -160 0 1 {name=l2 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1140 -330 0 1 {name=l3 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1140 -140 0 1 {name=l4 sig_type=std_logic lab=vccd1} +C {decoder2to4_x6.sym} 1550 -180 0 0 {name=x3} +C {devices/lab_pin.sym} 1140 -310 0 1 {name=l5 sig_type=std_logic lab=Ab_3.3} +C {devices/lab_pin.sym} 1140 -290 0 1 {name=l6 sig_type=std_logic lab=A_3.3} +C {devices/lab_pin.sym} 1140 -120 0 1 {name=l7 sig_type=std_logic lab=Bb_3.3} +C {devices/lab_pin.sym} 1140 -100 0 1 {name=l8 sig_type=std_logic lab=B_3.3} +C {devices/lab_pin.sym} 1350 -230 0 0 {name=l9 sig_type=std_logic lab=Ab_3.3} +C {devices/lab_pin.sym} 1350 -190 0 0 {name=l10 sig_type=std_logic lab=A_3.3} +C {devices/lab_pin.sym} 1350 -210 0 0 {name=l11 sig_type=std_logic lab=B_3.3} +C {devices/lab_pin.sym} 1350 -170 0 0 {name=l12 sig_type=std_logic lab=Bb_3.3} +C {devices/lab_pin.sym} 1750 -230 0 1 {name=l13 sig_type=std_logic lab=vdda1} +C {col_driver_x50.sym} 2090 -170 0 0 {name=x4} +C {devices/iopin.sym} 2340 -260 2 1 {name=p5 lab=col} +C {devices/lab_pin.sym} 2340 -240 0 1 {name=l15 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 2340 -200 0 1 {name=l17 sig_type=std_logic lab=SWcminus} +C {devices/lab_pin.sym} 1750 -130 0 1 {name=l18 sig_type=std_logic lab=SWcminus} +C {devices/lab_pin.sym} 1750 -170 0 1 {name=l19 sig_type=std_logic lab=SWref} +C {devices/lab_pin.sym} 1750 -190 0 1 {name=l20 sig_type=std_logic lab=SWrefb} +C {devices/lab_pin.sym} 2340 -160 0 1 {name=l21 sig_type=std_logic lab=SWrefb} +C {devices/lab_pin.sym} 2340 -180 0 1 {name=l22 sig_type=std_logic lab=SWref} +C {devices/lab_pin.sym} 2340 -140 0 1 {name=l23 sig_type=std_logic lab=SWcplus} +C {devices/lab_pin.sym} 1750 -150 0 1 {name=l24 sig_type=std_logic lab=SWcplus} +C {devices/iopin.sym} 2340 -80 2 1 {name=p6 lab=Vref} +C {devices/iopin.sym} 2340 -120 2 1 {name=p7 lab=Vcplus} +C {devices/iopin.sym} 2340 -100 2 1 {name=p8 lab=Vcminus} +C {devices/ipin.sym} 160 -290 2 1 {name=p9 lab=LA_A} +C {devices/ipin.sym} 160 -250 2 1 {name=p10 lab=LA_B} +C {and_pair.sym} 380 -260 0 0 {name=x5} +C {devices/ipin.sym} 160 -270 2 1 {name=p16 lab=SEL} +C {devices/lab_pin.sym} 580 -270 0 1 {name=l26 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 580 -290 0 1 {name=l25 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 580 -250 0 1 {name=l27 sig_type=std_logic lab=A} +C {devices/lab_pin.sym} 580 -230 0 1 {name=l28 sig_type=std_logic lab=B} +C {devices/lab_pin.sym} 730 -350 0 0 {name=l29 sig_type=std_logic lab=A} +C {devices/lab_pin.sym} 730 -160 0 0 {name=l30 sig_type=std_logic lab=B} +C {devices/lab_pin.sym} 1140 -270 0 1 {name=l1 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1140 -80 0 1 {name=l31 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1750 -210 0 1 {name=l14 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 2340 -220 0 1 {name=l16 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/col_driver_big.sym b/xschem/col_driver_big.sym new file mode 100755 index 0000000..e752e17 --- /dev/null +++ b/xschem/col_driver_big.sym
@@ -0,0 +1,42 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -81 -6 0 0 0.3 0.3 {} +T {@name} 135 -82 0 0 0.2 0.2 {} +L 4 -130 -70 130 -70 {} +L 4 -130 70 130 70 {} +L 4 -130 -70 -130 70 {} +L 4 130 -70 130 70 {} +B 5 147.5 -62.5 152.5 -57.5 {name=vdda1 dir=inout } +L 7 130 -60 150 -60 {} +T {vdda1} 125 -64 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=vccd1 dir=inout } +L 7 130 -40 150 -40 {} +T {vccd1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=VSUBS dir=inout } +L 7 130 -20 150 -20 {} +T {VSUBS} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -62.5 -147.5 -57.5 {name=LA_A dir=in } +L 4 -150 -60 -130 -60 {} +T {LA_A} -125 -64 0 0 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=SEL dir=in } +L 4 -150 -40 -130 -40 {} +T {SEL} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=col dir=inout } +L 7 130 0 150 0 {} +T {col} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=LA_B dir=in } +L 4 -150 -20 -130 -20 {} +T {LA_B} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vcplus dir=inout } +L 7 130 20 150 20 {} +T {Vcplus} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=Vcminus dir=inout } +L 7 130 40 150 40 {} +T {Vcminus} 125 36 0 1 0.2 0.2 {} +B 5 147.5 57.5 152.5 62.5 {name=Vref dir=inout } +L 7 130 60 150 60 {} +T {Vref} 125 56 0 1 0.2 0.2 {}
diff --git a/xschem/col_driver_x50.sch b/xschem/col_driver_x50.sch new file mode 100755 index 0000000..cd81b5c --- /dev/null +++ b/xschem/col_driver_x50.sch
@@ -0,0 +1,130 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 170 -210 170 -170 { +lab=Vcplus} +N 100 -240 130 -240 { +lab=SWcplus} +N 170 -340 170 -270 { +lab=col} +N 170 -240 230 -240 { +lab=VP} +N 390 -240 420 -240 { +lab=SWref} +N 460 -240 510 -240 { +lab=VSUBS} +N 1020 -240 1050 -240 { +lab=SWcminus} +N 930 -240 980 -240 { +lab=VN} +N 460 -340 460 -270 { +lab=col} +N 980 -340 980 -270 { +lab=col} +N 170 -340 460 -340 { +lab=col} +N 460 -340 750 -340 { +lab=col} +N 570 -430 570 -340 { +lab=col} +N 460 -210 460 -160 { +lab=Vref} +N 980 -210 980 -160 { +lab=Vcminus} +N 170 -170 170 -130 { +lab=Vcplus} +N 980 -160 980 -110 { +lab=Vcminus} +N 750 -340 910 -340 { +lab=col} +N 660 -210 660 -170 { +lab=Vref} +N 700 -240 730 -240 { +lab=SWrefb} +N 660 -340 660 -270 { +lab=col} +N 600 -240 660 -240 { +lab=VP} +N 460 -150 660 -150 { +lab=Vref} +N 910 -340 980 -340 { +lab=col} +N 560 -150 560 -110 { +lab=Vref} +N 660 -170 660 -150 { +lab=Vref} +N 460 -160 460 -150 { +lab=Vref} +C {devices/iopin.sym} 560 -120 1 0 {name=p1 lab=Vref} +C {devices/iopin.sym} 170 -130 1 0 {name=p2 lab=Vcplus} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 150 -240 2 1 {name=M4 +L=0.5 +W=1 +nf=1 +mult=50 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 70 -400 0 0 {name=p4 lab=VP} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 440 -240 0 0 {name=M1 +L=0.5 +W=1 +nf=1 +mult=25 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 230 -240 2 0 {name=l1 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 100 -240 2 0 {name=p5 lab=SWcplus} +C {devices/iopin.sym} 390 -240 2 0 {name=p6 lab=SWref} +C {devices/iopin.sym} 70 -380 0 0 {name=p7 lab=VSUBS} +C {devices/lab_pin.sym} 510 -240 2 0 {name=l2 sig_type=std_logic lab=VSUBS} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1000 -240 0 1 {name=M2 +L=0.5 +W=1 +nf=1 +mult=25 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 1050 -240 2 1 {name=p8 lab=SWcminus} +C {devices/lab_pin.sym} 930 -240 2 1 {name=l3 sig_type=std_logic lab=VSUBS} +C {devices/iopin.sym} 570 -430 3 0 {name=p9 lab=col} +C {devices/iopin.sym} 980 -120 1 0 {name=p11 lab=Vcminus} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 680 -240 2 0 {name=M3 +L=0.5 +W=1 +nf=1 +mult=50 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 600 -240 2 1 {name=l4 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 730 -240 2 1 {name=p10 lab=SWrefb}
diff --git a/xschem/col_driver_x50.sym b/xschem/col_driver_x50.sym new file mode 100755 index 0000000..b803069 --- /dev/null +++ b/xschem/col_driver_x50.sym
@@ -0,0 +1,42 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -81 -6 0 0 0.3 0.3 {} +T {@name} 135 -112 0 0 0.2 0.2 {} +L 4 -130 -100 130 -100 {} +L 4 -130 100 130 100 {} +L 4 -130 -100 -130 100 {} +L 4 130 -100 130 100 {} +B 5 147.5 -92.5 152.5 -87.5 {name=col dir=inout } +L 7 130 -90 150 -90 {} +T {col} 125 -94 0 1 0.2 0.2 {} +B 5 147.5 -72.5 152.5 -67.5 {name=VP dir=inout } +L 7 130 -70 150 -70 {} +T {VP} 125 -74 0 1 0.2 0.2 {} +B 5 147.5 -52.5 152.5 -47.5 {name=VSUBS dir=inout } +L 7 130 -50 150 -50 {} +T {VSUBS} 125 -54 0 1 0.2 0.2 {} +B 5 147.5 -32.5 152.5 -27.5 {name=SWcminus dir=inout } +L 7 130 -30 150 -30 {} +T {SWcminus} 125 -34 0 1 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=SWref dir=inout } +L 7 130 -10 150 -10 {} +T {SWref} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=SWrefb dir=inout } +L 7 130 10 150 10 {} +T {SWrefb} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=SWcplus dir=inout } +L 7 130 30 150 30 {} +T {SWcplus} 125 26 0 1 0.2 0.2 {} +B 5 147.5 47.5 152.5 52.5 {name=Vcplus dir=inout } +L 7 130 50 150 50 {} +T {Vcplus} 125 46 0 1 0.2 0.2 {} +B 5 147.5 67.5 152.5 72.5 {name=Vcminus dir=inout } +L 7 130 70 150 70 {} +T {Vcminus} 125 66 0 1 0.2 0.2 {} +B 5 147.5 87.5 152.5 92.5 {name=Vref dir=inout } +L 7 130 90 150 90 {} +T {Vref} 125 86 0 1 0.2 0.2 {}
diff --git a/xschem/col_drivers_1x16.sch b/xschem/col_drivers_1x16.sch new file mode 100755 index 0000000..5a3d741 --- /dev/null +++ b/xschem/col_drivers_1x16.sch
@@ -0,0 +1,508 @@ +v {xschem version=3.1.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 190 -560 190 -350 { +lab=col0} +N 500 -560 500 -350 { +lab=col1} +N 780 -560 780 -350 { +lab=col2} +N 1360 -560 1360 -350 { +lab=col4} +N 1650 -560 1650 -350 { +lab=col5} +N 1930 -560 1930 -350 { +lab=col6} +N 2220 -560 2220 -350 { +lab=col7} +N 2510 -560 2510 -350 { +lab=col8} +N 2800 -560 2800 -350 { +lab=col9} +N 3080 -560 3080 -350 { +lab=col10} +N 3370 -560 3370 -350 { +lab=col11} +N 3660 -560 3660 -350 { +lab=col12} +N 3950 -560 3950 -350 { +lab=col13} +N 4230 -560 4230 -350 { +lab=col14} +N 4520 -560 4520 -350 { +lab=col15} +N 170 -50 170 0 { +lab=B0} +N 130 -50 130 -0 { +lab=A0} +N 150 -50 150 0 { +lab=SEL} +N 150 -430 150 -350 { +lab=vccd1} +N 130 -430 130 -350 { +lab=vdda1} +N 170 -430 170 -350 { +lab=VSUBS} +N 210 -430 210 -350 { +lab=Vcplus} +N 230 -430 230 -350 { +lab=Vcminus} +N 250 -430 250 -350 { +lab=Vref} +N 480 -50 480 0 { +lab=B1} +N 440 -50 440 0 { +lab=A1} +N 460 -50 460 0 { +lab=SEL} +N 460 -430 460 -350 { +lab=vccd1} +N 440 -430 440 -350 { +lab=vdda1} +N 480 -430 480 -350 { +lab=VSUBS} +N 520 -430 520 -350 { +lab=Vcplus} +N 540 -430 540 -350 { +lab=Vcminus} +N 560 -430 560 -350 { +lab=Vref} +N 740 -430 740 -350 { +lab=vccd1} +N 720 -430 720 -350 { +lab=vdda1} +N 820 -430 820 -350 { +lab=Vcminus} +N 840 -430 840 -350 { +lab=Vref} +N 1010 -430 1010 -350 { +lab=vdda1} +N 1090 -430 1090 -350 { +lab=Vcplus} +N 1110 -430 1110 -350 { +lab=Vcminus} +N 1130 -430 1130 -350 { +lab=Vref} +N 1070 -560 1070 -350 { +lab=col3} +N 1030 -430 1030 -350 { +lab=vccd1} +N 1050 -430 1050 -350 { +lab=VSUBS} +N 760 -430 760 -350 { +lab=VSUBS} +N 800 -430 800 -350 { +lab=Vcplus} +N 1320 -430 1320 -350 { +lab=vccd1} +N 1300 -430 1300 -350 { +lab=vdda1} +N 1400 -430 1400 -350 { +lab=Vcminus} +N 1420 -430 1420 -350 { +lab=Vref} +N 1590 -430 1590 -350 { +lab=vdda1} +N 1670 -430 1670 -350 { +lab=Vcplus} +N 1690 -430 1690 -350 { +lab=Vcminus} +N 1710 -430 1710 -350 { +lab=Vref} +N 1610 -430 1610 -350 { +lab=vccd1} +N 1630 -430 1630 -350 { +lab=VSUBS} +N 1340 -430 1340 -350 { +lab=VSUBS} +N 1380 -430 1380 -350 { +lab=Vcplus} +N 1890 -430 1890 -350 { +lab=vccd1} +N 1870 -430 1870 -350 { +lab=vdda1} +N 1970 -430 1970 -350 { +lab=Vcminus} +N 1990 -430 1990 -350 { +lab=Vref} +N 2160 -430 2160 -350 { +lab=vdda1} +N 2240 -430 2240 -350 { +lab=Vcplus} +N 2260 -430 2260 -350 { +lab=Vcminus} +N 2280 -430 2280 -350 { +lab=Vref} +N 2180 -430 2180 -350 { +lab=vccd1} +N 2200 -430 2200 -350 { +lab=VSUBS} +N 1910 -430 1910 -350 { +lab=VSUBS} +N 1950 -430 1950 -350 { +lab=Vcplus} +N 2470 -430 2470 -350 { +lab=vccd1} +N 2450 -430 2450 -350 { +lab=vdda1} +N 2550 -430 2550 -350 { +lab=Vcminus} +N 2570 -430 2570 -350 { +lab=Vref} +N 2740 -430 2740 -350 { +lab=vdda1} +N 2820 -430 2820 -350 { +lab=Vcplus} +N 2840 -430 2840 -350 { +lab=Vcminus} +N 2860 -430 2860 -350 { +lab=Vref} +N 2760 -430 2760 -350 { +lab=vccd1} +N 2780 -430 2780 -350 { +lab=VSUBS} +N 2490 -430 2490 -350 { +lab=VSUBS} +N 2530 -430 2530 -350 { +lab=Vcplus} +N 3040 -430 3040 -350 { +lab=vccd1} +N 3020 -430 3020 -350 { +lab=vdda1} +N 3120 -430 3120 -350 { +lab=Vcminus} +N 3140 -430 3140 -350 { +lab=Vref} +N 3310 -430 3310 -350 { +lab=vdda1} +N 3390 -430 3390 -350 { +lab=Vcplus} +N 3410 -430 3410 -350 { +lab=Vcminus} +N 3430 -430 3430 -350 { +lab=Vref} +N 3330 -430 3330 -350 { +lab=vccd1} +N 3350 -430 3350 -350 { +lab=VSUBS} +N 3060 -430 3060 -350 { +lab=VSUBS} +N 3100 -430 3100 -350 { +lab=Vcplus} +N 3620 -430 3620 -350 { +lab=vccd1} +N 3600 -430 3600 -350 { +lab=vdda1} +N 3700 -430 3700 -350 { +lab=Vcminus} +N 3720 -430 3720 -350 { +lab=Vref} +N 3890 -430 3890 -350 { +lab=vdda1} +N 3970 -430 3970 -350 { +lab=Vcplus} +N 3990 -430 3990 -350 { +lab=Vcminus} +N 4010 -430 4010 -350 { +lab=Vref} +N 3910 -430 3910 -350 { +lab=vccd1} +N 3930 -430 3930 -350 { +lab=VSUBS} +N 3640 -430 3640 -350 { +lab=VSUBS} +N 3680 -430 3680 -350 { +lab=Vcplus} +N 4190 -430 4190 -350 { +lab=vccd1} +N 4170 -430 4170 -350 { +lab=vdda1} +N 4270 -430 4270 -350 { +lab=Vcminus} +N 4290 -430 4290 -350 { +lab=Vref} +N 4460 -430 4460 -350 { +lab=vdda1} +N 4540 -430 4540 -350 { +lab=Vcplus} +N 4560 -430 4560 -350 { +lab=Vcminus} +N 4580 -430 4580 -350 { +lab=Vref} +N 4480 -430 4480 -350 { +lab=vccd1} +N 4500 -430 4500 -350 { +lab=VSUBS} +N 4210 -430 4210 -350 { +lab=VSUBS} +N 4250 -430 4250 -350 { +lab=Vcplus} +N 760 -50 760 0 { +lab=B2} +N 720 -50 720 0 { +lab=A2} +N 740 -50 740 0 { +lab=SEL} +N 1050 -50 1050 0 { +lab=B3} +N 1010 -50 1010 0 { +lab=A3} +N 1030 -50 1030 0 { +lab=SEL} +N 1340 -50 1340 0 { +lab=B4} +N 1300 -50 1300 0 { +lab=A4} +N 1320 -50 1320 0 { +lab=SEL} +N 1630 -50 1630 0 { +lab=B5} +N 1590 -50 1590 0 { +lab=A5} +N 1610 -50 1610 0 { +lab=SEL} +N 1910 -50 1910 0 { +lab=B6} +N 1870 -50 1870 0 { +lab=A6} +N 1890 -50 1890 0 { +lab=SEL} +N 2200 -50 2200 0 { +lab=B7} +N 2160 -50 2160 0 { +lab=A7} +N 2180 -50 2180 0 { +lab=SEL} +N 2490 -50 2490 0 { +lab=B8} +N 2450 -50 2450 0 { +lab=A8} +N 2470 -50 2470 0 { +lab=SEL} +N 2780 -50 2780 0 { +lab=B9} +N 2740 -50 2740 0 { +lab=A9} +N 2760 -50 2760 0 { +lab=SEL} +N 3060 -50 3060 0 { +lab=B10} +N 3020 -50 3020 0 { +lab=A10} +N 3040 -50 3040 0 { +lab=SEL} +N 3350 -50 3350 0 { +lab=B11} +N 3310 -50 3310 0 { +lab=A11} +N 3330 -50 3330 0 { +lab=SEL} +N 3640 -50 3640 0 { +lab=B12} +N 3600 -50 3600 0 { +lab=A12} +N 3620 -50 3620 0 { +lab=SEL} +N 3930 -50 3930 0 { +lab=B13} +N 3890 -50 3890 0 { +lab=A13} +N 3910 -50 3910 0 { +lab=SEL} +N 4210 -50 4210 0 { +lab=B14} +N 4170 -50 4170 0 { +lab=A14} +N 4190 -50 4190 0 { +lab=SEL} +N 4500 -50 4500 0 { +lab=B15} +N 4460 -50 4460 0 { +lab=A15} +N 4480 -50 4480 0 { +lab=SEL} +C {col_driver_big.sym} 190 -200 3 0 {name=x1} +C {col_driver_big.sym} 500 -200 3 0 {name=x2} +C {col_driver_big.sym} 780 -200 3 0 {name=x3} +C {col_driver_big.sym} 1070 -200 3 0 {name=x4} +C {col_driver_big.sym} 1360 -200 3 0 {name=x5} +C {col_driver_big.sym} 1650 -200 3 0 {name=x6} +C {col_driver_big.sym} 1930 -200 3 0 {name=x7} +C {col_driver_big.sym} 2220 -200 3 0 {name=x8} +C {col_driver_big.sym} 2510 -200 3 0 {name=x9} +C {col_driver_big.sym} 2800 -200 3 0 {name=x10} +C {col_driver_big.sym} 3080 -200 3 0 {name=x11} +C {col_driver_big.sym} 3370 -200 3 0 {name=x12} +C {col_driver_big.sym} 3660 -200 3 0 {name=x13} +C {col_driver_big.sym} 3950 -200 3 0 {name=x14} +C {col_driver_big.sym} 4230 -200 3 0 {name=x15} +C {col_driver_big.sym} 4520 -200 3 0 {name=x16} +C {devices/iopin.sym} 20 -450 2 0 {name=p1 lab=vdda1} +C {devices/iopin.sym} 20 -410 2 0 {name=p2 lab=VSUBS} +C {devices/iopin.sym} 20 -510 2 0 {name=p5 lab=Vref} +C {devices/iopin.sym} 20 -490 2 0 {name=p6 lab=Vcplus} +C {devices/iopin.sym} 20 -470 2 0 {name=p7 lab=Vcminus} +C {devices/iopin.sym} 20 -430 2 0 {name=p3 lab=vccd1} +C {devices/iopin.sym} 190 -560 3 0 {name=p4 lab=col0} +C {devices/ipin.sym} 130 0 3 0 {name=p8 lab=A0} +C {devices/ipin.sym} 170 0 3 0 {name=p9 lab=B0} +C {devices/iopin.sym} 500 -560 3 0 {name=p10 lab=col1} +C {devices/ipin.sym} 440 0 1 1 {name=p11 lab=A1} +C {devices/ipin.sym} 480 0 1 1 {name=p12 lab=B1} +C {devices/iopin.sym} 780 -560 3 0 {name=p13 lab=col2} +C {devices/ipin.sym} 720 0 3 0 {name=p14 lab=A2} +C {devices/ipin.sym} 760 0 3 0 {name=p15 lab=B2} +C {devices/iopin.sym} 1070 -560 3 0 {name=p16 lab=col3} +C {devices/iopin.sym} 1360 -560 3 0 {name=p17 lab=col4} +C {devices/ipin.sym} 1010 0 3 0 {name=p18 lab=A3} +C {devices/ipin.sym} 1050 0 3 0 {name=p19 lab=B3} +C {devices/ipin.sym} 1300 0 3 0 {name=p20 lab=A4} +C {devices/ipin.sym} 1340 0 3 0 {name=p21 lab=B4} +C {devices/iopin.sym} 1650 -560 3 0 {name=p22 lab=col5} +C {devices/ipin.sym} 1590 0 3 0 {name=p23 lab=A5} +C {devices/ipin.sym} 1630 0 3 0 {name=p24 lab=B5} +C {devices/iopin.sym} 1930 -560 3 0 {name=p25 lab=col6} +C {devices/ipin.sym} 1870 0 3 0 {name=p26 lab=A6} +C {devices/ipin.sym} 1910 0 3 0 {name=p27 lab=B6} +C {devices/iopin.sym} 2220 -560 3 0 {name=p28 lab=col7} +C {devices/ipin.sym} 2160 0 3 0 {name=p29 lab=A7} +C {devices/ipin.sym} 2200 0 3 0 {name=p30 lab=B7} +C {devices/iopin.sym} 2510 -560 3 0 {name=p31 lab=col8} +C {devices/ipin.sym} 2450 0 3 0 {name=p32 lab=A8} +C {devices/ipin.sym} 2490 0 3 0 {name=p33 lab=B8} +C {devices/iopin.sym} 2800 -560 3 0 {name=p34 lab=col9} +C {devices/ipin.sym} 2740 0 3 0 {name=p35 lab=A9} +C {devices/ipin.sym} 2780 0 3 0 {name=p36 lab=B9} +C {devices/iopin.sym} 3080 -560 3 0 {name=p37 lab=col10} +C {devices/ipin.sym} 3020 0 3 0 {name=p38 lab=A10} +C {devices/ipin.sym} 3060 0 3 0 {name=p39 lab=B10} +C {devices/iopin.sym} 3370 -560 3 0 {name=p40 lab=col11} +C {devices/iopin.sym} 3660 -560 3 0 {name=p41 lab=col12} +C {devices/ipin.sym} 3310 0 3 0 {name=p42 lab=A11} +C {devices/ipin.sym} 3350 0 3 0 {name=p43 lab=B11} +C {devices/ipin.sym} 3600 0 3 0 {name=p44 lab=A12} +C {devices/ipin.sym} 3640 0 3 0 {name=p45 lab=B12} +C {devices/iopin.sym} 3950 -560 3 0 {name=p46 lab=col13} +C {devices/ipin.sym} 3890 0 3 0 {name=p47 lab=A13} +C {devices/ipin.sym} 3930 0 3 0 {name=p48 lab=B13} +C {devices/iopin.sym} 4230 -560 3 0 {name=p49 lab=col14} +C {devices/ipin.sym} 4170 0 3 0 {name=p50 lab=A14} +C {devices/ipin.sym} 4210 0 3 0 {name=p51 lab=B14} +C {devices/iopin.sym} 4520 -560 3 0 {name=p52 lab=col15} +C {devices/ipin.sym} 4460 0 3 0 {name=p53 lab=A15} +C {devices/ipin.sym} 4500 0 3 0 {name=p54 lab=B15} +C {devices/ipin.sym} 150 0 3 0 {name=p55 lab=SEL} +C {devices/lab_pin.sym} 130 -430 1 0 {name=l1 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 150 -430 1 0 {name=l2 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 170 -430 1 0 {name=l3 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 210 -430 1 0 {name=l4 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 250 -430 1 0 {name=l5 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 230 -430 1 0 {name=l6 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 460 0 1 1 {name=l7 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 440 -430 1 0 {name=l8 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 460 -430 1 0 {name=l9 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 520 -430 1 0 {name=l11 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 560 -430 1 0 {name=l12 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 540 -430 1 0 {name=l13 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 720 -430 1 0 {name=l14 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 740 -430 1 0 {name=l15 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 800 -430 1 0 {name=l17 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 840 -430 1 0 {name=l18 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 820 -430 1 0 {name=l19 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 1010 -430 1 0 {name=l20 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1030 -430 1 0 {name=l21 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1090 -430 1 0 {name=l23 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 1130 -430 1 0 {name=l24 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 1110 -430 1 0 {name=l25 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 1300 -430 1 0 {name=l26 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1320 -430 1 0 {name=l27 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1380 -430 1 0 {name=l29 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 1420 -430 1 0 {name=l30 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 1400 -430 1 0 {name=l31 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 1590 -430 1 0 {name=l32 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1610 -430 1 0 {name=l33 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1670 -430 1 0 {name=l35 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 1710 -430 1 0 {name=l36 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 1690 -430 1 0 {name=l37 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 1870 -430 1 0 {name=l38 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1890 -430 1 0 {name=l39 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1950 -430 1 0 {name=l41 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 1990 -430 1 0 {name=l42 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 1970 -430 1 0 {name=l43 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 2160 -430 1 0 {name=l44 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 2180 -430 1 0 {name=l45 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 2240 -430 1 0 {name=l47 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 2280 -430 1 0 {name=l48 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 2260 -430 1 0 {name=l49 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 2450 -430 1 0 {name=l50 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 2470 -430 1 0 {name=l51 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 2530 -430 1 0 {name=l53 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 2570 -430 1 0 {name=l54 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 2550 -430 1 0 {name=l55 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 2740 -430 1 0 {name=l56 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 2760 -430 1 0 {name=l57 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 2820 -430 1 0 {name=l59 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 2860 -430 1 0 {name=l60 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 2840 -430 1 0 {name=l61 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 3020 -430 1 0 {name=l62 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 3040 -430 1 0 {name=l63 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 3100 -430 1 0 {name=l65 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 3140 -430 1 0 {name=l66 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 3120 -430 1 0 {name=l67 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 3310 -430 1 0 {name=l68 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 3330 -430 1 0 {name=l69 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 3390 -430 1 0 {name=l71 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 3430 -430 1 0 {name=l72 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 3410 -430 1 0 {name=l73 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 3600 -430 1 0 {name=l74 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 3620 -430 1 0 {name=l75 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 3680 -430 1 0 {name=l77 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 3720 -430 1 0 {name=l78 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 3700 -430 1 0 {name=l79 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 3890 -430 1 0 {name=l80 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 3910 -430 1 0 {name=l81 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 3970 -430 1 0 {name=l83 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 4010 -430 1 0 {name=l84 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 3990 -430 1 0 {name=l85 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 4170 -430 1 0 {name=l86 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 4190 -430 1 0 {name=l87 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 4250 -430 1 0 {name=l89 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 4290 -430 1 0 {name=l90 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 4270 -430 1 0 {name=l91 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 4460 -430 1 0 {name=l92 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 4480 -430 1 0 {name=l93 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 4540 -430 1 0 {name=l95 sig_type=std_logic lab=Vcplus} +C {devices/lab_pin.sym} 4580 -430 1 0 {name=l96 sig_type=std_logic lab=Vref} +C {devices/lab_pin.sym} 4560 -430 1 0 {name=l97 sig_type=std_logic lab=Vcminus} +C {devices/lab_pin.sym} 740 0 1 1 {name=l98 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1030 0 1 1 {name=l99 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1320 0 1 1 {name=l100 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1610 0 1 1 {name=l101 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1890 0 1 1 {name=l102 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 2180 0 1 1 {name=l103 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 2470 0 1 1 {name=l104 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 2760 0 1 1 {name=l105 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 3040 0 1 1 {name=l106 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 3330 0 1 1 {name=l107 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 3620 0 1 1 {name=l108 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 3910 0 1 1 {name=l109 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 4190 0 1 1 {name=l110 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 4480 0 1 1 {name=l111 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 480 -430 1 0 {name=l10 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1050 -430 1 0 {name=l112 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1340 -430 1 0 {name=l16 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 760 -430 1 0 {name=l22 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1630 -430 1 0 {name=l28 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1910 -430 1 0 {name=l34 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 2200 -430 1 0 {name=l40 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 2490 -430 1 0 {name=l46 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 2780 -430 1 0 {name=l52 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 3060 -430 1 0 {name=l58 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 3350 -430 1 0 {name=l64 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 3640 -430 1 0 {name=l70 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 3930 -430 1 0 {name=l76 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 4210 -430 1 0 {name=l82 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 4500 -430 1 0 {name=l88 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/col_drivers_1x16.sym b/xschem/col_drivers_1x16.sym new file mode 100755 index 0000000..f977cba --- /dev/null +++ b/xschem/col_drivers_1x16.sym
@@ -0,0 +1,180 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -330 130 -330 {} +L 4 -130 330 130 330 {} +L 4 -130 -330 -130 330 {} +L 4 130 -330 130 330 {} +L 4 -150 -220 -130 -220 {} +L 4 -150 -40 -130 -40 {} +L 4 -150 -240 -130 -240 {} +L 4 -150 -60 -130 -60 {} +L 4 -150 280 -130 280 {} +L 4 -150 -80 -130 -80 {} +L 4 -150 -20 -130 -20 {} +L 4 -150 240 -130 240 {} +L 4 -150 220 -130 220 {} +L 4 -150 -100 -130 -100 {} +L 4 -150 -260 -130 -260 {} +L 4 -150 200 -130 200 {} +L 4 -150 160 -130 160 {} +L 4 -150 -120 -130 -120 {} +L 4 -150 -140 -130 -140 {} +L 4 -150 -160 -130 -160 {} +L 4 -150 -280 -130 -280 {} +L 4 -150 100 -130 100 {} +L 4 -150 120 -130 120 {} +L 4 -150 140 -130 140 {} +L 4 -150 80 -130 80 {} +L 4 -150 180 -130 180 {} +L 4 -150 60 -130 60 {} +L 4 -150 -180 -130 -180 {} +L 4 -150 40 -130 40 {} +L 4 -150 20 -130 20 {} +L 4 -150 0 -130 0 {} +L 4 -150 260 -130 260 {} +L 4 -150 -200 -130 -200 {} +L 4 -150 -300 -130 -300 {} +L 4 -150 300 -130 300 {} +L 4 -150 320 -130 320 {} +L 4 -150 -320 -130 -320 {} +L 7 130 -220 150 -220 {} +L 7 130 -120 150 -120 {} +L 7 130 -300 150 -300 {} +L 7 130 -240 150 -240 {} +L 7 130 -280 150 -280 {} +L 7 130 -140 150 -140 {} +L 7 130 -80 150 -80 {} +L 7 130 -60 150 -60 {} +L 7 130 -100 150 -100 {} +L 7 130 -40 150 -40 {} +L 7 130 -180 150 -180 {} +L 7 130 -320 150 -320 {} +L 7 130 -160 150 -160 {} +L 7 130 -260 150 -260 {} +L 7 130 -200 150 -200 {} +L 7 130 -20 150 -20 {} +L 7 130 0 150 0 {} +L 7 130 20 150 20 {} +L 7 130 40 150 40 {} +L 7 130 60 150 60 {} +L 7 130 80 150 80 {} +L 7 130 100 150 100 {} +B 5 147.5 -222.5 152.5 -217.5 {name=col5 dir=inout } +B 5 147.5 -122.5 152.5 -117.5 {name=col10 dir=inout } +B 5 147.5 -302.5 152.5 -297.5 {name=col1 dir=inout } +B 5 147.5 -242.5 152.5 -237.5 {name=col4 dir=inout } +B 5 147.5 -282.5 152.5 -277.5 {name=col2 dir=inout } +B 5 147.5 -142.5 152.5 -137.5 {name=col9 dir=inout } +B 5 147.5 -82.5 152.5 -77.5 {name=col12 dir=inout } +B 5 147.5 -62.5 152.5 -57.5 {name=col13 dir=inout } +B 5 147.5 -102.5 152.5 -97.5 {name=col11 dir=inout } +B 5 147.5 -42.5 152.5 -37.5 {name=col14 dir=inout } +B 5 147.5 -182.5 152.5 -177.5 {name=col7 dir=inout } +B 5 147.5 -322.5 152.5 -317.5 {name=col0 dir=inout } +B 5 147.5 -162.5 152.5 -157.5 {name=col8 dir=inout } +B 5 147.5 -262.5 152.5 -257.5 {name=col3 dir=inout } +B 5 147.5 -202.5 152.5 -197.5 {name=col6 dir=inout } +B 5 147.5 -22.5 152.5 -17.5 {name=col15 dir=inout } +B 5 147.5 -2.5 152.5 2.5 {name=Vref dir=inout } +B 5 147.5 17.5 152.5 22.5 {name=Vcplus dir=inout } +B 5 147.5 37.5 152.5 42.5 {name=Vcminus dir=inout } +B 5 147.5 57.5 152.5 62.5 {name=vdda1 dir=inout } +B 5 147.5 77.5 152.5 82.5 {name=vccd1 dir=inout } +B 5 147.5 97.5 152.5 102.5 {name=VSUBS dir=inout } +B 5 -152.5 -222.5 -147.5 -217.5 {name=B2 dir=in } +B 5 -152.5 -42.5 -147.5 -37.5 {name=A7 dir=in } +B 5 -152.5 -242.5 -147.5 -237.5 {name=A2 dir=in } +B 5 -152.5 -62.5 -147.5 -57.5 {name=B6 dir=in } +B 5 -152.5 277.5 -147.5 282.5 {name=A15 dir=in } +B 5 -152.5 -82.5 -147.5 -77.5 {name=A6 dir=in } +B 5 -152.5 -22.5 -147.5 -17.5 {name=B7 dir=in } +B 5 -152.5 237.5 -147.5 242.5 {name=A14 dir=in } +B 5 -152.5 217.5 -147.5 222.5 {name=B13 dir=in } +B 5 -152.5 -102.5 -147.5 -97.5 {name=B5 dir=in } +B 5 -152.5 -262.5 -147.5 -257.5 {name=B1 dir=in } +B 5 -152.5 197.5 -147.5 202.5 {name=A13 dir=in } +B 5 -152.5 157.5 -147.5 162.5 {name=A12 dir=in } +B 5 -152.5 -122.5 -147.5 -117.5 {name=A5 dir=in } +B 5 -152.5 -142.5 -147.5 -137.5 {name=B4 dir=in } +B 5 -152.5 -162.5 -147.5 -157.5 {name=A4 dir=in } +B 5 -152.5 -282.5 -147.5 -277.5 {name=A1 dir=in } +B 5 -152.5 97.5 -147.5 102.5 {name=B10 dir=in } +B 5 -152.5 117.5 -147.5 122.5 {name=A11 dir=in } +B 5 -152.5 137.5 -147.5 142.5 {name=B11 dir=in } +B 5 -152.5 77.5 -147.5 82.5 {name=A10 dir=in } +B 5 -152.5 177.5 -147.5 182.5 {name=B12 dir=in } +B 5 -152.5 57.5 -147.5 62.5 {name=B9 dir=in } +B 5 -152.5 -182.5 -147.5 -177.5 {name=B3 dir=in } +B 5 -152.5 37.5 -147.5 42.5 {name=A9 dir=in } +B 5 -152.5 17.5 -147.5 22.5 {name=B8 dir=in } +B 5 -152.5 -2.5 -147.5 2.5 {name=A8 dir=in } +B 5 -152.5 257.5 -147.5 262.5 {name=B14 dir=in } +B 5 -152.5 -202.5 -147.5 -197.5 {name=A3 dir=in } +B 5 -152.5 -302.5 -147.5 -297.5 {name=B0 dir=in } +B 5 -152.5 297.5 -147.5 302.5 {name=B15 dir=in } +B 5 -152.5 317.5 -147.5 322.5 {name=SEL dir=in } +B 5 -152.5 -322.5 -147.5 -317.5 {name=A0 dir=in } +T {@symname} -90 -6 0 0 0.3 0.3 {} +T {@name} 135 -342 0 0 0.2 0.2 {} +T {col5} 125 -224 0 1 0.2 0.2 {} +T {col10} 125 -124 0 1 0.2 0.2 {} +T {col1} 125 -304 0 1 0.2 0.2 {} +T {col4} 125 -244 0 1 0.2 0.2 {} +T {col2} 125 -284 0 1 0.2 0.2 {} +T {col9} 125 -144 0 1 0.2 0.2 {} +T {col12} 125 -84 0 1 0.2 0.2 {} +T {col13} 125 -64 0 1 0.2 0.2 {} +T {col11} 125 -104 0 1 0.2 0.2 {} +T {col14} 125 -44 0 1 0.2 0.2 {} +T {col7} 125 -184 0 1 0.2 0.2 {} +T {col0} 125 -324 0 1 0.2 0.2 {} +T {col8} 125 -164 0 1 0.2 0.2 {} +T {col3} 125 -264 0 1 0.2 0.2 {} +T {col6} 125 -204 0 1 0.2 0.2 {} +T {col15} 125 -24 0 1 0.2 0.2 {} +T {Vref} 125 -4 0 1 0.2 0.2 {} +T {Vcplus} 125 16 0 1 0.2 0.2 {} +T {Vcminus} 125 36 0 1 0.2 0.2 {} +T {vdda1} 125 56 0 1 0.2 0.2 {} +T {vccd1} 125 76 0 1 0.2 0.2 {} +T {VSUBS} 125 96 0 1 0.2 0.2 {} +T {B2} -125 -224 0 0 0.2 0.2 {} +T {A7} -125 -44 0 0 0.2 0.2 {} +T {A2} -125 -244 0 0 0.2 0.2 {} +T {B6} -125 -64 0 0 0.2 0.2 {} +T {A15} -125 276 0 0 0.2 0.2 {} +T {A6} -125 -84 0 0 0.2 0.2 {} +T {B7} -125 -24 0 0 0.2 0.2 {} +T {A14} -125 236 0 0 0.2 0.2 {} +T {B13} -125 216 0 0 0.2 0.2 {} +T {B5} -125 -104 0 0 0.2 0.2 {} +T {B1} -125 -264 0 0 0.2 0.2 {} +T {A13} -125 196 0 0 0.2 0.2 {} +T {A12} -125 156 0 0 0.2 0.2 {} +T {A5} -125 -124 0 0 0.2 0.2 {} +T {B4} -125 -144 0 0 0.2 0.2 {} +T {A4} -125 -164 0 0 0.2 0.2 {} +T {A1} -125 -284 0 0 0.2 0.2 {} +T {B10} -125 96 0 0 0.2 0.2 {} +T {A11} -125 116 0 0 0.2 0.2 {} +T {B11} -125 136 0 0 0.2 0.2 {} +T {A10} -125 76 0 0 0.2 0.2 {} +T {B12} -125 176 0 0 0.2 0.2 {} +T {B9} -125 56 0 0 0.2 0.2 {} +T {B3} -125 -184 0 0 0.2 0.2 {} +T {A9} -125 36 0 0 0.2 0.2 {} +T {B8} -125 16 0 0 0.2 0.2 {} +T {A8} -125 -4 0 0 0.2 0.2 {} +T {B14} -125 256 0 0 0.2 0.2 {} +T {A3} -125 -204 0 0 0.2 0.2 {} +T {B0} -125 -304 0 0 0.2 0.2 {} +T {B15} -125 296 0 0 0.2 0.2 {} +T {SEL} -125 316 0 0 0.2 0.2 {} +T {A0} -125 -324 0 0 0.2 0.2 {}
diff --git a/xschem/comp_out_sel.sch b/xschem/comp_out_sel.sch new file mode 100644 index 0000000..5978496 --- /dev/null +++ b/xschem/comp_out_sel.sch
@@ -0,0 +1,127 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 520 -140 520 -100 { +lab=#net1} +N 470 -170 520 -170 { +lab=vssd1} +N 520 -70 520 -40 { +lab=vssd1} +N 520 -40 520 -10 { +lab=vssd1} +N 340 -70 480 -70 { +lab=#net2} +N 340 -390 340 -70 { +lab=#net2} +N 340 -390 480 -390 { +lab=#net2} +N 300 -230 340 -230 { +lab=#net2} +N 170 -230 220 -230 { +lab=latch_high} +N 520 -250 520 -200 { +lab=latch_high_col} +N 520 -360 520 -310 { +lab=#net3} +N 470 -280 520 -280 { +lab=vccd1} +N 560 -170 610 -170 { +lab=row_selbuff} +N 940 -350 970 -350 { +lab=row_selb} +N 840 -350 860 -350 { +lab=row_selbuff} +N 820 -350 840 -350 { +lab=row_selbuff} +N 1050 -350 1080 -350 { +lab=row_sel} +N 560 -280 610 -280 { +lab=row_selb} +N 520 -450 520 -420 { +lab=vccd1} +N 520 -420 520 -390 { +lab=vccd1} +N 520 -230 580 -230 { +lab=latch_high_col} +C {inv_8.sym} 260 -230 0 0 {name=x1 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {devices/iopin.sym} 120 -380 0 1 {name=p7 lab=vccd1} +C {devices/iopin.sym} 120 -360 0 1 {name=p8 lab=vssd1} +C {sky130_fd_pr/nfet_01v8.sym} 500 -70 0 0 {name=M1 +L=0.15 +W=0.65 +nf=1 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 540 -170 0 1 {name=M2 +L=0.15 +W=0.65 +nf=1 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_hvt.sym} 500 -390 0 0 {name=M3 +L=0.15 +W=1 +nf=1 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_hvt +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8_hvt.sym} 540 -280 0 1 {name=M4 +L=0.15 +W=1 +nf=1 +mult=40 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8_hvt +spiceprefix=X +} +C {devices/lab_pin.sym} 520 -10 0 1 {name=l1 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 470 -170 0 0 {name=l2 sig_type=std_logic lab=vssd1} +C {devices/code.sym} 90 -570 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt +.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/lab_pin.sym} 470 -280 0 0 {name=l3 sig_type=std_logic lab=vccd1} +C {inv_8.sym} 1010 -350 0 1 {name=x2 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {inv_16.sym} 900 -350 0 1 {name=x3 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {devices/ipin.sym} 170 -230 0 0 {name=p1 lab=latch_high} +C {devices/ipin.sym} 1080 -350 0 1 {name=p2 lab=row_sel} +C {devices/lab_pin.sym} 960 -350 1 1 {name=l4 sig_type=std_logic lab=row_selb} +C {devices/lab_pin.sym} 820 -350 1 1 {name=l5 sig_type=std_logic lab=row_selbuff} +C {devices/lab_pin.sym} 610 -170 0 1 {name=l6 sig_type=std_logic lab=row_selbuff} +C {devices/lab_pin.sym} 610 -280 0 1 {name=l7 sig_type=std_logic lab=row_selb} +C {devices/lab_pin.sym} 520 -450 2 0 {name=l8 sig_type=std_logic lab=vccd1} +C {devices/opin.sym} 580 -230 0 0 {name=p3 lab=latch_high_col}
diff --git a/xschem/comp_out_sel.sym b/xschem/comp_out_sel.sym new file mode 100644 index 0000000..99be8e4 --- /dev/null +++ b/xschem/comp_out_sel.sym
@@ -0,0 +1,27 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -72 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +B 5 147.5 -22.5 152.5 -17.5 {name=vccd1 dir=inout } +L 7 130 -20 150 -20 {} +T {vccd1} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=vssd1 dir=inout } +L 7 130 0 150 0 {} +T {vssd1} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=row_sel dir=in } +L 4 -150 -20 -130 -20 {} +T {row_sel} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=latch_high_col dir=out } +L 4 130 20 150 20 {} +T {latch_high_col} 125 16 0 1 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=latch_high dir=in } +L 4 -150 0 -130 0 {} +T {latch_high} -125 -4 0 0 0.2 0.2 {}
diff --git a/xschem/comparator.sch b/xschem/comparator.sch new file mode 100755 index 0000000..b9dc28f --- /dev/null +++ b/xschem/comparator.sch
@@ -0,0 +1,319 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 110 -340 260 -340 { lab=high} +N 110 -280 260 -280 { lab=vssd1} +N 480 -340 630 -340 { lab=low} +N 480 -280 630 -280 { lab=vssd1} +N 440 -460 440 -310 { lab=high} +N 300 -500 300 -310 { lab=low} +N 260 -410 260 -340 { lab=high} +N 480 -410 480 -340 { lab=low} +N 260 -410 440 -410 { lab=high} +N 300 -340 480 -340 { lab=low} +N 810 -400 920 -400 { lab=tail} +N 920 -400 1030 -400 { lab=tail} +N 440 -500 440 -460 { lab=high} +N 240 -380 260 -380 { lab=high} +N 480 -380 510 -380 { lab=low} +N 260 -530 260 -500 { +lab=vccd1} +N 480 -530 480 -500 { +lab=vccd1} +N 1030 -520 1030 -490 { +lab=vccd1} +N 810 -520 810 -490 { +lab=vccd1} +N 260 -440 280 -440 { +lab=vccd1} +N 460 -440 480 -440 { +lab=vccd1} +N 810 -430 860 -430 { +lab=vssd1} +N 860 -430 1030 -430 { +lab=vssd1} +N 630 -280 670 -280 { +lab=vssd1} +N 630 -340 670 -340 { +lab=low} +N 260 -310 260 -280 { +lab=vssd1} +N 110 -310 110 -280 { +lab=vssd1} +N 670 -310 670 -280 { +lab=vssd1} +N 480 -310 480 -280 { +lab=vssd1} +N 920 -370 920 -340 { +lab=vssd1} +N 260 -550 260 -530 { +lab=vccd1} +N 480 -550 480 -530 { +lab=vccd1} +N 1030 -540 1030 -520 { +lab=vccd1} +N 810 -540 810 -520 { +lab=vccd1} +N 190 -280 190 -260 { +lab=vssd1} +N 580 -280 580 -260 { +lab=vssd1} +N 920 -340 920 -320 { +lab=vssd1} +N 1220 -200 1280 -200 { +lab=high_buff} +N 1230 -110 1270 -110 { +lab=low_buff} +N 1270 -110 1280 -110 { +lab=low_buff} +N 1460 -220 1510 -220 { +lab=latch_high} +N 1250 -200 1250 -150 { +lab=high_buff} +N 1250 -150 1320 -150 { +lab=high_buff} +N 1040 -200 1140 -200 { +lab=high} +N 1040 -110 1140 -110 { +lab=low} +N 1220 -110 1230 -110 { +lab=low_buff} +C {sky130_fd_pr/pfet_01v8.sym} 240 -440 0 0 {name=M16 +L=0.15 +W=1 +body=VDD +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 500 -440 0 1 {name=M11 +L=0.15 +W=1 +body=VDD +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {devices/lab_pin.sym} 520 -440 0 1 {name=l104 sig_type=std_logic lab=FN} +C {devices/lab_pin.sym} 220 -440 0 0 {name=l105 sig_type=std_logic lab=FP} +C {devices/lab_pin.sym} 880 -370 0 0 {name=l106 sig_type=std_logic lab=phi1} +C {devices/lab_pin.sym} 240 -380 0 0 {name=l107 sig_type=std_logic lab=high} +C {devices/lab_pin.sym} 510 -380 2 0 {name=l108 sig_type=std_logic lab=low} +C {devices/lab_pin.sym} 850 -490 2 0 {name=l109 sig_type=std_logic lab=phi1} +C {devices/lab_pin.sym} 710 -310 3 0 {name=l110 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 70 -310 0 0 {name=l111 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 810 -460 0 0 {name=l124 sig_type=std_logic lab=FP} +C {devices/lab_pin.sym} 1030 -460 0 1 {name=l125 sig_type=std_logic lab=FN} +C {devices/lab_pin.sym} 770 -430 0 0 {name=l15 sig_type=std_logic lab=inp} +C {devices/lab_pin.sym} 1070 -430 0 1 {name=l121 sig_type=std_logic lab=inm} +C {devices/ipin.sym} 140 -470 0 0 {name=p1 lab=phi1} +C {devices/ipin.sym} 140 -450 0 0 {name=p3 lab=phi1b} +C {devices/ipin.sym} 140 -430 0 0 {name=p4 lab=inp} +C {devices/ipin.sym} 140 -410 0 0 {name=p5 lab=inm} +C {devices/lab_pin.sym} 990 -490 2 1 {name=l1 sig_type=std_logic lab=phi1} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 790 -430 0 0 {name=M5 +L=0.5 +W=4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1050 -430 0 1 {name=M6 +L=0.5 +W=4 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 280 -500 0 1 {name=M8 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 460 -500 0 0 {name=M1 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 90 -310 0 0 {name=M14 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 280 -310 0 1 {name=M4 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 460 -310 0 0 {name=M7 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 690 -310 0 1 {name=M9 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 1010 -490 0 0 {name=M2 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 830 -490 0 1 {name=M3 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/nfet_01v8.sym} 900 -370 0 0 {name=M10 +L=0.15 +W=0.42 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {devices/iopin.sym} 140 -560 0 1 {name=p7 lab=vccd1} +C {devices/lab_pin.sym} 260 -550 0 1 {name=l6 sig_type=std_logic lab=vccd1} +C {devices/iopin.sym} 140 -540 0 1 {name=p8 lab=vssd1} +C {devices/lab_pin.sym} 190 -260 2 1 {name=l5 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 480 -550 0 1 {name=l7 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 280 -440 0 1 {name=l2 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 460 -440 0 0 {name=l3 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 580 -260 2 1 {name=l10 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 920 -320 2 1 {name=l11 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1030 -540 0 1 {name=l8 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 810 -540 0 0 {name=l9 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 920 -430 1 0 {name=l4 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1000 -400 3 0 {name=l17 sig_type=std_logic lab=tail} +C {devices/opin.sym} 1510 -220 0 0 {name=p2 lab=latch_high} +C {devices/lab_pin.sym} 1280 -220 2 1 {name=l29 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 1040 -200 0 0 {name=l33 sig_type=std_logic lab=high} +C {devices/lab_pin.sym} 1040 -110 0 0 {name=l34 sig_type=std_logic lab=low} +C {devices/lab_pin.sym} 1250 -110 1 1 {name=l35 sig_type=std_logic lab=low_buff} +C {dfxtp_1.sym} 1370 -210 0 0 {name=x6 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {buf_4.sym} 1180 -200 0 0 {name=x7 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {buf_4.sym} 1180 -110 0 0 {name=x8 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 1280 -90 1 1 {name=l28 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 1460 -90 0 1 {name=l30 sig_type=std_logic lab=latch_low + + +} +C {dfxtp_1.sym} 1370 -100 2 1 {name=x1 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {devices/opin.sym} 1320 -150 0 0 {name=p6 lab=high_buff} +C {devices/code.sym} 1230 -650 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt +.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice +" +spice_ignore=false}
diff --git a/xschem/comparator.sym b/xschem/comparator.sym new file mode 100755 index 0000000..68a1db9 --- /dev/null +++ b/xschem/comparator.sym
@@ -0,0 +1,39 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -40 130 -40 {} +L 4 -130 40 130 40 {} +L 4 -130 -40 -130 40 {} +L 4 130 -40 130 40 {} +L 4 -150 -30 -130 -30 {} +L 4 -150 -10 -130 -10 {} +L 4 -150 10 -130 10 {} +L 4 -150 30 -130 30 {} +L 4 130 10 150 10 {} +L 4 130 30 150 30 {} +L 7 130 -30 150 -30 {} +L 7 130 -10 150 -10 {} +B 5 147.5 -32.5 152.5 -27.5 {name=vccd1 dir=inout } +B 5 147.5 -12.5 152.5 -7.5 {name=vssd1 dir=inout } +B 5 -152.5 -32.5 -147.5 -27.5 {name=phi1 dir=in } +B 5 -152.5 -12.5 -147.5 -7.5 {name=phi1b dir=in } +B 5 -152.5 7.5 -147.5 12.5 {name=inp dir=in } +B 5 -152.5 27.5 -147.5 32.5 {name=inm dir=in } +B 5 147.5 7.5 152.5 12.5 {name=latch_high dir=out } +B 5 147.5 27.5 152.5 32.5 {name=high_buff dir=out } +T {@symname} -63 -6 0 0 0.3 0.3 {} +T {@name} 135 -52 0 0 0.2 0.2 {} +T {vccd1} 125 -34 0 1 0.2 0.2 {} +T {vssd1} 125 -14 0 1 0.2 0.2 {} +T {phi1} -125 -34 0 0 0.2 0.2 {} +T {phi1b} -125 -14 0 0 0.2 0.2 {} +T {inp} -125 6 0 0 0.2 0.2 {} +T {inm} -125 26 0 0 0.2 0.2 {} +T {latch_high} 125 6 0 1 0.2 0.2 {} +T {high_buff} 125 26 0 1 0.2 0.2 {}
diff --git a/xschem/core.sch b/xschem/core.sch new file mode 100644 index 0000000..d7ece5a --- /dev/null +++ b/xschem/core.sch
@@ -0,0 +1,742 @@ +v {xschem version=3.1.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 2460 -1200 2500 -1200 { +lab=col0} +N 2460 -1200 2460 -1110 { +lab=col0} +N 2420 -1240 2420 -1110 { +lab=col2} +N 2400 -1260 2400 -1110 { +lab=col3} +N 2380 -1280 2380 -1110 { +lab=col4} +N 2260 -1400 2260 -1110 { +lab=col10} +N 2240 -1420 2240 -1110 { +lab=col11} +N 2220 -1440 2220 -1110 { +lab=col12} +N 2200 -1460 2200 -1110 { +lab=col13} +N 2180 -1480 2180 -1110 { +lab=col14} +N 2440 -1220 2500 -1220 { +lab=col1} +N 2360 -1300 2360 -1110 { +lab=col5} +N 2340 -1320 2340 -1110 { +lab=col6} +N 2320 -1340 2320 -1110 { +lab=col7} +N 2300 -1360 2300 -1110 { +lab=col8} +N 2280 -1380 2280 -1110 { +lab=col9} +N 2160 -1500 2160 -1110 { +lab=col15} +N 2420 -1240 2500 -1240 { +lab=col2} +N 2400 -1260 2500 -1260 { +lab=col3} +N 2380 -1280 2500 -1280 { +lab=col4} +N 2360 -1300 2500 -1300 { +lab=col5} +N 2340 -1320 2500 -1320 { +lab=col6} +N 2320 -1340 2500 -1340 { +lab=col7} +N 2300 -1360 2500 -1360 { +lab=col8} +N 2280 -1380 2500 -1380 { +lab=col9} +N 2260 -1400 2500 -1400 { +lab=col10} +N 2240 -1420 2500 -1420 { +lab=col11} +N 2220 -1440 2500 -1440 { +lab=col12} +N 2200 -1460 2500 -1460 { +lab=col13} +N 2180 -1480 2500 -1480 { +lab=col14} +N 2160 -1500 2500 -1500 { +lab=col15} +N 2440 -1220 2440 -1110 { +lab=col1} +N 2000 -1520 2500 -1520 { +lab=vssd1} +N 2510 -610 2510 -510 { +lab=vdda1} +N 2530 -610 2530 -510 { +lab=vccd1} +N 2550 -610 2550 -510 { +lab=vssd1} +N 2490 -610 2490 -510 { +lab=Vcminus} +N 2470 -610 2470 -510 { +lab=Vcplus} +N 2450 -610 2450 -510 { +lab=Vref} +N 2130 -610 2130 -510 { +lab=col0} +N 2150 -610 2150 -510 { +lab=col1} +N 2170 -610 2170 -510 { +lab=col2} +N 2190 -610 2190 -510 { +lab=col3} +N 2210 -610 2210 -510 { +lab=col4} +N 2230 -610 2230 -510 { +lab=col5} +N 2250 -610 2250 -510 { +lab=col6} +N 2270 -610 2270 -510 { +lab=col7} +N 2290 -610 2290 -510 { +lab=col8} +N 2310 -610 2310 -510 { +lab=col9} +N 2330 -610 2330 -510 { +lab=col10} +N 2350 -610 2350 -510 { +lab=col11} +N 2370 -610 2370 -510 { +lab=col12} +N 2390 -610 2390 -510 { +lab=col13} +N 2410 -610 2410 -510 { +lab=col14} +N 2430 -610 2430 -510 { +lab=col15} +N 2000 -2160 2500 -2160 { +lab=WL_out15} +N 2000 -2140 2500 -2140 { +lab=row15} +N 2000 -2120 2500 -2120 { +lab=WL_out14} +N 2000 -2100 2500 -2100 { +lab=row14} +N 2000 -2080 2500 -2080 { +lab=WL_out13} +N 2000 -2060 2500 -2060 { +lab=row13} +N 2000 -2040 2500 -2040 { +lab=WL_out12} +N 2000 -2020 2500 -2020 { +lab=row12} +N 2000 -2000 2500 -2000 { +lab=WL_out11} +N 2000 -1980 2500 -1980 { +lab=row11} +N 2000 -1960 2500 -1960 { +lab=WL_out10} +N 2000 -1940 2500 -1940 { +lab=row10} +N 2000 -1920 2500 -1920 { +lab=WL_out9} +N 2000 -1900 2500 -1900 { +lab=row9} +N 2000 -1880 2500 -1880 { +lab=WL_out8} +N 2000 -1860 2500 -1860 { +lab=row8} +N 2000 -1840 2500 -1840 { +lab=WL_out7} +N 2000 -1820 2500 -1820 { +lab=row7} +N 2000 -1800 2500 -1800 { +lab=WL_out6} +N 2000 -1780 2500 -1780 { +lab=row6} +N 2000 -1760 2500 -1760 { +lab=WL_out5} +N 2000 -1740 2500 -1740 { +lab=row5} +N 2000 -1720 2500 -1720 { +lab=WL_out4} +N 2000 -1700 2500 -1700 { +lab=row4} +N 2000 -1680 2500 -1680 { +lab=WL_out3} +N 2000 -1660 2500 -1660 { +lab=row3} +N 2000 -1640 2500 -1640 { +lab=WL_out2} +N 2000 -1620 2500 -1620 { +lab=row2} +N 2000 -1600 2500 -1600 { +lab=WL_out1} +N 2000 -1580 2500 -1580 { +lab=row1} +N 2000 -1560 2500 -1560 { +lab=WL_out0} +N 2000 -1540 2500 -1540 { +lab=row0} +N 1390 -2050 1490 -2050 { +lab=vccd1} +N 1390 -1950 1490 -1950 { +lab=vdda1} +N 1390 -2030 1490 -2030 { +lab=Vref} +N 1390 -2010 1490 -2010 { +lab=Vrminus} +N 1390 -1990 1490 -1990 { +lab=Vrplus} +N 1390 -1970 1490 -1970 { +lab=vssd1} +N 1390 -2070 1490 -2070 { +lab=Vsample} +N 990 -2290 1090 -2290 { +lab=SAMPLE_3.3} +N 990 -2310 1090 -2310 { +lab=SAMPLEb_3.3} +N 990 -2330 1090 -2330 { +lab=WR_3.3} +N 990 -2350 1090 -2350 { +lab=Vgpr} +N 990 -2370 1090 -2370 { +lab=Vgnr} +N 1390 -2270 1490 -2270 { +lab=row9} +N 1390 -2310 1490 -2310 { +lab=row11} +N 1390 -2330 1490 -2330 { +lab=row12} +N 1390 -2250 1490 -2250 { +lab=row8} +N 1390 -2230 1490 -2230 { +lab=row7} +N 1390 -2210 1490 -2210 { +lab=row6} +N 1390 -2290 1490 -2290 { +lab=row10} +N 1390 -2190 1490 -2190 { +lab=row5} +N 1390 -2170 1490 -2170 { +lab=row4} +N 1390 -2150 1490 -2150 { +lab=row3} +N 1390 -2130 1490 -2130 { +lab=row2} +N 1390 -2110 1490 -2110 { +lab=row1} +N 1390 -2090 1490 -2090 { +lab=row0} +N 1390 -2370 1490 -2370 { +lab=row14} +N 1390 -2390 1490 -2390 { +lab=row15} +N 1390 -2350 1490 -2350 { +lab=row13} +N 1030 -1630 1090 -1630 { +lab=A0r} +N 1030 -1650 1090 -1650 { +lab=B0r} +N 1030 -1670 1090 -1670 { +lab=A1r} +N 1030 -1690 1090 -1690 { +lab=B1r} +N 1030 -1710 1090 -1710 { +lab=A2r} +N 1030 -1730 1090 -1730 { +lab=B2r} +N 1030 -1750 1090 -1750 { +lab=A3r} +N 1030 -1770 1090 -1770 { +lab=B3r} +N 1030 -1790 1090 -1790 { +lab=A4r} +N 1030 -1810 1090 -1810 { +lab=B4r} +N 1030 -1830 1090 -1830 { +lab=A5r} +N 1030 -1850 1090 -1850 { +lab=B5r} +N 1030 -1870 1090 -1870 { +lab=A6r} +N 1030 -1890 1090 -1890 { +lab=B6r} +N 1030 -1910 1090 -1910 { +lab=A7r} +N 1030 -1930 1090 -1930 { +lab=B7r} +N 1030 -1950 1090 -1950 { +lab=A8r} +N 1030 -1970 1090 -1970 { +lab=B8r} +N 1030 -1990 1090 -1990 { +lab=A9r} +N 1030 -2010 1090 -2010 { +lab=B9r} +N 1030 -2030 1090 -2030 { +lab=A10r} +N 1030 -2050 1090 -2050 { +lab=B10r} +N 1030 -2070 1090 -2070 { +lab=A11r} +N 1030 -2090 1090 -2090 { +lab=B11r} +N 1030 -2110 1090 -2110 { +lab=A12r} +N 1030 -2130 1090 -2130 { +lab=B12r} +N 1030 -2150 1090 -2150 { +lab=A13r} +N 1030 -2170 1090 -2170 { +lab=B13r} +N 1030 -2190 1090 -2190 { +lab=A14r} +N 1030 -2210 1090 -2210 { +lab=B14r} +N 1030 -2230 1090 -2230 { +lab=A15r} +N 1700 -1810 1800 -1810 { +lab=Vsample} +N 1700 -1790 1800 -1790 { +lab=vssd1} +N 990 -2270 1090 -2270 { +lab=WRb_3.3} +N 1030 -2250 1090 -2250 { +lab=B15r} +N 990 -2390 1090 -2390 { +lab=SEL} +N 2130 -210 2130 -150 { +lab=A0c} +N 2150 -210 2150 -150 { +lab=B0c} +N 2170 -210 2170 -150 { +lab=A1c} +N 2190 -210 2190 -150 { +lab=B1c} +N 2210 -210 2210 -150 { +lab=A2c} +N 2230 -210 2230 -150 { +lab=B2c} +N 2250 -210 2250 -150 { +lab=A3c} +N 2270 -210 2270 -150 { +lab=B3c} +N 2290 -210 2290 -150 { +lab=A4c} +N 2310 -210 2310 -150 { +lab=B4c} +N 2330 -210 2330 -150 { +lab=A5c} +N 2350 -210 2350 -150 { +lab=B5c} +N 2370 -210 2370 -150 { +lab=A6c} +N 2390 -210 2390 -150 { +lab=B6c} +N 2410 -210 2410 -150 { +lab=A7c} +N 2430 -210 2430 -150 { +lab=B7c} +N 2450 -210 2450 -150 { +lab=A8c} +N 2470 -210 2470 -150 { +lab=B8c} +N 2490 -210 2490 -150 { +lab=A9c} +N 2510 -210 2510 -150 { +lab=B9c} +N 2530 -210 2530 -150 { +lab=A10c} +N 2550 -210 2550 -150 { +lab=B10c} +N 2570 -210 2570 -150 { +lab=A11c} +N 2590 -210 2590 -150 { +lab=B11c} +N 2610 -210 2610 -150 { +lab=A12c} +N 2630 -210 2630 -150 { +lab=B12c} +N 2650 -210 2650 -150 { +lab=A13c} +N 2670 -210 2670 -150 { +lab=B13c} +N 2690 -210 2690 -150 { +lab=A14c} +N 2710 -210 2710 -150 { +lab=B14c} +N 2730 -210 2730 -150 { +lab=A15c} +N 2750 -210 2750 -150 { +lab=B15c} +N 2770 -210 2770 -150 { +lab=SEL} +N 1390 -1500 1490 -1500 { +lab=vccd1} +N 1390 -1520 1490 -1520 { +lab=vdda1} +N 1390 -1480 1490 -1480 { +lab=vssd1} +N 1030 -1200 1090 -1200 { +lab=SEL} +N 1030 -1220 1090 -1220 { +lab=WL0} +N 1030 -1240 1090 -1240 { +lab=WL1} +N 1030 -1260 1090 -1260 { +lab=WL2} +N 1030 -1280 1090 -1280 { +lab=WL3} +N 1030 -1300 1090 -1300 { +lab=WL4} +N 1030 -1320 1090 -1320 { +lab=WL5} +N 1030 -1340 1090 -1340 { +lab=WL6} +N 1030 -1360 1090 -1360 { +lab=WL7} +N 1030 -1380 1090 -1380 { +lab=WL8} +N 1030 -1400 1090 -1400 { +lab=WL9} +N 1030 -1420 1090 -1420 { +lab=WL10} +N 1030 -1440 1090 -1440 { +lab=WL11} +N 1030 -1460 1090 -1460 { +lab=WL12} +N 1030 -1480 1090 -1480 { +lab=WL13} +N 1030 -1500 1090 -1500 { +lab=WL14} +N 1030 -1520 1090 -1520 { +lab=WL15} +N 1390 -1440 1490 -1440 { +lab=WL_out14} +N 1390 -1460 1490 -1460 { +lab=WL_out15} +N 1390 -1420 1490 -1420 { +lab=WL_out13} +N 1390 -1400 1490 -1400 { +lab=WL_out12} +N 1390 -1360 1490 -1360 { +lab=WL_out10} +N 1390 -1380 1490 -1380 { +lab=WL_out11} +N 1390 -1340 1490 -1340 { +lab=WL_out9} +N 1390 -1320 1490 -1320 { +lab=WL_out8} +N 1390 -1280 1490 -1280 { +lab=WL_out6} +N 1390 -1300 1490 -1300 { +lab=WL_out7} +N 1390 -1260 1490 -1260 { +lab=WL_out5} +N 1390 -1240 1490 -1240 { +lab=WL_out4} +N 1390 -1200 1490 -1200 { +lab=WL_out2} +N 1390 -1220 1490 -1220 { +lab=WL_out3} +N 1390 -1180 1490 -1180 { +lab=WL_out1} +N 1390 -1160 1490 -1160 { +lab=WL_out0} +N 310 -2360 410 -2360 { +lab=WR} +N 310 -2190 410 -2190 { +lab=SAMPLE} +N 310 -2340 410 -2340 { +lab=SEL} +N 310 -2170 410 -2170 { +lab=SEL} +N 400 -2530 510 -2530 { +lab=row_sel} +N 400 -2490 510 -2490 { +lab=col_sel} +N 630 -2510 750 -2510 { +lab=SEL} +N 1340 -850 1430 -850 { +lab=phi1} +N 1340 -830 1430 -830 { +lab=phi1b} +N 1340 -810 1430 -810 { +lab=Vsample} +N 1340 -790 1430 -790 { +lab=Vref_comp} +N 1730 -850 1790 -850 { +lab=vccd1} +N 1730 -830 1790 -830 { +lab=vssd1} +N 1730 -810 1790 -810 { +lab=#net1} +N 760 -830 810 -830 { +lab=RISC_CLK} +N 890 -830 970 -830 { +lab=phi1b} +N 1050 -830 1120 -830 { +lab=phi1} +N 2250 -810 2330 -810 { +lab=vssd1} +N 2250 -790 2320 -790 { +lab=latch_high} +N 1790 -810 1950 -810 { +lab=#net1} +N 2250 -830 2330 -830 { +lab=vccd1} +C {devices/iopin.sym} 2510 -610 3 0 {name=p1 lab=vdda1} +C {devices/iopin.sym} 2550 -610 1 1 {name=p2 lab=vssd1} +C {devices/ipin.sym} 2450 -610 1 0 {name=p5 lab=Vref} +C {devices/ipin.sym} 2470 -610 1 0 {name=p6 lab=Vcplus} +C {devices/ipin.sym} 2490 -610 1 0 {name=p7 lab=Vcminus} +C {devices/lab_pin.sym} 2130 -610 1 0 {name=l1 sig_type=std_logic lab=col0} +C {1T1R_16x16.sym} 2650 -1680 0 1 {name=x1} +C {devices/lab_pin.sym} 2460 -1110 1 1 {name=l17 sig_type=std_logic lab=col0} +C {devices/lab_pin.sym} 2440 -1110 3 0 {name=l18 sig_type=std_logic lab=col1} +C {devices/lab_pin.sym} 2420 -1110 1 1 {name=l19 sig_type=std_logic lab=col2} +C {devices/lab_pin.sym} 2400 -1110 3 0 {name=l20 sig_type=std_logic lab=col3} +C {devices/lab_pin.sym} 2380 -1110 1 1 {name=l21 sig_type=std_logic lab=col4} +C {devices/lab_pin.sym} 2360 -1110 1 1 {name=l22 sig_type=std_logic lab=col5} +C {devices/lab_pin.sym} 2340 -1110 1 1 {name=l23 sig_type=std_logic lab=col6} +C {devices/lab_pin.sym} 2320 -1110 1 1 {name=l24 sig_type=std_logic lab=col7} +C {devices/lab_pin.sym} 2300 -1110 1 1 {name=l25 sig_type=std_logic lab=col8} +C {devices/lab_pin.sym} 2280 -1110 1 1 {name=l26 sig_type=std_logic lab=col9} +C {devices/lab_pin.sym} 2260 -1110 1 1 {name=l27 sig_type=std_logic lab=col10} +C {devices/lab_pin.sym} 2240 -1110 1 1 {name=l28 sig_type=std_logic lab=col11} +C {devices/lab_pin.sym} 2220 -1110 1 1 {name=l29 sig_type=std_logic lab=col12} +C {devices/lab_pin.sym} 2200 -1110 1 1 {name=l30 sig_type=std_logic lab=col13} +C {devices/lab_pin.sym} 2180 -1110 1 1 {name=l31 sig_type=std_logic lab=col14} +C {devices/lab_pin.sym} 2160 -1110 1 1 {name=l32 sig_type=std_logic lab=col15} +C {col_drivers_1x16.sym} 2450 -360 3 0 {name=x133} +C {devices/iopin.sym} 2530 -610 3 0 {name=p3 lab=vccd1} +C {devices/lab_pin.sym} 2150 -610 1 0 {name=l34 sig_type=std_logic lab=col1} +C {devices/lab_pin.sym} 2170 -610 1 0 {name=l35 sig_type=std_logic lab=col2} +C {devices/lab_pin.sym} 2190 -610 1 0 {name=l36 sig_type=std_logic lab=col3} +C {devices/lab_pin.sym} 2210 -610 1 0 {name=l37 sig_type=std_logic lab=col4} +C {devices/lab_pin.sym} 2230 -610 1 0 {name=l38 sig_type=std_logic lab=col5} +C {devices/lab_pin.sym} 2250 -610 1 0 {name=l2 sig_type=std_logic lab=col6} +C {devices/lab_pin.sym} 2270 -610 1 0 {name=l3 sig_type=std_logic lab=col7} +C {devices/lab_pin.sym} 2290 -610 1 0 {name=l4 sig_type=std_logic lab=col8} +C {devices/lab_pin.sym} 2310 -610 1 0 {name=l5 sig_type=std_logic lab=col9} +C {devices/lab_pin.sym} 2330 -610 1 0 {name=l6 sig_type=std_logic lab=col10} +C {devices/lab_pin.sym} 2350 -610 1 0 {name=l7 sig_type=std_logic lab=col11} +C {devices/lab_pin.sym} 2370 -610 1 0 {name=l8 sig_type=std_logic lab=col12} +C {devices/lab_pin.sym} 2390 -610 1 0 {name=l9 sig_type=std_logic lab=col13} +C {devices/lab_pin.sym} 2410 -610 1 0 {name=l10 sig_type=std_logic lab=col14} +C {devices/lab_pin.sym} 2430 -610 1 0 {name=l11 sig_type=std_logic lab=col15} +C {row_drivers_16x1.sym} 1240 -2010 0 0 {name=x2} +C {devices/lab_pin.sym} 2000 -1540 2 1 {name=l247 sig_type=std_logic lab=row0} +C {devices/lab_pin.sym} 2000 -1580 2 1 {name=l248 sig_type=std_logic lab=row1} +C {devices/lab_pin.sym} 2000 -1620 2 1 {name=l249 sig_type=std_logic lab=row2} +C {devices/lab_pin.sym} 2000 -1660 2 1 {name=l250 sig_type=std_logic lab=row3} +C {devices/lab_pin.sym} 2000 -1700 2 1 {name=l251 sig_type=std_logic lab=row4} +C {devices/lab_pin.sym} 2000 -1740 2 1 {name=l252 sig_type=std_logic lab=row5} +C {devices/lab_pin.sym} 2000 -1780 2 1 {name=l253 sig_type=std_logic lab=row6} +C {devices/lab_pin.sym} 2000 -1820 2 1 {name=l254 sig_type=std_logic lab=row7} +C {devices/lab_pin.sym} 2000 -1860 2 1 {name=l255 sig_type=std_logic lab=row8} +C {devices/lab_pin.sym} 2000 -1900 2 1 {name=l256 sig_type=std_logic lab=row9} +C {devices/lab_pin.sym} 2000 -1940 2 1 {name=l257 sig_type=std_logic lab=row10} +C {devices/lab_pin.sym} 2000 -1980 2 1 {name=l258 sig_type=std_logic lab=row11} +C {devices/lab_pin.sym} 2000 -2020 2 1 {name=l259 sig_type=std_logic lab=row12} +C {devices/lab_pin.sym} 2000 -2060 2 1 {name=l260 sig_type=std_logic lab=row13} +C {devices/lab_pin.sym} 2000 -2100 2 1 {name=l261 sig_type=std_logic lab=row14} +C {devices/lab_pin.sym} 2000 -2140 2 1 {name=l262 sig_type=std_logic lab=row15} +C {devices/ipin.sym} 1490 -1990 2 0 {name=p11 lab=Vrplus} +C {devices/ipin.sym} 1490 -2010 2 0 {name=p17 lab=Vrminus} +C {devices/lab_pin.sym} 1490 -1970 2 0 {name=l13 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1490 -2050 2 0 {name=l14 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1490 -1950 2 0 {name=l15 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 1490 -2030 2 0 {name=l16 sig_type=std_logic lab=Vref} +C {devices/ipin.sym} 990 -2350 0 0 {name=p21 lab=Vgpr} +C {devices/lab_pin.sym} 1490 -2090 2 0 {name=l39 sig_type=std_logic lab=row0} +C {devices/lab_pin.sym} 1490 -2110 2 0 {name=l40 sig_type=std_logic lab=row1} +C {devices/lab_pin.sym} 1490 -2130 2 0 {name=l41 sig_type=std_logic lab=row2} +C {devices/lab_pin.sym} 1490 -2150 2 0 {name=l42 sig_type=std_logic lab=row3} +C {devices/lab_pin.sym} 1490 -2170 2 0 {name=l43 sig_type=std_logic lab=row4} +C {devices/lab_pin.sym} 1490 -2190 2 0 {name=l44 sig_type=std_logic lab=row5} +C {devices/lab_pin.sym} 1490 -2210 2 0 {name=l45 sig_type=std_logic lab=row6} +C {devices/lab_pin.sym} 1490 -2230 2 0 {name=l46 sig_type=std_logic lab=row7} +C {devices/lab_pin.sym} 1490 -2250 2 0 {name=l47 sig_type=std_logic lab=row8} +C {devices/lab_pin.sym} 1490 -2270 2 0 {name=l48 sig_type=std_logic lab=row9} +C {devices/lab_pin.sym} 1490 -2290 2 0 {name=l49 sig_type=std_logic lab=row10} +C {devices/lab_pin.sym} 1490 -2310 2 0 {name=l50 sig_type=std_logic lab=row11} +C {devices/lab_pin.sym} 1490 -2330 2 0 {name=l51 sig_type=std_logic lab=row12} +C {devices/lab_pin.sym} 1490 -2350 2 0 {name=l52 sig_type=std_logic lab=row13} +C {devices/lab_pin.sym} 1490 -2370 2 0 {name=l53 sig_type=std_logic lab=row14} +C {devices/lab_pin.sym} 1490 -2390 2 0 {name=l54 sig_type=std_logic lab=row15} +C {devices/ipin.sym} 1030 -1630 2 1 {name=p22 sig_type=std_logic lab=A0r} +C {devices/ipin.sym} 1030 -1670 2 1 {name=p23 sig_type=std_logic lab=A1r} +C {devices/ipin.sym} 1030 -1710 2 1 {name=p24 sig_type=std_logic lab=A2r} +C {devices/ipin.sym} 1030 -1750 2 1 {name=p25 sig_type=std_logic lab=A3r} +C {devices/ipin.sym} 1030 -1790 2 1 {name=p26 sig_type=std_logic lab=A4r} +C {devices/ipin.sym} 1030 -1830 2 1 {name=p27 sig_type=std_logic lab=A5r} +C {devices/ipin.sym} 1030 -1870 2 1 {name=p28 sig_type=std_logic lab=A6r} +C {devices/ipin.sym} 1030 -1910 2 1 {name=p29 sig_type=std_logic lab=A7r} +C {devices/ipin.sym} 1030 -1950 2 1 {name=p30 sig_type=std_logic lab=A8r} +C {devices/ipin.sym} 1030 -1990 2 1 {name=p31 sig_type=std_logic lab=A9r} +C {devices/ipin.sym} 1030 -2030 2 1 {name=p32 sig_type=std_logic lab=A10r} +C {devices/ipin.sym} 1030 -2070 2 1 {name=p33 sig_type=std_logic lab=A11r} +C {devices/ipin.sym} 1030 -2110 2 1 {name=p34 sig_type=std_logic lab=A12r} +C {devices/ipin.sym} 1030 -2150 2 1 {name=p35 sig_type=std_logic lab=A13r} +C {devices/ipin.sym} 1030 -2190 2 1 {name=p36 sig_type=std_logic lab=A14r} +C {devices/ipin.sym} 1030 -2230 2 1 {name=p37 sig_type=std_logic lab=A15r} +C {devices/ipin.sym} 1030 -1650 2 1 {name=p38 sig_type=std_logic lab=B0r} +C {devices/ipin.sym} 1030 -1690 2 1 {name=p59 sig_type=std_logic lab=B1r} +C {devices/ipin.sym} 1030 -1730 2 1 {name=p66 sig_type=std_logic lab=B2r} +C {devices/ipin.sym} 1030 -1770 2 1 {name=p67 sig_type=std_logic lab=B3r} +C {devices/ipin.sym} 1030 -1810 2 1 {name=p68 sig_type=std_logic lab=B4r} +C {devices/ipin.sym} 1030 -1850 2 1 {name=p69 sig_type=std_logic lab=B5r} +C {devices/ipin.sym} 1030 -1890 2 1 {name=p70 sig_type=std_logic lab=B6r} +C {devices/ipin.sym} 1030 -1930 2 1 {name=p71 sig_type=std_logic lab=B7r} +C {devices/ipin.sym} 1030 -1970 2 1 {name=p72 sig_type=std_logic lab=B8r} +C {devices/ipin.sym} 1030 -2050 2 1 {name=p73 sig_type=std_logic lab=B10r} +C {devices/ipin.sym} 1030 -2090 2 1 {name=p74 sig_type=std_logic lab=B11r} +C {devices/ipin.sym} 1030 -2130 2 1 {name=p75 sig_type=std_logic lab=B12r} +C {devices/ipin.sym} 1030 -2170 2 1 {name=p76 sig_type=std_logic lab=B13r} +C {devices/ipin.sym} 1030 -2210 2 1 {name=p77 sig_type=std_logic lab=B14r} +C {devices/ipin.sym} 1030 -2250 2 1 {name=p19 sig_type=std_logic lab=B15r} +C {devices/ipin.sym} 1030 -2010 2 1 {name=p79 sig_type=std_logic lab=B9r} +C {mimcap_stacked_57x50.sym} 1550 -1800 0 0 {name=x3} +C {devices/lab_pin.sym} 1490 -2070 2 0 {name=l55 sig_type=std_logic lab=Vsample} +C {devices/lab_pin.sym} 1800 -1810 2 0 {name=l56 sig_type=std_logic lab=Vsample} +C {devices/lab_pin.sym} 1800 -1790 2 0 {name=l57 sig_type=std_logic lab=vssd1} +C {devices/ipin.sym} 990 -2370 0 0 {name=p8 lab=Vgnr} +C {devices/ipin.sym} 2130 -150 1 1 {name=p80 sig_type=std_logic lab=A0c} +C {devices/ipin.sym} 2170 -150 1 1 {name=p81 sig_type=std_logic lab=A1c} +C {devices/ipin.sym} 2210 -150 1 1 {name=p82 sig_type=std_logic lab=A2c} +C {devices/ipin.sym} 2250 -150 1 1 {name=p83 sig_type=std_logic lab=A3c} +C {devices/ipin.sym} 2290 -150 1 1 {name=p84 sig_type=std_logic lab=A4c} +C {devices/ipin.sym} 2330 -150 1 1 {name=p85 sig_type=std_logic lab=A5c} +C {devices/ipin.sym} 2370 -150 1 1 {name=p86 sig_type=std_logic lab=A6c} +C {devices/ipin.sym} 2410 -150 1 1 {name=p87 sig_type=std_logic lab=A7c} +C {devices/ipin.sym} 2450 -150 1 1 {name=p88 sig_type=std_logic lab=A8c} +C {devices/ipin.sym} 2490 -150 1 1 {name=p89 sig_type=std_logic lab=A9c} +C {devices/ipin.sym} 2530 -150 1 1 {name=p90 sig_type=std_logic lab=A10c} +C {devices/ipin.sym} 2570 -150 1 1 {name=p91 sig_type=std_logic lab=A11c} +C {devices/ipin.sym} 2610 -150 1 1 {name=p92 sig_type=std_logic lab=A12c} +C {devices/ipin.sym} 2650 -150 1 1 {name=p93 sig_type=std_logic lab=A13c} +C {devices/ipin.sym} 2690 -150 1 1 {name=p94 sig_type=std_logic lab=A14c} +C {devices/ipin.sym} 2730 -150 1 1 {name=p95 sig_type=std_logic lab=A15c} +C {devices/ipin.sym} 2150 -150 1 1 {name=p96 sig_type=std_logic lab=B0c} +C {devices/ipin.sym} 2190 -150 1 1 {name=p97 sig_type=std_logic lab=B1c} +C {devices/ipin.sym} 2230 -150 1 1 {name=p98 sig_type=std_logic lab=B2c} +C {devices/ipin.sym} 2270 -150 1 1 {name=p99 sig_type=std_logic lab=B3c} +C {devices/ipin.sym} 2310 -150 1 1 {name=p100 sig_type=std_logic lab=B4c} +C {devices/ipin.sym} 2350 -150 1 1 {name=p101 sig_type=std_logic lab=B5c} +C {devices/ipin.sym} 2390 -150 1 1 {name=p102 sig_type=std_logic lab=B6c} +C {devices/ipin.sym} 2430 -150 1 1 {name=p103 sig_type=std_logic lab=B7c} +C {devices/ipin.sym} 2470 -150 1 1 {name=p104 sig_type=std_logic lab=B8c} +C {devices/ipin.sym} 2550 -150 1 1 {name=p105 sig_type=std_logic lab=B10c} +C {devices/ipin.sym} 2590 -150 1 1 {name=p106 sig_type=std_logic lab=B11c} +C {devices/ipin.sym} 2630 -150 1 1 {name=p107 sig_type=std_logic lab=B12c} +C {devices/ipin.sym} 2670 -150 1 1 {name=p108 sig_type=std_logic lab=B13c} +C {devices/ipin.sym} 2710 -150 1 1 {name=p109 sig_type=std_logic lab=B14c} +C {devices/ipin.sym} 2750 -150 1 1 {name=p110 sig_type=std_logic lab=B15c} +C {devices/ipin.sym} 2510 -150 1 1 {name=p111 sig_type=std_logic lab=B9c} +C {devices/lab_pin.sym} 2770 -150 3 0 {name=l58 sig_type=std_logic lab=SEL} +C {WL_drivers_16x1.sym} 1240 -1340 0 0 {name=x4} +C {devices/lab_pin.sym} 1490 -1480 2 0 {name=l75 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1490 -1500 2 0 {name=l76 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1490 -1520 2 0 {name=l77 sig_type=std_logic lab=vdda1} +C {devices/ipin.sym} 1030 -1220 2 1 {name=p4 sig_type=std_logic lab=WL0} +C {devices/lab_pin.sym} 1030 -1200 0 0 {name=l78 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1490 -1460 0 1 {name=l79 sig_type=std_logic lab=WL_out15} +C {devices/lab_pin.sym} 2000 -2160 2 1 {name=l59 sig_type=std_logic lab=WL_out15} +C {devices/lab_pin.sym} 2000 -2120 2 1 {name=l60 sig_type=std_logic lab=WL_out14} +C {devices/lab_pin.sym} 2000 -2080 2 1 {name=l61 sig_type=std_logic lab=WL_out13} +C {devices/lab_pin.sym} 2000 -2040 2 1 {name=l62 sig_type=std_logic lab=WL_out12} +C {devices/lab_pin.sym} 2000 -2000 2 1 {name=l63 sig_type=std_logic lab=WL_out11} +C {devices/lab_pin.sym} 2000 -1960 2 1 {name=l64 sig_type=std_logic lab=WL_out10} +C {devices/lab_pin.sym} 2000 -1920 2 1 {name=l65 sig_type=std_logic lab=WL_out9} +C {devices/lab_pin.sym} 2000 -1880 2 1 {name=l66 sig_type=std_logic lab=WL_out8} +C {devices/lab_pin.sym} 2000 -1840 2 1 {name=l67 sig_type=std_logic lab=WL_out7} +C {devices/lab_pin.sym} 2000 -1800 2 1 {name=l68 sig_type=std_logic lab=WL_out6} +C {devices/lab_pin.sym} 2000 -1760 2 1 {name=l69 sig_type=std_logic lab=WL_out5} +C {devices/lab_pin.sym} 2000 -1720 2 1 {name=l70 sig_type=std_logic lab=WL_out4} +C {devices/lab_pin.sym} 2000 -1680 2 1 {name=l71 sig_type=std_logic lab=WL_out3} +C {devices/lab_pin.sym} 2000 -1640 2 1 {name=l72 sig_type=std_logic lab=WL_out2} +C {devices/lab_pin.sym} 2000 -1600 2 1 {name=l73 sig_type=std_logic lab=WL_out1} +C {devices/lab_pin.sym} 2000 -1560 2 1 {name=l74 sig_type=std_logic lab=WL_out0} +C {devices/ipin.sym} 1030 -1240 2 1 {name=p12 sig_type=std_logic lab=WL1} +C {devices/ipin.sym} 1030 -1260 2 1 {name=p13 sig_type=std_logic lab=WL2} +C {devices/ipin.sym} 1030 -1280 2 1 {name=p14 sig_type=std_logic lab=WL3} +C {devices/ipin.sym} 1030 -1300 2 1 {name=p15 sig_type=std_logic lab=WL4} +C {devices/ipin.sym} 1030 -1320 2 1 {name=p16 sig_type=std_logic lab=WL5} +C {devices/ipin.sym} 1030 -1340 2 1 {name=p39 sig_type=std_logic lab=WL6} +C {devices/ipin.sym} 1030 -1360 2 1 {name=p40 sig_type=std_logic lab=WL7} +C {devices/ipin.sym} 1030 -1380 2 1 {name=p41 sig_type=std_logic lab=WL8} +C {devices/ipin.sym} 1030 -1400 2 1 {name=p42 sig_type=std_logic lab=WL9} +C {devices/ipin.sym} 1030 -1420 2 1 {name=p43 sig_type=std_logic lab=WL10} +C {devices/ipin.sym} 1030 -1440 2 1 {name=p44 sig_type=std_logic lab=WL11} +C {devices/ipin.sym} 1030 -1460 2 1 {name=p45 sig_type=std_logic lab=WL12} +C {devices/ipin.sym} 1030 -1480 2 1 {name=p46 sig_type=std_logic lab=WL13} +C {devices/ipin.sym} 1030 -1500 2 1 {name=p47 sig_type=std_logic lab=WL14} +C {devices/ipin.sym} 1030 -1520 2 1 {name=p48 sig_type=std_logic lab=WL15} +C {devices/lab_pin.sym} 1490 -1440 0 1 {name=l80 sig_type=std_logic lab=WL_out14} +C {devices/lab_pin.sym} 1490 -1420 0 1 {name=l81 sig_type=std_logic lab=WL_out13} +C {devices/lab_pin.sym} 1490 -1400 0 1 {name=l82 sig_type=std_logic lab=WL_out12} +C {devices/lab_pin.sym} 1490 -1380 0 1 {name=l83 sig_type=std_logic lab=WL_out11} +C {devices/lab_pin.sym} 1490 -1360 0 1 {name=l84 sig_type=std_logic lab=WL_out10} +C {devices/lab_pin.sym} 1490 -1340 0 1 {name=l85 sig_type=std_logic lab=WL_out9} +C {devices/lab_pin.sym} 1490 -1320 0 1 {name=l86 sig_type=std_logic lab=WL_out8} +C {devices/lab_pin.sym} 1490 -1300 0 1 {name=l87 sig_type=std_logic lab=WL_out7} +C {devices/lab_pin.sym} 1490 -1280 0 1 {name=l88 sig_type=std_logic lab=WL_out6} +C {devices/lab_pin.sym} 1490 -1260 0 1 {name=l89 sig_type=std_logic lab=WL_out5} +C {devices/lab_pin.sym} 1490 -1240 0 1 {name=l90 sig_type=std_logic lab=WL_out4} +C {devices/lab_pin.sym} 1490 -1220 0 1 {name=l91 sig_type=std_logic lab=WL_out3} +C {devices/lab_pin.sym} 1490 -1200 0 1 {name=l92 sig_type=std_logic lab=WL_out2} +C {devices/lab_pin.sym} 1490 -1180 0 1 {name=l93 sig_type=std_logic lab=WL_out1} +C {devices/lab_pin.sym} 1490 -1160 0 1 {name=l94 sig_type=std_logic lab=WL_out0} +C {and_level_up_shifter_x4.sym} 560 -2320 0 0 {name=x5} +C {and_level_up_shifter_x4.sym} 560 -2150 0 0 {name=x6} +C {devices/ipin.sym} 310 -2360 0 0 {name=p49 lab=WR} +C {devices/ipin.sym} 310 -2190 0 0 {name=p50 lab=SAMPLE} +C {devices/lab_pin.sym} 310 -2340 0 0 {name=l95 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 310 -2170 0 0 {name=l96 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 710 -2320 2 0 {name=l97 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 710 -2360 2 0 {name=l98 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 710 -2340 2 0 {name=l99 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 710 -2300 0 1 {name=l100 sig_type=std_logic lab=WRb_3.3} +C {devices/lab_pin.sym} 710 -2280 0 1 {name=l101 sig_type=std_logic lab=WR_3.3} +C {devices/lab_pin.sym} 990 -2330 0 0 {name=l102 sig_type=std_logic lab=WR_3.3} +C {devices/lab_pin.sym} 990 -2270 0 0 {name=l103 sig_type=std_logic lab=WRb_3.3} +C {devices/lab_pin.sym} 710 -2150 2 0 {name=l104 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 710 -2190 2 0 {name=l105 sig_type=std_logic lab=vdda1} +C {devices/lab_pin.sym} 710 -2170 2 0 {name=l106 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 710 -2130 0 1 {name=l107 sig_type=std_logic lab=SAMPLEb_3.3} +C {devices/lab_pin.sym} 710 -2110 0 1 {name=l108 sig_type=std_logic lab=SAMPLE_3.3} +C {devices/lab_pin.sym} 990 -2310 0 0 {name=l109 sig_type=std_logic lab=SAMPLEb_3.3} +C {devices/lab_pin.sym} 990 -2290 0 0 {name=l110 sig_type=std_logic lab=SAMPLE_3.3} +C {devices/ipin.sym} 400 -2530 0 0 {name=p9 lab=row_sel} +C {devices/ipin.sym} 400 -2490 0 0 {name=p10 lab=col_sel} +C {devices/lab_pin.sym} 750 -2510 0 1 {name=l113 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 990 -2390 0 0 {name=l114 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 1340 -850 0 0 {name=l115 sig_type=std_logic lab=phi1} +C {devices/lab_pin.sym} 1340 -830 0 0 {name=l116 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 1790 -830 2 0 {name=l117 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1790 -850 2 0 {name=l118 sig_type=std_logic lab=vccd1} +C {devices/ipin.sym} 1345 -790 2 1 {name=p18 lab=Vref_comp} +C {devices/opin.sym} 2315 -790 2 1 {name=p58 lab=latch_high} +C {devices/lab_pin.sym} 1340 -810 2 1 {name=l123 sig_type=std_logic lab=Vsample} +C {devices/ipin.sym} 765 -830 2 1 {name=p20 lab=RISC_CLK} +C {comparator.sym} 1580 -820 0 0 {name=x9} +C {devices/noconn.sym} 1730 -790 0 1 {name=l127} +C {inv_2.sym} 850 -830 0 0 {name=x10 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {inv_2.sym} 1010 -830 0 0 {name=x11 VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {devices/code.sym} 310 -970 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt +.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/lab_pin.sym} 930 -830 1 1 {name=l128 sig_type=std_logic lab=phi1b} +C {devices/lab_pin.sym} 1120 -830 0 1 {name=l129 sig_type=std_logic lab=phi1} +C {and2_4.sym} 570 -2510 0 0 {name=x8[13:0] VGND=vssd1 VNB=vssd1 VPB=vccd1 VPWR=vccd1 prefix=sky130_fd_sc_hd__ } +C {comp_out_sel.sym} 2100 -810 0 0 {name=x7} +C {devices/lab_pin.sym} 2330 -830 0 1 {name=l112 sig_type=std_logic lab=vccd1} +C {devices/lab_pin.sym} 1950 -830 0 0 {name=l121 sig_type=std_logic lab=row_sel} +C {devices/lab_pin.sym} 2330 -810 2 0 {name=l111 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 2000 -1520 2 1 {name=l57 sig_type=std_logic lab=vssd1}
diff --git a/xschem/core.sym b/xschem/core.sym new file mode 100644 index 0000000..904186d --- /dev/null +++ b/xschem/core.sym
@@ -0,0 +1,308 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -770 130 -770 {} +L 4 -130 540 130 540 {} +L 4 -150 -760 -130 -760 {} +L 4 -150 -740 -130 -740 {} +L 4 -150 -720 -130 -720 {} +L 4 -150 -700 -130 -700 {} +L 4 -150 -680 -130 -680 {} +L 4 130 -460 150 -460 {} +L 4 -150 -460 -130 -460 {} +L 4 130 -440 150 -440 {} +L 4 -150 -440 -130 -440 {} +L 4 -150 -660 -130 -660 {} +L 4 130 -420 150 -420 {} +L 4 -150 -420 -130 -420 {} +L 4 130 -400 150 -400 {} +L 4 -150 -400 -130 -400 {} +L 4 130 -380 150 -380 {} +L 4 -150 -380 -130 -380 {} +L 4 130 -360 150 -360 {} +L 4 -150 -360 -130 -360 {} +L 4 -150 -640 -130 -640 {} +L 4 130 -340 150 -340 {} +L 4 -150 -340 -130 -340 {} +L 4 -150 -620 -130 -620 {} +L 4 130 -320 150 -320 {} +L 4 -150 -320 -130 -320 {} +L 4 130 -300 150 -300 {} +L 4 -150 -300 -130 -300 {} +L 4 130 -280 150 -280 {} +L 4 -150 -280 -130 -280 {} +L 4 130 -260 150 -260 {} +L 4 -150 -260 -130 -260 {} +L 4 130 -240 150 -240 {} +L 4 -150 -240 -130 -240 {} +L 4 130 -220 150 -220 {} +L 4 -150 -220 -130 -220 {} +L 4 130 -200 150 -200 {} +L 4 -150 -200 -130 -200 {} +L 4 130 -180 150 -180 {} +L 4 -150 -180 -130 -180 {} +L 4 130 -160 150 -160 {} +L 4 -150 -160 -130 -160 {} +L 4 -150 -120 -130 -120 {} +L 4 -150 -100 -130 -100 {} +L 4 -150 -80 -130 -80 {} +L 4 -150 -60 -130 -60 {} +L 4 -150 -40 -130 -40 {} +L 4 -150 -20 -130 -20 {} +L 4 -150 0 -130 0 {} +L 4 -150 20 -130 20 {} +L 4 -150 40 -130 40 {} +L 4 -150 60 -130 60 {} +L 4 -150 80 -130 80 {} +L 4 -150 100 -130 100 {} +L 4 -150 120 -130 120 {} +L 4 -150 140 -130 140 {} +L 4 -150 160 -130 160 {} +L 4 -150 180 -130 180 {} +L 4 -150 -600 -130 -600 {} +L 4 130 -760 150 -760 {} +L 4 -150 -580 -130 -580 {} +L 4 -150 -560 -130 -560 {} +L 4 -150 -540 -130 -540 {} +L 4 -150 -520 -130 -520 {} +L 4 130 440 150 440 {} +L 4 130 460 150 460 {} +L 4 130 480 150 480 {} +L 4 130 500 150 500 {} +L 4 130 520 150 520 {} +L 4 -150 220 -130 220 {} +L 4 -150 240 -130 240 {} +L 4 -150 260 -130 260 {} +L 4 -150 280 -130 280 {} +L 4 -150 300 -130 300 {} +L 4 -150 320 -130 320 {} +L 4 -150 340 -130 340 {} +L 4 -150 360 -130 360 {} +L 4 -150 380 -130 380 {} +L 4 -150 400 -130 400 {} +L 4 -150 420 -130 420 {} +L 4 -150 440 -130 440 {} +L 4 -150 460 -130 460 {} +L 4 -150 480 -130 480 {} +L 4 130 340 150 340 {} +L 4 130 220 150 220 {} +L 4 130 240 150 240 {} +L 4 130 260 150 260 {} +L 4 130 280 150 280 {} +L 4 130 300 150 300 {} +L 4 130 320 150 320 {} +L 4 130 360 150 360 {} +L 4 130 380 150 380 {} +L 4 130 400 150 400 {} +L 4 130 420 150 420 {} +L 4 -150 500 -130 500 {} +L 4 -150 520 -130 520 {} +L 4 -130 -770 -130 -650 {} +L 4 130 -770 130 -650 {} +L 4 -130 -650 -130 540 {} +L 4 130 -650 130 540 {} +L 7 130 -740 150 -740 {} +L 7 130 -720 150 -720 {} +L 7 130 -700 150 -700 {} +B 5 -152.5 -762.5 -147.5 -757.5 {name=row_sel dir=in } +B 5 -152.5 -742.5 -147.5 -737.5 {name=col_sel dir=in } +B 5 -152.5 -722.5 -147.5 -717.5 {name=Vgnr dir=in } +B 5 -152.5 -702.5 -147.5 -697.5 {name=WR dir=in } +B 5 -152.5 -682.5 -147.5 -677.5 {name=Vgpr dir=in } +B 5 147.5 -462.5 152.5 -457.5 {name=B15r sig_type=std_logic dir=in } +B 5 -152.5 -462.5 -147.5 -457.5 {name=A15r sig_type=std_logic dir=in } +B 5 147.5 -442.5 152.5 -437.5 {name=B14r sig_type=std_logic dir=in } +B 5 -152.5 -442.5 -147.5 -437.5 {name=A14r sig_type=std_logic dir=in } +B 5 -152.5 -662.5 -147.5 -657.5 {name=SAMPLE dir=in } +B 5 147.5 -422.5 152.5 -417.5 {name=B13r sig_type=std_logic dir=in } +B 5 -152.5 -422.5 -147.5 -417.5 {name=A13r sig_type=std_logic dir=in } +B 5 147.5 -402.5 152.5 -397.5 {name=B12r sig_type=std_logic dir=in } +B 5 -152.5 -402.5 -147.5 -397.5 {name=A12r sig_type=std_logic dir=in } +B 5 147.5 -382.5 152.5 -377.5 {name=B11r sig_type=std_logic dir=in } +B 5 -152.5 -382.5 -147.5 -377.5 {name=A11r sig_type=std_logic dir=in } +B 5 147.5 -362.5 152.5 -357.5 {name=B10r sig_type=std_logic dir=in } +B 5 -152.5 -362.5 -147.5 -357.5 {name=A10r sig_type=std_logic dir=in } +B 5 -152.5 -642.5 -147.5 -637.5 {name=Vrminus dir=in } +B 5 147.5 -342.5 152.5 -337.5 {name=B9r sig_type=std_logic dir=in } +B 5 -152.5 -342.5 -147.5 -337.5 {name=A9r sig_type=std_logic dir=in } +B 5 -152.5 -622.5 -147.5 -617.5 {name=Vrplus dir=in } +B 5 147.5 -322.5 152.5 -317.5 {name=B8r sig_type=std_logic dir=in } +B 5 -152.5 -322.5 -147.5 -317.5 {name=A8r sig_type=std_logic dir=in } +B 5 147.5 -302.5 152.5 -297.5 {name=B7r sig_type=std_logic dir=in } +B 5 -152.5 -302.5 -147.5 -297.5 {name=A7r sig_type=std_logic dir=in } +B 5 147.5 -282.5 152.5 -277.5 {name=B6r sig_type=std_logic dir=in } +B 5 -152.5 -282.5 -147.5 -277.5 {name=A6r sig_type=std_logic dir=in } +B 5 147.5 -262.5 152.5 -257.5 {name=B5r sig_type=std_logic dir=in } +B 5 -152.5 -262.5 -147.5 -257.5 {name=A5r sig_type=std_logic dir=in } +B 5 147.5 -242.5 152.5 -237.5 {name=B4r sig_type=std_logic dir=in } +B 5 -152.5 -242.5 -147.5 -237.5 {name=A4r sig_type=std_logic dir=in } +B 5 147.5 -222.5 152.5 -217.5 {name=B3r sig_type=std_logic dir=in } +B 5 -152.5 -222.5 -147.5 -217.5 {name=A3r sig_type=std_logic dir=in } +B 5 147.5 -202.5 152.5 -197.5 {name=B2r sig_type=std_logic dir=in } +B 5 -152.5 -202.5 -147.5 -197.5 {name=A2r sig_type=std_logic dir=in } +B 5 147.5 -182.5 152.5 -177.5 {name=B1r sig_type=std_logic dir=in } +B 5 -152.5 -182.5 -147.5 -177.5 {name=A1r sig_type=std_logic dir=in } +B 5 147.5 -162.5 152.5 -157.5 {name=B0r sig_type=std_logic dir=in } +B 5 -152.5 -162.5 -147.5 -157.5 {name=A0r sig_type=std_logic dir=in } +B 5 -152.5 -122.5 -147.5 -117.5 {name=WL15 sig_type=std_logic dir=in } +B 5 -152.5 -102.5 -147.5 -97.5 {name=WL14 sig_type=std_logic dir=in } +B 5 -152.5 -82.5 -147.5 -77.5 {name=WL13 sig_type=std_logic dir=in } +B 5 -152.5 -62.5 -147.5 -57.5 {name=WL12 sig_type=std_logic dir=in } +B 5 -152.5 -42.5 -147.5 -37.5 {name=WL11 sig_type=std_logic dir=in } +B 5 -152.5 -22.5 -147.5 -17.5 {name=WL10 sig_type=std_logic dir=in } +B 5 -152.5 -2.5 -147.5 2.5 {name=WL9 sig_type=std_logic dir=in } +B 5 -152.5 17.5 -147.5 22.5 {name=WL8 sig_type=std_logic dir=in } +B 5 -152.5 37.5 -147.5 42.5 {name=WL7 sig_type=std_logic dir=in } +B 5 -152.5 57.5 -147.5 62.5 {name=WL6 sig_type=std_logic dir=in } +B 5 -152.5 77.5 -147.5 82.5 {name=WL5 sig_type=std_logic dir=in } +B 5 -152.5 97.5 -147.5 102.5 {name=WL4 sig_type=std_logic dir=in } +B 5 -152.5 117.5 -147.5 122.5 {name=WL3 sig_type=std_logic dir=in } +B 5 -152.5 137.5 -147.5 142.5 {name=WL2 sig_type=std_logic dir=in } +B 5 -152.5 157.5 -147.5 162.5 {name=WL1 sig_type=std_logic dir=in } +B 5 -152.5 177.5 -147.5 182.5 {name=WL0 sig_type=std_logic dir=in } +B 5 -152.5 -602.5 -147.5 -597.5 {name=RISC_CLK dir=in } +B 5 147.5 -762.5 152.5 -757.5 {name=latch_high dir=out } +B 5 -152.5 -582.5 -147.5 -577.5 {name=Vref_comp dir=in } +B 5 -152.5 -562.5 -147.5 -557.5 {name=Vref dir=in } +B 5 147.5 -742.5 152.5 -737.5 {name=vccd1 dir=inout } +B 5 147.5 -722.5 152.5 -717.5 {name=vdda1 dir=inout } +B 5 147.5 -702.5 152.5 -697.5 {name=vssd1 dir=inout } +B 5 -152.5 -542.5 -147.5 -537.5 {name=Vcminus dir=in } +B 5 -152.5 -522.5 -147.5 -517.5 {name=Vcplus dir=in } +B 5 147.5 437.5 152.5 442.5 {name=B4c sig_type=std_logic dir=in } +B 5 147.5 457.5 152.5 462.5 {name=B3c sig_type=std_logic dir=in } +B 5 147.5 477.5 152.5 482.5 {name=B2c sig_type=std_logic dir=in } +B 5 147.5 497.5 152.5 502.5 {name=B1c sig_type=std_logic dir=in } +B 5 147.5 517.5 152.5 522.5 {name=B0c sig_type=std_logic dir=in } +B 5 -152.5 217.5 -147.5 222.5 {name=A15c sig_type=std_logic dir=in } +B 5 -152.5 237.5 -147.5 242.5 {name=A14c sig_type=std_logic dir=in } +B 5 -152.5 257.5 -147.5 262.5 {name=A13c sig_type=std_logic dir=in } +B 5 -152.5 277.5 -147.5 282.5 {name=A12c sig_type=std_logic dir=in } +B 5 -152.5 297.5 -147.5 302.5 {name=A11c sig_type=std_logic dir=in } +B 5 -152.5 317.5 -147.5 322.5 {name=A10c sig_type=std_logic dir=in } +B 5 -152.5 337.5 -147.5 342.5 {name=A9c sig_type=std_logic dir=in } +B 5 -152.5 357.5 -147.5 362.5 {name=A8c sig_type=std_logic dir=in } +B 5 -152.5 377.5 -147.5 382.5 {name=A7c sig_type=std_logic dir=in } +B 5 -152.5 397.5 -147.5 402.5 {name=A6c sig_type=std_logic dir=in } +B 5 -152.5 417.5 -147.5 422.5 {name=A5c sig_type=std_logic dir=in } +B 5 -152.5 437.5 -147.5 442.5 {name=A4c sig_type=std_logic dir=in } +B 5 -152.5 457.5 -147.5 462.5 {name=A3c sig_type=std_logic dir=in } +B 5 -152.5 477.5 -147.5 482.5 {name=A2c sig_type=std_logic dir=in } +B 5 147.5 337.5 152.5 342.5 {name=B9c sig_type=std_logic dir=in } +B 5 147.5 217.5 152.5 222.5 {name=B15c sig_type=std_logic dir=in } +B 5 147.5 237.5 152.5 242.5 {name=B14c sig_type=std_logic dir=in } +B 5 147.5 257.5 152.5 262.5 {name=B13c sig_type=std_logic dir=in } +B 5 147.5 277.5 152.5 282.5 {name=B12c sig_type=std_logic dir=in } +B 5 147.5 297.5 152.5 302.5 {name=B11c sig_type=std_logic dir=in } +B 5 147.5 317.5 152.5 322.5 {name=B10c sig_type=std_logic dir=in } +B 5 147.5 357.5 152.5 362.5 {name=B8c sig_type=std_logic dir=in } +B 5 147.5 377.5 152.5 382.5 {name=B7c sig_type=std_logic dir=in } +B 5 147.5 397.5 152.5 402.5 {name=B6c sig_type=std_logic dir=in } +B 5 147.5 417.5 152.5 422.5 {name=B5c sig_type=std_logic dir=in } +B 5 -152.5 497.5 -147.5 502.5 {name=A1c sig_type=std_logic dir=in } +B 5 -152.5 517.5 -147.5 522.5 {name=A0c sig_type=std_logic dir=in } +T {@symname} -36 -6 0 0 0.3 0.3 {} +T {@name} 85 -792 0 0 0.2 0.2 {} +T {row_sel} -125 -764 0 0 0.2 0.2 {} +T {col_sel} -125 -744 0 0 0.2 0.2 {} +T {Vgnr} -125 -724 0 0 0.2 0.2 {} +T {WR} -125 -704 0 0 0.2 0.2 {} +T {Vgpr} -125 -684 0 0 0.2 0.2 {} +T {B15r} 125 -464 0 1 0.2 0.2 {} +T {A15r} -125 -464 0 0 0.2 0.2 {} +T {B14r} 125 -444 0 1 0.2 0.2 {} +T {A14r} -125 -444 0 0 0.2 0.2 {} +T {SAMPLE} -125 -664 0 0 0.2 0.2 {} +T {B13r} 125 -424 0 1 0.2 0.2 {} +T {A13r} -125 -424 0 0 0.2 0.2 {} +T {B12r} 125 -404 0 1 0.2 0.2 {} +T {A12r} -125 -404 0 0 0.2 0.2 {} +T {B11r} 125 -384 0 1 0.2 0.2 {} +T {A11r} -125 -384 0 0 0.2 0.2 {} +T {B10r} 125 -364 0 1 0.2 0.2 {} +T {A10r} -125 -364 0 0 0.2 0.2 {} +T {Vrminus} -125 -644 0 0 0.2 0.2 {} +T {B9r} 125 -344 0 1 0.2 0.2 {} +T {A9r} -125 -344 0 0 0.2 0.2 {} +T {Vrplus} -125 -624 0 0 0.2 0.2 {} +T {B8r} 125 -324 0 1 0.2 0.2 {} +T {A8r} -125 -324 0 0 0.2 0.2 {} +T {B7r} 125 -304 0 1 0.2 0.2 {} +T {A7r} -125 -304 0 0 0.2 0.2 {} +T {B6r} 125 -284 0 1 0.2 0.2 {} +T {A6r} -125 -284 0 0 0.2 0.2 {} +T {B5r} 125 -264 0 1 0.2 0.2 {} +T {A5r} -125 -264 0 0 0.2 0.2 {} +T {B4r} 125 -244 0 1 0.2 0.2 {} +T {A4r} -125 -244 0 0 0.2 0.2 {} +T {B3r} 125 -224 0 1 0.2 0.2 {} +T {A3r} -125 -224 0 0 0.2 0.2 {} +T {B2r} 125 -204 0 1 0.2 0.2 {} +T {A2r} -125 -204 0 0 0.2 0.2 {} +T {B1r} 125 -184 0 1 0.2 0.2 {} +T {A1r} -125 -184 0 0 0.2 0.2 {} +T {B0r} 125 -164 0 1 0.2 0.2 {} +T {A0r} -125 -164 0 0 0.2 0.2 {} +T {WL15} -125 -124 0 0 0.2 0.2 {} +T {WL14} -125 -104 0 0 0.2 0.2 {} +T {WL13} -125 -84 0 0 0.2 0.2 {} +T {WL12} -125 -64 0 0 0.2 0.2 {} +T {WL11} -125 -44 0 0 0.2 0.2 {} +T {WL10} -125 -24 0 0 0.2 0.2 {} +T {WL9} -125 -4 0 0 0.2 0.2 {} +T {WL8} -125 16 0 0 0.2 0.2 {} +T {WL7} -125 36 0 0 0.2 0.2 {} +T {WL6} -125 56 0 0 0.2 0.2 {} +T {WL5} -125 76 0 0 0.2 0.2 {} +T {WL4} -125 96 0 0 0.2 0.2 {} +T {WL3} -125 116 0 0 0.2 0.2 {} +T {WL2} -125 136 0 0 0.2 0.2 {} +T {WL1} -125 156 0 0 0.2 0.2 {} +T {WL0} -125 176 0 0 0.2 0.2 {} +T {RISC_CLK} -125 -604 0 0 0.2 0.2 {} +T {latch_high} 125 -764 0 1 0.2 0.2 {} +T {Vref_comp} -125 -584 0 0 0.2 0.2 {} +T {Vref} -125 -564 0 0 0.2 0.2 {} +T {vccd1} 125 -744 0 1 0.2 0.2 {} +T {vdda1} 125 -724 0 1 0.2 0.2 {} +T {vssd1} 125 -704 0 1 0.2 0.2 {} +T {Vcminus} -125 -544 0 0 0.2 0.2 {} +T {Vcplus} -125 -524 0 0 0.2 0.2 {} +T {B4c} 125 436 0 1 0.2 0.2 {} +T {B3c} 125 456 0 1 0.2 0.2 {} +T {B2c} 125 476 0 1 0.2 0.2 {} +T {B1c} 125 496 0 1 0.2 0.2 {} +T {B0c} 125 516 0 1 0.2 0.2 {} +T {A15c} -125 216 0 0 0.2 0.2 {} +T {A14c} -125 236 0 0 0.2 0.2 {} +T {A13c} -125 256 0 0 0.2 0.2 {} +T {A12c} -125 276 0 0 0.2 0.2 {} +T {A11c} -125 296 0 0 0.2 0.2 {} +T {A10c} -125 316 0 0 0.2 0.2 {} +T {A9c} -125 336 0 0 0.2 0.2 {} +T {A8c} -125 356 0 0 0.2 0.2 {} +T {A7c} -125 376 0 0 0.2 0.2 {} +T {A6c} -125 396 0 0 0.2 0.2 {} +T {A5c} -125 416 0 0 0.2 0.2 {} +T {A4c} -125 436 0 0 0.2 0.2 {} +T {A3c} -125 456 0 0 0.2 0.2 {} +T {A2c} -125 476 0 0 0.2 0.2 {} +T {B9c} 125 336 0 1 0.2 0.2 {} +T {B15c} 125 216 0 1 0.2 0.2 {} +T {B14c} 125 236 0 1 0.2 0.2 {} +T {B13c} 125 256 0 1 0.2 0.2 {} +T {B12c} 125 276 0 1 0.2 0.2 {} +T {B11c} 125 296 0 1 0.2 0.2 {} +T {B10c} 125 316 0 1 0.2 0.2 {} +T {B8c} 125 356 0 1 0.2 0.2 {} +T {B7c} 125 376 0 1 0.2 0.2 {} +T {B6c} 125 396 0 1 0.2 0.2 {} +T {B5c} 125 416 0 1 0.2 0.2 {} +T {A1c} -125 496 0 0 0.2 0.2 {} +T {A0c} -125 516 0 0 0.2 0.2 {}
diff --git a/xschem/current_test.spice b/xschem/current_test.spice deleted file mode 100644 index 8e4162d..0000000 --- a/xschem/current_test.spice +++ /dev/null
@@ -1,86 +0,0 @@ -*--------------------------------------------------------------------------- -* SPDX-FileCopyrightText: 2020 Efabless Corporation -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* https://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* SPDX-License-Identifier: Apache-2.0 -*--------------------------------------------------------------------------- -* Simple POR circuit for Caravel current mirror test -*------------------------------------------------------------------- - -.param mc_mm_switch=0 -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - -* Note: 20 resistors of length 25um connected in series -Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 -Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149 - -* voltage sources at 0V for measuring current in each branch - -Vm1 vssm1 vss DC=0 -Vm2 vdda vddm2 DC=0 -Vm3 vdda vddm3 DC=0 -Vm4 vssm4 vss DC=0 -Vm5 vssm5 vss DC=0 -Vm6 vdda vddm6 DC=0 -Vm7 vdda vddm7 DC=0 - -* D G S B -Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 -Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 -Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 -Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 -Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 - -* Check branch currents in each mirror branch. -* 1st branch should be 240nA -* 2nd branch should be 30nA -* 3rd branch should be 4.3nA -* 4th branch should be 612pA -* -* Result: vin sits at 0.7590 (close to 0.7575 target) -* I(Vm1/2) = 202.80 nA -* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77 -* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70 -* I(Vm7) = 0.67 nA (should be /7) actually /6.80 - -*---------------------------- -* Testbench circuit -*---------------------------- -Vpwr vdda vss DC=3.3 -Rgnd vss 0 0.01 -Rload vcap vss 1MEG -*---------------------------- - -*---------------------------- -* Testbench control -*---------------------------- -.control -op -print V(vin) -print I(Vm1) -print I(Vm2) -print I(Vm3) -print I(Vm4) -print I(Vm5) -print I(Vm6) -print I(Vm7) -.endc - -.end -
diff --git a/xschem/decoder2to4_x6.sch b/xschem/decoder2to4_x6.sch new file mode 100755 index 0000000..9258bb2 --- /dev/null +++ b/xschem/decoder2to4_x6.sch
@@ -0,0 +1,116 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 580 -310 660 -310 { +lab=#net1} +N 660 -310 730 -310 { +lab=#net1} +N 580 -330 610 -330 { +lab=VSUBS} +N 580 -350 640 -350 { +lab=VP} +N 580 -90 660 -90 { +lab=#net2} +N 660 -90 730 -90 { +lab=#net2} +N 610 -330 620 -330 { +lab=VSUBS} +N 620 -330 620 -220 { +lab=VSUBS} +N 580 -220 620 -220 { +lab=VSUBS} +N 620 -220 620 -110 { +lab=VSUBS} +N 580 -110 620 -110 { +lab=VSUBS} +N 640 -350 640 -240 { +lab=VP} +N 580 -240 640 -240 { +lab=VP} +N 640 -240 640 -130 { +lab=VP} +N 580 -130 640 -130 { +lab=VP} +N 580 -200 910 -200 { +lab=A1b} +N 1030 -290 1090 -290 { +lab=A0} +N 1030 -70 1090 -70 { +lab=A2} +N 190 -330 190 -110 { +lab=Bb} +N 220 -350 280 -350 { +lab=Ab} +N 170 -350 220 -350 { +lab=Ab} +N 220 -330 280 -330 { +lab=Bb} +N 240 -350 240 -240 { +lab=Ab} +N 240 -240 280 -240 { +lab=Ab} +N 90 -220 280 -220 { +lab=B} +N 90 -130 280 -130 { +lab=A} +N 90 -110 280 -110 { +lab=Bb} +N 190 -330 190 -110 { +lab=Bb} +N 190 -330 220 -330 { +lab=Bb} +N 90 -350 170 -350 { +lab=Ab} +N 1030 -270 1100 -270 { +lab=VSUBS} +N 1030 -310 1100 -310 { +lab=VP} +N 1150 -310 1180 -310 { +lab=A0} +N 1150 -310 1150 -290 { +lab=A0} +N 1090 -290 1150 -290 { +lab=A0} +N 1480 -290 1540 -290 { +lab=A0b} +N 1480 -270 1550 -270 { +lab=VSUBS} +N 1480 -310 1550 -310 { +lab=VP} +N 1150 -220 1540 -220 { +lab=A0} +N 1150 -290 1150 -220 { +lab=A0} +N 1030 -70 1090 -70 { +lab=A2} +N 1030 -50 1100 -50 { +lab=VSUBS} +N 1030 -90 1100 -90 { +lab=VP} +C {devices/lab_pin.sym} 1100 -310 0 1 {name=l5 sig_type=std_logic lab=VP} +C {devices/opin.sym} 1540 -220 0 0 {name=p5 lab=A0} +C {devices/opin.sym} 910 -200 0 0 {name=p6 lab=A1b} +C {devices/opin.sym} 1090 -70 0 0 {name=p7 lab=A2} +C {devices/lab_pin.sym} 640 -350 2 0 {name=l9 sig_type=std_logic lab=VP} +C {devices/lab_pin.sym} 620 -110 0 1 {name=l10 sig_type=std_logic lab=VSUBS} +C {devices/iopin.sym} 100 -470 2 0 {name=p3 lab=VP} +C {devices/iopin.sym} 100 -450 2 0 {name=p4 lab=VSUBS} +C {devices/ipin.sym} 90 -350 0 0 {name=p1 lab=Ab} +C {devices/ipin.sym} 90 -220 0 0 {name=p2 lab=B} +C {devices/ipin.sym} 90 -130 0 0 {name=p8 lab=A} +C {devices/ipin.sym} 90 -110 0 0 {name=p9 lab=Bb} +C {inv_x6.sym} 880 -290 0 0 {name=x4} +C {inv_x6.sym} 880 -70 0 0 {name=x5} +C {inv_x6.sym} 1330 -290 0 0 {name=x6} +C {devices/lab_pin.sym} 1550 -310 0 1 {name=l1 sig_type=std_logic lab=VP} +C {devices/opin.sym} 1540 -290 0 0 {name=p10 lab=A0b} +C {devices/lab_pin.sym} 1100 -90 0 1 {name=l3 sig_type=std_logic lab=VP} +C {nand2_x6.sym} 430 -330 0 0 {name=x1} +C {nand2_x6.sym} 430 -220 0 0 {name=x2} +C {nand2_x6.sym} 430 -110 0 0 {name=x3} +C {devices/lab_pin.sym} 1100 -50 0 1 {name=l4 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1100 -270 0 1 {name=l6 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1550 -270 0 1 {name=l2 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/decoder2to4_x6.sym b/xschem/decoder2to4_x6.sym new file mode 100755 index 0000000..1647129 --- /dev/null +++ b/xschem/decoder2to4_x6.sym
@@ -0,0 +1,42 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -81 -6 0 0 0.3 0.3 {} +T {@name} 135 -72 0 0 0.2 0.2 {} +L 4 -130 -60 130 -60 {} +L 4 -130 60 130 60 {} +L 4 -130 -60 -130 60 {} +L 4 130 -60 130 60 {} +B 5 147.5 -52.5 152.5 -47.5 {name=VP dir=inout } +L 7 130 -50 150 -50 {} +T {VP} 125 -54 0 1 0.2 0.2 {} +B 5 147.5 -32.5 152.5 -27.5 {name=VSUBS dir=inout } +L 7 130 -30 150 -30 {} +T {VSUBS} 125 -34 0 1 0.2 0.2 {} +B 5 -152.5 -52.5 -147.5 -47.5 {name=Ab dir=in } +L 4 -150 -50 -130 -50 {} +T {Ab} -125 -54 0 0 0.2 0.2 {} +B 5 147.5 -12.5 152.5 -7.5 {name=A0b dir=out } +L 4 130 -10 150 -10 {} +T {A0b} 125 -14 0 1 0.2 0.2 {} +B 5 -152.5 -32.5 -147.5 -27.5 {name=B dir=in } +L 4 -150 -30 -130 -30 {} +T {B} -125 -34 0 0 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=A0 dir=out } +L 4 130 10 150 10 {} +T {A0} 125 6 0 1 0.2 0.2 {} +B 5 147.5 27.5 152.5 32.5 {name=A1b dir=out } +L 4 130 30 150 30 {} +T {A1b} 125 26 0 1 0.2 0.2 {} +B 5 -152.5 -12.5 -147.5 -7.5 {name=A dir=in } +L 4 -150 -10 -130 -10 {} +T {A} -125 -14 0 0 0.2 0.2 {} +B 5 -152.5 7.5 -147.5 12.5 {name=Bb dir=in } +L 4 -150 10 -130 10 {} +T {Bb} -125 6 0 0 0.2 0.2 {} +B 5 147.5 47.5 152.5 52.5 {name=A2 dir=out } +L 4 130 50 150 50 {} +T {A2} 125 46 0 1 0.2 0.2 {}
diff --git a/xschem/decoder_3to8_top.sch b/xschem/decoder_3to8_top.sch new file mode 100644 index 0000000..fda2cf3 --- /dev/null +++ b/xschem/decoder_3to8_top.sch
@@ -0,0 +1,165 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 810 -770 870 -770 { +lab=Y0} +N 810 -580 870 -580 { +lab=#net1} +N 120 -490 190 -490 { +lab=IN0} +N 270 -490 340 -490 { +lab=IN0b} +N 120 -420 190 -420 { +lab=IN1} +N 270 -420 340 -420 { +lab=IN1b} +N 120 -350 190 -350 { +lab=IN2} +N 270 -350 340 -350 { +lab=IN2b} +N 640 -830 690 -830 { +lab=IN2b} +N 640 -790 690 -790 { +lab=IN1b} +N 640 -750 690 -750 { +lab=IN0b} +N 640 -640 690 -640 { +lab=IN2b} +N 640 -600 690 -600 { +lab=IN1b} +N 640 -560 690 -560 { +lab=IN0} +N 810 -400 870 -400 { +lab=#net2} +N 810 -220 870 -220 { +lab=#net3} +N 640 -460 690 -460 { +lab=IN2b} +N 640 -420 690 -420 { +lab=IN1} +N 640 -380 690 -380 { +lab=IN0b} +N 640 -280 690 -280 { +lab=IN2b} +N 640 -240 690 -240 { +lab=IN1} +N 640 -200 690 -200 { +lab=IN0} +N 1380 -770 1440 -770 { +lab=#net4} +N 1380 -580 1440 -580 { +lab=#net5} +N 1210 -830 1260 -830 { +lab=IN2} +N 1210 -790 1260 -790 { +lab=IN1b} +N 1210 -750 1260 -750 { +lab=IN0b} +N 1210 -640 1260 -640 { +lab=IN2} +N 1210 -600 1260 -600 { +lab=IN1b} +N 1210 -560 1260 -560 { +lab=IN0} +N 1380 -400 1440 -400 { +lab=#net6} +N 1380 -220 1440 -220 { +lab=#net7} +N 1210 -460 1260 -460 { +lab=IN2} +N 1210 -420 1260 -420 { +lab=IN1} +N 1210 -380 1260 -380 { +lab=IN0b} +N 1210 -280 1260 -280 { +lab=IN2} +N 1210 -240 1260 -240 { +lab=IN1} +N 1210 -200 1260 -200 { +lab=IN0} +N 640 -710 690 -710 { +lab=EN} +N 640 -520 690 -520 { +lab=EN} +N 640 -340 690 -340 { +lab=EN} +N 640 -160 690 -160 { +lab=EN} +N 1210 -710 1260 -710 { +lab=EN} +N 1210 -520 1260 -520 { +lab=EN} +N 1210 -340 1260 -340 { +lab=EN} +N 1210 -160 1260 -160 { +lab=EN} +C {devices/ipin.sym} 120 -640 2 1 {name=p3 lab=VP} +C {devices/ipin.sym} 120 -620 2 1 {name=p4 lab=VN} +C {devices/ipin.sym} 120 -420 0 0 {name=p2 lab=IN1} +C {devices/ipin.sym} 120 -490 0 0 {name=p8 lab=IN0} +C {devices/code.sym} 220 -730 0 0 {name=TT_MODELS +only_toplevel=true +format="tcleval( @value )" +value=".lib $::SKYWATER_MODELS/sky130.lib.spice tt +.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice +" +spice_ignore=false} +C {devices/ipin.sym} 120 -350 0 0 {name=p1 lab=IN2} +C {inv_16.sym} 230 -490 0 0 {name=x1 VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {inv_16.sym} 230 -420 0 0 {name=x2 VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {inv_16.sym} 230 -350 0 0 {name=x3 VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 640 -750 0 0 {name=l4 sig_type=std_logic lab=IN0b} +C {devices/lab_pin.sym} 640 -790 0 0 {name=l5 sig_type=std_logic lab=IN1b} +C {devices/lab_pin.sym} 640 -830 0 0 {name=l6 sig_type=std_logic lab=IN2b} +C {devices/lab_pin.sym} 640 -560 0 0 {name=l7 sig_type=std_logic lab=IN0} +C {devices/lab_pin.sym} 640 -600 0 0 {name=l8 sig_type=std_logic lab=IN1b} +C {devices/lab_pin.sym} 640 -640 0 0 {name=l9 sig_type=std_logic lab=IN2b} +C {devices/lab_pin.sym} 640 -380 0 0 {name=l10 sig_type=std_logic lab=IN0b} +C {devices/lab_pin.sym} 640 -420 0 0 {name=l11 sig_type=std_logic lab=IN1} +C {devices/lab_pin.sym} 640 -460 0 0 {name=l12 sig_type=std_logic lab=IN2b} +C {devices/lab_pin.sym} 640 -200 0 0 {name=l13 sig_type=std_logic lab=IN0} +C {devices/lab_pin.sym} 640 -240 0 0 {name=l14 sig_type=std_logic lab=IN1} +C {devices/lab_pin.sym} 640 -280 0 0 {name=l15 sig_type=std_logic lab=IN2b} +C {devices/lab_pin.sym} 1210 -750 0 0 {name=l16 sig_type=std_logic lab=IN0b} +C {devices/lab_pin.sym} 1210 -790 0 0 {name=l17 sig_type=std_logic lab=IN1b} +C {devices/lab_pin.sym} 1210 -830 0 0 {name=l18 sig_type=std_logic lab=IN2} +C {devices/lab_pin.sym} 1210 -560 0 0 {name=l19 sig_type=std_logic lab=IN0} +C {devices/lab_pin.sym} 1210 -600 0 0 {name=l20 sig_type=std_logic lab=IN1b} +C {devices/lab_pin.sym} 1210 -640 0 0 {name=l21 sig_type=std_logic lab=IN2} +C {devices/lab_pin.sym} 1210 -380 0 0 {name=l22 sig_type=std_logic lab=IN0b} +C {devices/lab_pin.sym} 1210 -420 0 0 {name=l23 sig_type=std_logic lab=IN1} +C {devices/lab_pin.sym} 1210 -460 0 0 {name=l24 sig_type=std_logic lab=IN2} +C {devices/lab_pin.sym} 1210 -200 0 0 {name=l25 sig_type=std_logic lab=IN0} +C {devices/lab_pin.sym} 1210 -240 0 0 {name=l26 sig_type=std_logic lab=IN1} +C {devices/lab_pin.sym} 1210 -280 0 0 {name=l27 sig_type=std_logic lab=IN2} +C {and4_4.sym} 750 -770 0 0 {name=x8[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 640 -710 0 0 {name=l28 sig_type=std_logic lab=EN} +C {and4_4.sym} 750 -580 0 0 {name=x1[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 640 -520 0 0 {name=l29 sig_type=std_logic lab=EN} +C {and4_4.sym} 750 -400 0 0 {name=x2[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 640 -340 0 0 {name=l30 sig_type=std_logic lab=EN} +C {and4_4.sym} 750 -220 0 0 {name=x3[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 640 -160 0 0 {name=l31 sig_type=std_logic lab=EN} +C {and4_4.sym} 1320 -770 0 0 {name=x4[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 1210 -710 0 0 {name=l32 sig_type=std_logic lab=EN} +C {and4_4.sym} 1320 -580 0 0 {name=x5[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 1210 -520 0 0 {name=l33 sig_type=std_logic lab=EN} +C {and4_4.sym} 1320 -400 0 0 {name=x6[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 1210 -340 0 0 {name=l34 sig_type=std_logic lab=EN} +C {and4_4.sym} 1320 -220 0 0 {name=x7[9:0] VGND=VN VNB=VN VPB=VP VPWR=VP prefix=sky130_fd_sc_hd__ } +C {devices/lab_pin.sym} 1210 -160 0 0 {name=l35 sig_type=std_logic lab=EN} +C {devices/ipin.sym} 120 -280 0 0 {name=p14 lab=EN} +C {devices/lab_pin.sym} 340 -490 0 1 {name=l1 sig_type=std_logic lab=IN0b} +C {devices/lab_pin.sym} 340 -420 0 1 {name=l2 sig_type=std_logic lab=IN1b} +C {devices/lab_pin.sym} 340 -350 0 1 {name=l3 sig_type=std_logic lab=IN2b} +C {devices/opin.sym} 870 -770 0 0 {name=p5 lab=Y0} +C {devices/opin.sym} 870 -580 0 0 {name=p6 lab=Y1} +C {devices/opin.sym} 870 -400 0 0 {name=p7 lab=Y2} +C {devices/opin.sym} 870 -220 0 0 {name=p9 lab=Y3} +C {devices/opin.sym} 1440 -770 0 0 {name=p10 lab=Y4} +C {devices/opin.sym} 1440 -580 0 0 {name=p11 lab=Y5} +C {devices/opin.sym} 1440 -400 0 0 {name=p12 lab=Y6} +C {devices/opin.sym} 1440 -220 0 0 {name=p13 lab=Y7}
diff --git a/xschem/decoder_3to8_top.sym b/xschem/decoder_3to8_top.sym new file mode 100644 index 0000000..1b65a9b --- /dev/null +++ b/xschem/decoder_3to8_top.sym
@@ -0,0 +1,57 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +V {} +S {} +E {} +L 4 -130 -80 130 -80 {} +L 4 -130 80 130 80 {} +L 4 -130 -80 -130 80 {} +L 4 130 -80 130 80 {} +L 4 130 -70 150 -70 {} +L 4 130 10 150 10 {} +L 4 -150 -70 -130 -70 {} +L 4 -150 -50 -130 -50 {} +L 4 130 30 150 30 {} +L 4 130 -50 150 -50 {} +L 4 -150 -30 -130 -30 {} +L 4 -150 -10 -130 -10 {} +L 4 130 50 150 50 {} +L 4 130 -30 150 -30 {} +L 4 -150 10 -130 10 {} +L 4 -150 30 -130 30 {} +L 4 130 70 150 70 {} +L 4 130 -10 150 -10 {} +B 5 147.5 -72.5 152.5 -67.5 {name=Y0 dir=out } +B 5 147.5 7.5 152.5 12.5 {name=Y4 dir=out } +B 5 -152.5 -72.5 -147.5 -67.5 {name=VP dir=in } +B 5 -152.5 -52.5 -147.5 -47.5 {name=VN dir=in } +B 5 147.5 27.5 152.5 32.5 {name=Y5 dir=out } +B 5 147.5 -52.5 152.5 -47.5 {name=Y1 dir=out } +B 5 -152.5 -32.5 -147.5 -27.5 {name=IN0 dir=in } +B 5 -152.5 -12.5 -147.5 -7.5 {name=IN1 dir=in } +B 5 147.5 47.5 152.5 52.5 {name=Y6 dir=out } +B 5 147.5 -32.5 152.5 -27.5 {name=Y2 dir=out } +B 5 -152.5 7.5 -147.5 12.5 {name=IN2 dir=in } +B 5 -152.5 27.5 -147.5 32.5 {name=EN dir=in } +B 5 147.5 67.5 152.5 72.5 {name=Y7 dir=out } +B 5 147.5 -12.5 152.5 -7.5 {name=Y3 dir=out } +T {@symname} -90 -6 0 0 0.3 0.3 {} +T {@name} 135 -92 0 0 0.2 0.2 {} +T {Y0} 125 -74 0 1 0.2 0.2 {} +T {Y4} 125 6 0 1 0.2 0.2 {} +T {VP} -125 -74 0 0 0.2 0.2 {} +T {VN} -125 -54 0 0 0.2 0.2 {} +T {Y5} 125 26 0 1 0.2 0.2 {} +T {Y1} 125 -54 0 1 0.2 0.2 {} +T {IN0} -125 -34 0 0 0.2 0.2 {} +T {IN1} -125 -14 0 0 0.2 0.2 {} +T {Y6} 125 46 0 1 0.2 0.2 {} +T {Y2} 125 -34 0 1 0.2 0.2 {} +T {IN2} -125 6 0 0 0.2 0.2 {} +T {EN} -125 26 0 0 0.2 0.2 {} +T {Y7} 125 66 0 1 0.2 0.2 {} +T {Y3} 125 -14 0 1 0.2 0.2 {}
diff --git a/xschem/dfxtp_1.sym b/xschem/dfxtp_1.sym new file mode 100644 index 0000000..a41e44f --- /dev/null +++ b/xschem/dfxtp_1.sym
@@ -0,0 +1,40 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +function2="1 0 & 0 ~ 2 & |" +format="@name @@CLK @@D @VGND @VNB @VPB @VPWR @@Q @prefix\\\\dfxtp_1" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +} +V {} +S {} +E {} +L 4 -70 -20 70 -20 {} +L 4 -70 20 70 20 {} +L 4 -70 -20 -70 20 {} +L 4 70 -20 70 20 {} +L 4 -90 -10 -70 -10 {} +L 4 -90 10 -70 10 {} +L 4 70 -10 90 -10 {} +B 5 -92.5 -12.5 -87.5 -7.5 {name=CLK dir=in goto=2 clock=1} +B 5 -92.5 7.5 -87.5 12.5 {name=D dir=in } +B 5 87.5 -12.5 92.5 -7.5 {name=Q dir=out } +T {@symname} 0 -6 0 0 0.3 0.3 {hcenter=true} +T {@name} 75 -32 0 0 0.2 0.2 {} +T {CLK} -65 -14 0 0 0.2 0.2 {} +T {D} -65 6 0 0 0.2 0.2 {} +T {Q} 65 -14 0 1 0.2 0.2 {}
diff --git a/xschem/example_por.sch b/xschem/example_por.sch deleted file mode 100644 index cf6e0c3..0000000 --- a/xschem/example_por.sch +++ /dev/null
@@ -1,297 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -L 4 3370 -60 3390 -60 {} -L 4 3390 -60 3390 80 {} -L 4 3370 80 3390 80 {} -T {Current step-down mirror} 2270 140 0 0 0.4 0.4 {} -T {Charge accumulator} 2650 140 0 0 0.4 0.4 {} -T {Voltage divider} 1860 140 0 0 0.4 0.4 {} -T {Schmitt trigger} 2930 -200 0 0 0.4 0.4 {} -T {150 / 650 * 3.3V = 0.76V} 1860 180 0 0 0.4 0.4 {} -T {step down 8x} 2130 -430 0 0 0.4 0.4 {} -T {step down 7x} 2330 80 0 0 0.4 0.4 {} -T {step down 7x} 2520 -430 0 0 0.4 0.4 {} -T {1.8V domain outputs} 3400 0 0 0 0.4 0.4 {} -T {3.3V domain output} 3410 -140 0 0 0.4 0.4 {} -T {392 : 1} 2270 180 0 0 0.4 0.4 {} -T {Simple power-on-reset circuit -calibrated to 500us nominal delay -no temperature compensation} 1950 -570 0 0 0.6 0.6 {} -N 2500 -310 2500 -270 { lab=#net1} -N 2500 -210 2500 -100 { lab=#net2} -N 2300 -40 2300 20 { lab=#net3} -N 2300 80 2300 110 { lab=vss} -N 2360 110 2500 110 { lab=vss} -N 2500 80 2500 110 { lab=vss} -N 2400 50 2460 50 { lab=#net3} -N 2360 -400 2500 -400 { lab=vdd3v3} -N 2500 -400 2500 -370 { lab=vdd3v3} -N 2500 -400 2790 -400 { lab=vdd3v3} -N 2300 -10 2370 -10 { lab=#net3} -N 2370 -10 2370 50 { lab=#net3} -N 2500 -290 2570 -290 { lab=#net1} -N 2570 -340 2570 -290 { lab=#net1} -N 2540 -340 2570 -340 { lab=#net1} -N 2500 -190 2570 -190 { lab=#net2} -N 2570 -240 2570 -190 { lab=#net2} -N 2540 -240 2570 -240 { lab=#net2} -N 2240 110 2360 110 { lab=vss} -N 2500 110 2630 110 { lab=vss} -N 2500 50 2630 50 { lab=vss} -N 2110 110 2240 110 { lab=vss} -N 1930 60 1930 110 { lab=vss} -N 1930 -160 1930 0 { lab=#net4} -N 1930 -400 1930 -220 { lab=vdd3v3} -N 2110 -400 2360 -400 { lab=vdd3v3} -N 1880 -190 1910 -190 { lab=vss} -N 1880 -190 1880 110 { lab=vss} -N 1880 110 1930 110 { lab=vss} -N 1880 30 1910 30 { lab=vss} -N 2300 -310 2300 -270 { lab=#net5} -N 2300 -400 2300 -370 { lab=vdd3v3} -N 2300 -140 2300 -100 { lab=#net3} -N 2340 50 2400 50 { lab=#net3} -N 2300 -210 2300 -140 { lab=#net3} -N 2100 80 2100 110 { lab=vss} -N 2100 110 2110 110 { lab=vss} -N 2050 50 2060 50 { lab=#net4} -N 2050 -70 2050 50 { lab=#net4} -N 1930 -70 2050 -70 { lab=#net4} -N 1930 -400 2110 -400 { lab=vdd3v3} -N 2100 -400 2100 -370 { lab=vdd3v3} -N 2100 -310 2100 -270 { lab=#net6} -N 2100 -210 2100 20 { lab=#net7} -N 2100 50 2300 50 { lab=vss} -N 2200 50 2200 110 { lab=vss} -N 2140 -240 2260 -240 { lab=#net7} -N 2140 -340 2260 -340 { lab=#net6} -N 2100 -290 2180 -290 { lab=#net6} -N 2180 -340 2180 -290 { lab=#net6} -N 2100 -180 2180 -180 { lab=#net7} -N 2180 -240 2180 -180 { lab=#net7} -N 1930 -240 2100 -240 { lab=vdd3v3} -N 1930 -340 2100 -340 { lab=vdd3v3} -N 1930 110 2100 110 { lab=vss} -N 2300 -240 2500 -240 { lab=vdd3v3} -N 2300 -340 2500 -340 { lab=vdd3v3} -N 2400 -340 2400 -240 { lab=vdd3v3} -N 2400 -400 2400 -340 { lab=vdd3v3} -N 2570 -240 2650 -240 { lab=#net2} -N 2570 -340 2650 -340 { lab=#net1} -N 2690 -400 2690 -370 { lab=vdd3v3} -N 2790 -400 2790 -340 { lab=vdd3v3} -N 2690 -340 2790 -340 { lab=vdd3v3} -N 2690 -240 2790 -240 { lab=vdd3v3} -N 2790 -340 2790 -240 { lab=vdd3v3} -N 2690 -310 2690 -270 { lab=#net8} -N 2690 -210 2690 -150 { lab=#net9} -N 1830 30 1880 30 { lab=vss} -N 1810 60 1810 110 { lab=vss} -N 1810 110 1880 110 { lab=vss} -N 1810 -70 1810 0 { lab=vss} -N 1810 -70 1880 -70 { lab=vss} -N 2690 -150 2690 -70 { lab=#net9} -N 2820 -130 2820 -70 { lab=#net9} -N 2690 -130 2820 -130 { lab=#net9} -N 2630 110 2820 110 { lab=vss} -N 2820 -10 2820 110 { lab=vss} -N 2690 -10 2690 110 { lab=vss} -N 2820 -130 2980 -130 { lab=#net9} -N 3060 -130 3130 -130 { lab=#net10} -N 3090 -130 3090 60 { lab=#net10} -N 3090 60 3130 60 { lab=#net10} -N 3090 -40 3130 -40 { lab=#net10} -N 3210 -130 3300 -130 { lab=porb_h} -N 3210 -40 3300 -40 { lab=porb_l} -N 3210 60 3300 60 { lab=por_l} -N 2790 -400 2840 -400 { lab=vdd3v3} -N 2820 110 2870 110 { lab=vss} -N 2630 50 2690 50 { lab=vss} -N 2300 -100 2300 -40 { lab=#net3} -N 2500 -100 2500 -30 { lab=#net2} -N 2500 -30 2500 20 { lab=#net2} -C {sky130_fd_pr/cap_mim_m3_1.sym} 2690 -40 0 0 {name=C1 model=cap_mim_m3_1 W=30 L=30 MF=1 spiceprefix=X} -C {sky130_fd_pr/cap_mim_m3_2.sym} 2820 -40 2 1 {name=C2 model=cap_mim_m3_2 W=30 L=30 MF=1 spiceprefix=X} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -240 0 0 {name=M1 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2480 50 0 0 {name=M2 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 -190 0 0 {name=R1 -L=500 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=1} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2280 -340 0 0 {name=M4 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2320 50 0 1 {name=M5 -L=0.8 -W=14 -nf=7 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1930 30 0 0 {name=R2 -L=150 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=1} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -240 0 1 {name=M7 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2520 -340 0 1 {name=M8 -L=0.8 -W=14 -nf=7 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/nfet_g5v0d10v5.sym} 2080 50 0 0 {name=M10 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=nfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -240 0 1 {name=M9 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2120 -340 0 1 {name=M11 -L=0.8 -W=16 -nf=8 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -340 0 0 {name=M12 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/pfet_g5v0d10v5.sym} 2670 -240 0 0 {name=M13 -L=0.8 -W=2 -nf=1 -mult=1 -ad="'int((nf+1)/2) * W/nf * 0.29'" -pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" -as="'int((nf+2)/2) * W/nf * 0.29'" -ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" -nrd="'0.29 / W'" nrs="'0.29 / W'" -sa=0 sb=0 sd=0 -model=pfet_g5v0d10v5 -spiceprefix=X -} -C {sky130_fd_pr/res_xhigh_po_0p69.sym} 1810 30 0 1 {name=R3 -L=25 -model=res_xhigh_po_0p69 -spiceprefix=X -mult=2} -C {sky130_stdcells/buf_8.sym} 3170 -130 0 0 {name=x2 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/buf_8.sym} 3170 -40 0 0 {name=x3 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/inv_8.sym} 3170 60 0 0 {name=x4 VGND=vss VNB=vss VPB=vdd1v8 VPWR=vdd1v8 prefix=sky130_fd_sc_hvl__ } -C {sky130_stdcells/buf_1.sym} 3020 -130 0 0 {name=x5 VGND=vss VNB=vss VPB=vdd3v3 VPWR=vdd3v3 prefix=sky130_fd_sc_hvl__schmitt } -C {devices/iopin.sym} 2840 -400 0 0 {name=p1 lab=vdd3v3} -C {devices/iopin.sym} 2870 110 0 0 {name=p2 lab=vss} -C {devices/opin.sym} 3300 -130 0 0 {name=p3 lab=porb_h} -C {devices/opin.sym} 3300 -40 0 0 {name=p4 lab=porb_l} -C {devices/opin.sym} 3300 60 0 0 {name=p5 lab=por_l} -C {devices/iopin.sym} 2840 -330 0 0 {name=p6 lab=vdd1v8}
diff --git a/xschem/example_por.sym b/xschem/example_por.sym deleted file mode 100644 index e3875f5..0000000 --- a/xschem/example_por.sym +++ /dev/null
@@ -1,33 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {type=subcircuit -format="@name @pinlist @symname" -template="name=x1" -} -V {} -S {} -E {} -L 4 -130 -60 130 -60 {} -L 4 -130 60 130 60 {} -L 4 -130 -60 -130 60 {} -L 4 130 -60 130 60 {} -L 4 130 -30 150 -30 {} -L 4 130 0 150 0 {} -L 4 130 30 150 30 {} -L 7 -30 -80 -30 -60 {} -L 7 30 -80 30 -60 {} -L 7 0 60 0 80 {} -B 5 -32.5 -82.5 -27.5 -77.5 {name=vdd3v3 dir=inout } -B 5 27.5 -82.5 32.5 -77.5 {name=vdd1v8 dir=inout } -B 5 147.5 -32.5 152.5 -27.5 {name=porb_h dir=out } -B 5 147.5 -2.5 152.5 2.5 {name=porb_l dir=out } -B 5 147.5 27.5 152.5 32.5 {name=por_l dir=out } -B 5 -2.5 77.5 2.5 82.5 {name=vss dir=inout } -T {@symname} -47.5 -6 0 0 0.3 0.3 {} -T {@name} -25 18 0 0 0.2 0.2 {} -T {vdd3v3} -15 -54 0 1 0.2 0.2 {} -T {vdd1v8} 55 -54 0 1 0.2 0.2 {} -T {porb_h} 125 -34 0 1 0.2 0.2 {} -T {porb_l} 125 -4 0 1 0.2 0.2 {} -T {por_l} 125 26 0 1 0.2 0.2 {} -T {vss} 5 46 0 1 0.2 0.2 {}
diff --git a/xschem/example_por_tb.sch b/xschem/example_por_tb.sch deleted file mode 100644 index a24d814..0000000 --- a/xschem/example_por_tb.sch +++ /dev/null
@@ -1,45 +0,0 @@ -v {xschem version=2.9.9 file_version=1.2 } -G {} -K {} -V {} -S {} -E {} -T {Testbench for simple POR} -350 -240 0 0 0.6 0.6 {} -N -280 60 -10 60 { lab=GND} -N -540 0 -540 60 { lab=GND} -N -330 0 -330 60 { lab=GND} -N -330 -100 -330 -60 { lab=vdd3v3} -N -330 -110 -330 -100 { lab=vdd3v3} -N -210 -110 -40 -110 { lab=vdd3v3} -N -40 -110 -40 -100 { lab=vdd3v3} -N -540 -130 -540 -60 { lab=vdd1v8} -N -280 -130 20 -130 { lab=vdd1v8} -N 20 -130 20 -100 { lab=vdd1v8} -N 140 -50 180 -50 { lab=porb_h} -N 140 -20 180 -20 { lab=porb_l} -N 140 10 180 10 { lab=por_l} -N -340 -110 -330 -110 { lab=vdd3v3} -N -500 -130 -490 -130 { lab=vdd1v8} -N -540 -130 -500 -130 { lab=vdd1v8} -N -560 -130 -540 -130 { lab=vdd1v8} -N -540 60 -490 60 { lab=GND} -N -490 -130 -280 -130 { lab=vdd1v8} -N -490 60 -330 60 { lab=GND} -N -330 60 -280 60 { lab=GND} -N -330 -110 -210 -110 { lab=vdd3v3} -C {example_por.sym} -10 -20 0 0 {name=x1} -C {devices/gnd.sym} -100 60 0 0 {name=l1 lab=GND} -C {devices/vsource.sym} -330 -30 0 0 {name=V1 value="PWL(0.0 0 100u 0 5m 3.3)"} -C {devices/vsource.sym} -540 -30 0 0 {name=V2 value="PWL(0.0 0 300u 0 5.3m 1.8)"} -C {devices/opin.sym} -340 -110 0 1 {name=p1 lab=vdd3v3} -C {devices/opin.sym} -560 -130 0 1 {name=p2 lab=vdd1v8} -C {devices/opin.sym} 180 -50 0 0 {name=p3 lab=porb_h} -C {devices/opin.sym} 180 -20 0 0 {name=p4 lab=porb_l} -C {devices/opin.sym} 180 10 0 0 {name=p5 lab=por_l} -C {devices/code.sym} -470 140 0 0 {name=TT_MODELS only_toplevel=false -format="tcleval(@value )" value=".lib \\\\$::SKYWATER_MODELS\\\\/sky130.lib.spice tt -.include \\\\$::PDKPATH\\\\/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"} -C {devices/code_shown.sym} -320 160 0 0 {name=s2 only_toplevel=false value=".control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc"}
diff --git a/xschem/example_por_tb.spice b/xschem/example_por_tb.spice deleted file mode 100644 index fa82f74..0000000 --- a/xschem/example_por_tb.spice +++ /dev/null
@@ -1,78 +0,0 @@ -**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l -*.opin vdd3v3 -*.opin vdd1v8 -*.opin porb_h -*.opin porb_l -*.opin por_l -x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por -V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3) -V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8) -**** begin user architecture code -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc - -**** end user architecture code -**.ends - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end
diff --git a/xschem/example_por_tb.spice.orig b/xschem/example_por_tb.spice.orig deleted file mode 100644 index 069c74d..0000000 --- a/xschem/example_por_tb.spice.orig +++ /dev/null
@@ -1,88 +0,0 @@ -**.subckt example_por_tb vdd3v3 vdd1v8 porb_h porb_l por_l -.param mc_switch=0 -*.opin vdd3v3 -*.opin vdd1v8 -*.opin porb_h -*.opin porb_l -*.opin por_l -x1 vdd3v3 vdd1v8 porb_h porb_l por_l GND example_por -V1 vdd3v3 GND PWL(0.0 0 100u 0 5m 3.3) -V2 vdd1v8 GND PWL(0.0 0 300u 0 5.3m 1.8) -**** begin user architecture code - -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - - -.include /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice - -.control -tran 1u 20m -plot V(vdd3v3) V(vdd1v8) V(porb_h) V(porb_l) V(por_l) -.endc - -**** end user architecture code -**.ends - -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net11 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 net11 vss sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net5 net9 net7 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net1 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net6 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=500 mult=1 m=1 -XM3 net3 net5 net1 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM4 net7 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net4 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM6 net5 net5 net4 vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net6 vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=150 mult=1 m=1 -XM7 net3 net3 net2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net2 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net9 net6 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net9 net9 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net8 net8 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net10 net2 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net11 net3 net10 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 W=0.69 L=25 mult=2 m=2 -x2 net12 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net12 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net12 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net11 vss vss vdd3v3 vdd3v3 net12 sky130_fd_sc_hvl__schmittbuf_1 -.ends - -.GLOBAL GND -** flattened .save nodes -.end
diff --git a/xschem/inv_16.sym b/xschem/inv_16.sym new file mode 100644 index 0000000..4dd255a --- /dev/null +++ b/xschem/inv_16.sym
@@ -0,0 +1,36 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +format="@name @@A @VGND @VNB @VPB @VPWR @@Y @prefix\\\\inv_16" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -20 -20 -20 20 {} +L 4 -20 -20 20 0 {} +L 4 -20 20 20 0 {} +L 4 30 0 40 0 {} +L 4 -40 0 -20 0 {} +B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in goto=1 propag=1 } +B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } +A 4 25 0 5 180 360 {} +T {A} -35 -14 0 0 0.2 0.2 {} +T {Y} 35 -14 0 1 0.2 0.2 {} +T {@name} 2.5 15 0 0 0.2 0.2 {} +T {@symname} -7.5 -25 0 0 0.2 0.2 {}
diff --git a/xschem/inv_2.sym b/xschem/inv_2.sym new file mode 100644 index 0000000..d52902d --- /dev/null +++ b/xschem/inv_2.sym
@@ -0,0 +1,37 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +function1="0 ~" +format="@name @@A @VGND @VNB @VPB @VPWR @@Y @prefix\\\\inv_2" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -20 -20 -20 20 {} +L 4 -20 -20 20 0 {} +L 4 -20 20 20 0 {} +L 4 30 0 40 0 {} +L 4 -40 0 -20 0 {} +B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in goto=1 propag=1 } +B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } +A 4 25 0 5 180 360 {} +T {A} -35 -14 0 0 0.2 0.2 {} +T {Y} 35 -14 0 1 0.2 0.2 {} +T {@name} 2.5 15 0 0 0.2 0.2 {} +T {@symname} -7.5 -25 0 0 0.2 0.2 {}
diff --git a/xschem/inv_8.sym b/xschem/inv_8.sym new file mode 100644 index 0000000..1362efd --- /dev/null +++ b/xschem/inv_8.sym
@@ -0,0 +1,36 @@ +v {xschem version=3.1.0 file_version=1.2 +* Copyright 2022 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +} +G {} +K {type=primitive +format="@name @@A @VGND @VNB @VPB @VPWR @@Y @prefix\\\\inv_8" +template="name=x1 VGND=VGND VNB=VNB VPB=VPB VPWR=VPWR prefix=sky130_fd_sc_hd__ " +extra="VGND VNB VPB VPWR prefix" +highlight=true} +V {} +S {} +E {} +L 4 -20 -20 -20 20 {} +L 4 -20 -20 20 0 {} +L 4 -20 20 20 0 {} +L 4 30 0 40 0 {} +L 4 -40 0 -20 0 {} +B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in goto=1 propag=1 } +B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out } +A 4 25 0 5 180 360 {} +T {A} -35 -14 0 0 0.2 0.2 {} +T {Y} 35 -14 0 1 0.2 0.2 {} +T {@name} 2.5 15 0 0 0.2 0.2 {} +T {@symname} -7.5 -25 0 0 0.2 0.2 {}
diff --git a/xschem/inv_x6.sch b/xschem/inv_x6.sch new file mode 100755 index 0000000..2ede495 --- /dev/null +++ b/xschem/inv_x6.sch
@@ -0,0 +1,62 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 1180 -1320 1180 -1280 { +lab=Y} +N 1180 -1380 1180 -1350 { +lab=VP} +N 1180 -1250 1180 -1220 { +lab=VSUBS} +N 1120 -1250 1140 -1250 { +lab=A} +N 1120 -1350 1120 -1250 { +lab=A} +N 1120 -1350 1140 -1350 { +lab=A} +N 1090 -1300 1120 -1300 { +lab=A} +N 1180 -1300 1310 -1300 { +lab=Y} +N 1000 -1300 1090 -1300 { +lab=A} +N 1180 -1220 1180 -1180 { +lab=VSUBS} +N 1180 -1440 1180 -1380 { +lab=VP} +N 1180 -1180 1180 -1160 { +lab=VSUBS} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1160 -1250 0 0 {name=M1 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 1160 -1350 0 0 {name=M2 +L=0.5 +W=1 +nf=1 +mult=6 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 1180 -1440 3 0 {name=p1 lab=VP} +C {devices/iopin.sym} 1180 -1160 1 0 {name=p2 lab=VSUBS} +C {devices/ipin.sym} 1000 -1300 2 1 {name=p3 lab=A} +C {devices/opin.sym} 1310 -1300 0 0 {name=p4 lab=Y}
diff --git a/xschem/inv_x6.sym b/xschem/inv_x6.sym new file mode 100755 index 0000000..2610513 --- /dev/null +++ b/xschem/inv_x6.sym
@@ -0,0 +1,24 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -45 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +B 5 147.5 -22.5 152.5 -17.5 {name=VP dir=inout } +L 7 130 -20 150 -20 {} +T {VP} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=A dir=in } +L 4 -150 -20 -130 -20 {} +T {A} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=Y dir=out } +L 4 130 0 150 0 {} +T {Y} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=VSUBS dir=inout } +L 7 130 20 150 20 {} +T {VSUBS} 125 16 0 1 0.2 0.2 {}
diff --git a/xschem/level_up_shifter_2x.sch b/xschem/level_up_shifter_2x.sch new file mode 100755 index 0000000..e4260d9 --- /dev/null +++ b/xschem/level_up_shifter_2x.sch
@@ -0,0 +1,245 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 160 -250 160 -220 { +lab=inb} +N 160 -260 160 -250 { +lab=inb} +N 120 -290 120 -190 { +lab=in} +N 50 -240 120 -240 { +lab=in} +N 160 -240 220 -240 { +lab=inb} +N 220 -240 260 -240 { +lab=inb} +N 160 -190 160 -160 { +lab=vssd1} +N 160 -160 160 -110 { +lab=vssd1} +N 160 -320 160 -290 { +lab=vccd1} +N 160 -370 160 -320 { +lab=vccd1} +N 450 -310 450 -250 { +lab=outb} +N 450 -240 540 -240 { +lab=outb} +N 550 -240 550 -210 { +lab=outb} +N 450 -250 450 -240 { +lab=outb} +N 550 -180 550 -150 { +lab=vssd1} +N 550 -150 550 -110 { +lab=vssd1} +N 470 -180 510 -180 { +lab=in} +N 650 -310 650 -240 { +lab=outb} +N 540 -240 650 -240 { +lab=outb} +N 690 -340 730 -340 { +lab=out} +N 380 -340 410 -340 { +lab=inb} +N 450 -340 480 -340 { +lab=vssd1} +N 480 -340 520 -340 { +lab=vssd1} +N 650 -370 650 -340 { +lab=vdda1} +N 650 -410 650 -370 { +lab=vdda1} +N 450 -410 450 -370 { +lab=vdda1} +N 450 -410 650 -410 { +lab=vdda1} +N 550 -450 550 -410 { +lab=vdda1} +N 1100 -310 1100 -250 { +lab=out} +N 1000 -240 1000 -210 { +lab=out} +N 1100 -250 1100 -240 { +lab=out} +N 1000 -180 1000 -150 { +lab=vssd1} +N 1000 -150 1000 -110 { +lab=vssd1} +N 1040 -180 1080 -180 { +lab=inb} +N 900 -310 900 -240 { +lab=out} +N 900 -240 1010 -240 { +lab=out} +N 820 -340 860 -340 { +lab=outb} +N 1140 -340 1170 -340 { +lab=in} +N 1070 -340 1100 -340 { +lab=vssd1} +N 1030 -340 1070 -340 { +lab=vssd1} +N 900 -370 900 -340 { +lab=vdda1} +N 900 -410 900 -370 { +lab=vdda1} +N 1100 -410 1100 -370 { +lab=vdda1} +N 900 -410 1100 -410 { +lab=vdda1} +N 1010 -450 1010 -410 { +lab=vdda1} +N 650 -240 810 -240 { +lab=outb} +N 820 -340 820 -240 { +lab=outb} +N 810 -240 820 -240 { +lab=outb} +N 730 -340 730 -230 { +lab=out} +N 1010 -240 1100 -240 { +lab=out} +N 730 -220 1000 -220 { +lab=out} +N 730 -230 730 -220 { +lab=out} +N 1010 -220 1080 -220 { +lab=out} +N 1000 -220 1010 -220 { +lab=out} +N 550 -220 620 -220 { +lab=outb} +C {sky130_fd_pr/nfet_01v8.sym} 140 -190 0 0 {name=M1 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 140 -290 0 0 {name=M2 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {devices/ipin.sym} 50 -240 0 0 {name=p1 lab=in} +C {devices/lab_pin.sym} 260 -240 2 0 {name=l1 sig_type=std_logic lab=inb} +C {devices/iopin.sym} 160 -370 3 0 {name=p2 lab=vccd1} +C {devices/iopin.sym} 160 -120 1 0 {name=p3 lab=vssd1 +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 530 -180 0 0 {name=M3 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 430 -340 0 0 {name=M4 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 550 -110 3 0 {name=l2 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 470 -180 0 0 {name=l3 sig_type=std_logic lab=in} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 670 -340 0 1 {name=M5 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 520 -340 2 0 {name=l4 sig_type=std_logic lab=vssd1} +C {devices/iopin.sym} 550 -440 3 0 {name=p4 lab=vdda1} +C {devices/lab_pin.sym} 380 -340 0 0 {name=l5 sig_type=std_logic lab=inb} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1020 -180 0 1 {name=M6 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1120 -340 0 1 {name=M7 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1000 -110 1 1 {name=l6 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1080 -180 0 1 {name=l7 sig_type=std_logic lab=inb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 880 -340 0 0 {name=M8 +L=0.5 +W=1 +nf=1 +mult=2 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1030 -340 2 1 {name=l8 sig_type=std_logic lab=vssd1} +C {devices/lab_pin.sym} 1170 -340 0 1 {name=l9 sig_type=std_logic lab=in} +C {devices/lab_pin.sym} 1010 -450 1 0 {name=l10 sig_type=std_logic lab=vdda1} +C {devices/opin.sym} 1080 -220 0 0 {name=p5 lab=out} +C {devices/opin.sym} 620 -220 0 0 {name=p6 lab=outb}
diff --git a/xschem/level_up_shifter_2x.sym b/xschem/level_up_shifter_2x.sym new file mode 100755 index 0000000..404a4de --- /dev/null +++ b/xschem/level_up_shifter_2x.sym
@@ -0,0 +1,29 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -103.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 147.5 -42.5 152.5 -37.5 {name=vdda1 dir=inout } +L 7 130 -40 150 -40 {} +T {vdda1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=vccd1 dir=inout } +L 7 130 -20 150 -20 {} +T {vccd1} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=in dir=in } +L 4 -150 -40 -130 -40 {} +T {in} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=outb dir=out } +L 4 130 0 150 0 {} +T {outb} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=out dir=out } +L 4 130 20 150 20 {} +T {out} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=vssd1 dir=inout } +L 7 130 40 150 40 {} +T {vssd1} 125 36 0 1 0.2 0.2 {}
diff --git a/xschem/level_up_shifter_x4.sch b/xschem/level_up_shifter_x4.sch new file mode 100755 index 0000000..7a00a2f --- /dev/null +++ b/xschem/level_up_shifter_x4.sch
@@ -0,0 +1,245 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 160 -250 160 -220 { +lab=inb} +N 160 -260 160 -250 { +lab=inb} +N 120 -290 120 -190 { +lab=in} +N 50 -240 120 -240 { +lab=in} +N 160 -240 220 -240 { +lab=inb} +N 220 -240 260 -240 { +lab=inb} +N 160 -190 160 -160 { +lab=VSUBS} +N 160 -160 160 -110 { +lab=VSUBS} +N 160 -320 160 -290 { +lab=vccd1} +N 160 -370 160 -320 { +lab=vccd1} +N 450 -310 450 -250 { +lab=outb} +N 450 -240 540 -240 { +lab=outb} +N 550 -240 550 -210 { +lab=outb} +N 450 -250 450 -240 { +lab=outb} +N 550 -180 550 -150 { +lab=VSUBS} +N 550 -150 550 -110 { +lab=VSUBS} +N 470 -180 510 -180 { +lab=in} +N 650 -310 650 -240 { +lab=outb} +N 540 -240 650 -240 { +lab=outb} +N 690 -340 730 -340 { +lab=out} +N 380 -340 410 -340 { +lab=inb} +N 450 -340 480 -340 { +lab=VSUBS} +N 480 -340 520 -340 { +lab=VSUBS} +N 650 -370 650 -340 { +lab=vdda1} +N 650 -410 650 -370 { +lab=vdda1} +N 450 -410 450 -370 { +lab=vdda1} +N 450 -410 650 -410 { +lab=vdda1} +N 550 -450 550 -410 { +lab=vdda1} +N 1100 -310 1100 -250 { +lab=out} +N 1000 -240 1000 -210 { +lab=out} +N 1100 -250 1100 -240 { +lab=out} +N 1000 -180 1000 -150 { +lab=VSUBS} +N 1000 -150 1000 -110 { +lab=VSUBS} +N 1040 -180 1080 -180 { +lab=inb} +N 900 -310 900 -240 { +lab=out} +N 900 -240 1010 -240 { +lab=out} +N 820 -340 860 -340 { +lab=outb} +N 1140 -340 1170 -340 { +lab=in} +N 1070 -340 1100 -340 { +lab=VSUBS} +N 1030 -340 1070 -340 { +lab=VSUBS} +N 900 -370 900 -340 { +lab=vdda1} +N 900 -410 900 -370 { +lab=vdda1} +N 1100 -410 1100 -370 { +lab=vdda1} +N 900 -410 1100 -410 { +lab=vdda1} +N 1010 -450 1010 -410 { +lab=vdda1} +N 650 -240 810 -240 { +lab=outb} +N 820 -340 820 -240 { +lab=outb} +N 810 -240 820 -240 { +lab=outb} +N 730 -340 730 -230 { +lab=out} +N 1010 -240 1100 -240 { +lab=out} +N 730 -220 1000 -220 { +lab=out} +N 730 -230 730 -220 { +lab=out} +N 1010 -220 1080 -220 { +lab=out} +N 1000 -220 1010 -220 { +lab=out} +N 550 -220 620 -220 { +lab=outb} +C {sky130_fd_pr/nfet_01v8.sym} 140 -190 0 0 {name=M1 +L=0.15 +W=1 +nf=1 +mult=1 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_01v8 +spiceprefix=X +} +C {sky130_fd_pr/pfet_01v8.sym} 140 -290 0 0 {name=M2 +L=0.15 +W=1 +nf=1 +mult=3 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_01v8 +spiceprefix=X +} +C {devices/ipin.sym} 50 -240 0 0 {name=p1 lab=in} +C {devices/lab_pin.sym} 260 -240 2 0 {name=l1 sig_type=std_logic lab=inb} +C {devices/iopin.sym} 160 -370 3 0 {name=p2 lab=vccd1} +C {devices/iopin.sym} 160 -120 1 0 {name=p3 lab=VSUBS +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 530 -180 0 0 {name=M3 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 430 -340 0 0 {name=M4 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 550 -110 3 0 {name=l2 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 470 -180 0 0 {name=l3 sig_type=std_logic lab=in} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 670 -340 0 1 {name=M5 +L=0.5 +W=1 +nf=1 +mult=3 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 550 -440 3 0 {name=p4 lab=vdda1} +C {devices/lab_pin.sym} 380 -340 0 0 {name=l5 sig_type=std_logic lab=inb} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1020 -180 0 1 {name=M6 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1120 -340 0 1 {name=M7 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1080 -180 0 1 {name=l7 sig_type=std_logic lab=inb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 880 -340 0 0 {name=M8 +L=0.5 +W=1 +nf=1 +mult=3 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1170 -340 0 1 {name=l9 sig_type=std_logic lab=in} +C {devices/lab_pin.sym} 1010 -450 1 0 {name=l10 sig_type=std_logic lab=vdda1} +C {devices/opin.sym} 1080 -220 0 0 {name=p5 lab=out} +C {devices/opin.sym} 620 -220 0 0 {name=p6 lab=outb} +C {devices/lab_pin.sym} 1000 -110 3 0 {name=l6 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 520 -340 2 0 {name=l4 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1030 -340 2 1 {name=l8 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/level_up_shifter_x4.sym b/xschem/level_up_shifter_x4.sym new file mode 100755 index 0000000..13ab661 --- /dev/null +++ b/xschem/level_up_shifter_x4.sym
@@ -0,0 +1,30 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -103.5 -6 0 0 0.3 0.3 {} +T {@name} 135 -62 0 0 0.2 0.2 {} +L 4 -130 -50 130 -50 {} +L 4 -130 50 130 50 {} +L 4 -130 -50 -130 50 {} +L 4 130 -50 130 50 {} +B 5 147.5 -42.5 152.5 -37.5 {name=vdda1 dir=inout } +L 7 130 -40 150 -40 {} +T {vdda1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=vccd1 dir=inout } +L 7 130 -20 150 -20 {} +T {vccd1} 125 -24 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=in dir=in } +L 4 -150 -40 -130 -40 {} +T {in} -125 -44 0 0 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=outb dir=out } +L 4 130 0 150 0 {} +T {outb} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=out dir=out } +L 4 130 20 150 20 {} +T {out} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=VSUBS dir=inout } +L 7 130 40 150 40 {} +T {VSUBS} 125 36 0 1 0.2 0.2 {}
diff --git a/xschem/mimcap_stacked_57x50.sch b/xschem/mimcap_stacked_57x50.sch new file mode 100755 index 0000000..396a997 --- /dev/null +++ b/xschem/mimcap_stacked_57x50.sch
@@ -0,0 +1,22 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 1120 -1660 1310 -1660 { +lab=vssd1} +N 1220 -1660 1220 -1630 { +lab=vssd1} +N 1120 -1760 1120 -1720 { +lab=sig} +N 1120 -1760 1310 -1760 { +lab=sig} +N 1310 -1760 1310 -1720 { +lab=sig} +N 1220 -1800 1220 -1760 { +lab=sig} +C {sky130_fd_pr/cap_mim_m3_1.sym} 1120 -1690 0 0 {name=C1 model=cap_mim_m3_1 W=5 L=5 MF=2850 spiceprefix=X} +C {devices/iopin.sym} 1220 -1630 3 1 {name=p2 lab=vssd1} +C {devices/iopin.sym} 1220 -1800 1 1 {name=p1 lab=sig} +C {sky130_fd_pr/cap_mim_m3_2.sym} 1310 -1690 2 1 {name=C3 model=cap_mim_m3_2 W=5 L=5 MF=2850 spiceprefix=X}
diff --git a/xschem/mimcap_stacked_57x50.sym b/xschem/mimcap_stacked_57x50.sym new file mode 100755 index 0000000..5ce53fa --- /dev/null +++ b/xschem/mimcap_stacked_57x50.sym
@@ -0,0 +1,17 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} +T {@symname} -108 -6 0 0 0.3 0.3 {} +T {@name} 135 -32 0 0 0.2 0.2 {} +L 4 -130 -20 130 -20 {} +L 4 -130 20 130 20 {} +L 4 -130 -20 -130 20 {} +L 4 130 -20 130 20 {} +B 5 147.5 -12.5 152.5 -7.5 {name=sig dir=inout } +L 7 130 -10 150 -10 {} +T {sig} 125 -14 0 1 0.2 0.2 {} +B 5 147.5 7.5 152.5 12.5 {name=vssd1 dir=inout } +L 7 130 10 150 10 {} +T {vssd1} 125 6 0 1 0.2 0.2 {}
diff --git a/xschem/nand2_x6.sch b/xschem/nand2_x6.sch new file mode 100755 index 0000000..6589907 --- /dev/null +++ b/xschem/nand2_x6.sch
@@ -0,0 +1,116 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 1260 -940 1260 -900 { +lab=VSUBS} +N 1260 -970 1260 -940 { +lab=VSUBS} +N 1140 -970 1220 -970 { +lab=A} +N 1140 -1030 1220 -1030 { +lab=B} +N 1260 -1100 1260 -1060 { +lab=Y} +N 1150 -1150 1150 -1100 { +lab=Y} +N 1150 -1100 1370 -1100 { +lab=Y} +N 1370 -1150 1370 -1100 { +lab=Y} +N 1370 -1210 1370 -1180 { +lab=VP} +N 1150 -1210 1150 -1180 { +lab=VP} +N 1150 -1230 1150 -1210 { +lab=VP} +N 1150 -1230 1370 -1230 { +lab=VP} +N 1370 -1230 1370 -1210 { +lab=VP} +N 1260 -1250 1260 -1230 { +lab=VP} +N 1410 -1180 1490 -1180 { +lab=B} +N 1030 -1180 1110 -1180 { +lab=A} +N 1260 -970 1300 -970 { +lab=VSUBS} +N 1300 -1030 1300 -970 { +lab=VSUBS} +N 1260 -1030 1300 -1030 { +lab=VSUBS} +N 1260 -1080 1360 -1080 { +lab=Y} +N 1360 -1080 1410 -1080 { +lab=Y} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1240 -1030 0 0 {name=M1 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1240 -970 0 0 {name=M2 +L=0.5 +W=1 +nf=1 +mult=4 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1260 -900 3 0 {name=l3 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1140 -1030 0 0 {name=l2 sig_type=std_logic lab=B} +C {devices/lab_pin.sym} 1140 -970 0 0 {name=l4 sig_type=std_logic lab=A} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 1130 -1180 0 0 {name=M3 +L=0.5 +W=1 +nf=1 +mult=6 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 1390 -1180 0 1 {name=M4 +L=0.5 +W=1 +nf=1 +mult=6 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 1490 -1180 0 1 {name=l5 sig_type=std_logic lab=B} +C {devices/lab_pin.sym} 1030 -1180 0 0 {name=l6 sig_type=std_logic lab=A} +C {devices/lab_pin.sym} 1260 -1250 1 0 {name=l7 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 1030 -1320 0 1 {name=p1 lab=VP} +C {devices/iopin.sym} 1030 -1300 0 1 {name=p2 lab=VSUBS} +C {devices/ipin.sym} 1030 -1280 0 0 {name=p3 lab=A} +C {devices/ipin.sym} 1030 -1260 0 0 {name=p4 lab=B} +C {devices/lab_pin.sym} 1410 -1080 0 1 {name=l1 sig_type=std_logic lab=Y} +C {devices/opin.sym} 1020 -1240 0 0 {name=p5 lab=Y}
diff --git a/xschem/nand2_x6.sym b/xschem/nand2_x6.sym new file mode 100755 index 0000000..c0dcc79 --- /dev/null +++ b/xschem/nand2_x6.sym
@@ -0,0 +1,27 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -54 -6 0 0 0.3 0.3 {} +T {@name} 135 -42 0 0 0.2 0.2 {} +L 4 -130 -30 130 -30 {} +L 4 -130 30 130 30 {} +L 4 -130 -30 -130 30 {} +L 4 130 -30 130 30 {} +B 5 147.5 -22.5 152.5 -17.5 {name=VP dir=inout } +L 7 130 -20 150 -20 {} +T {VP} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=VSUBS dir=inout } +L 7 130 0 150 0 {} +T {VSUBS} 125 -4 0 1 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=A dir=in } +L 4 -150 -20 -130 -20 {} +T {A} -125 -24 0 0 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=B dir=in } +L 4 -150 0 -130 0 {} +T {B} -125 -4 0 0 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Y dir=out } +L 4 130 20 150 20 {} +T {Y} 125 16 0 1 0.2 0.2 {}
diff --git a/xschem/reram.sym b/xschem/reram.sym new file mode 100755 index 0000000..ae3133e --- /dev/null +++ b/xschem/reram.sym
@@ -0,0 +1,45 @@ +v {xschem version=3.0.0 file_version=1.2 + +* Copyright 2021 Stefan Frederik Schippers +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +} +G {} +K {type=reram +format="@spiceprefix@name @pinlist sky130_fd_pr__@model m=@mult" +template="name=R1 +model=reram_reram_cell +mult=1 +spiceprefix=X" +device_model=".model reram_reram_cell rram2 rram2_params.scs" + +} +V {} +S {} +E {} +L 4 0 -30 0 -15 {} +L 4 -3.75 -15 0 -15 {} +L 4 -3.75 -15 -3.75 -5 {} +L 4 -3.75 -5 3.75 -5 {} +L 4 3.75 -5 3.75 5 {} +L 4 -3.75 5 3.75 5 {} +L 4 -3.75 5 -3.75 15 {} +L 4 -3.75 15 0 15 {} +L 4 0 15 0 30 {} +B 5 -2.5 27.5 2.5 32.5 {name=BE dir=inout} +B 5 -2.5 -32.5 2.5 -27.5 {name=TE dir=inout} +T {@name} 15 -13.75 0 0 0.2 0.2 {} +T {@model} 15 2.5 0 0 0.2 0.2 {} +T {TE} 10 -28.75 0 0 0.2 0.2 {} +T {BE} 10 28.75 2 1 0.2 0.2 {}
diff --git a/xschem/row_driver_x30.sch b/xschem/row_driver_x30.sch new file mode 100755 index 0000000..b570027 --- /dev/null +++ b/xschem/row_driver_x30.sch
@@ -0,0 +1,265 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 1220 -320 1220 -280 { +lab=#net1} +N 690 -320 690 -280 { +lab=#net2} +N 170 -320 170 -280 { +lab=#net3} +N 100 -350 130 -350 { +lab=SWrplus} +N 170 -450 170 -380 { +lab=row} +N 170 -350 230 -350 { +lab=VP} +N 490 -350 520 -350 { +lab=SWref} +N 560 -350 610 -350 { +lab=VSUBS} +N 1150 -350 1180 -350 { +lab=SWrminus} +N 1220 -350 1270 -350 { +lab=VSUBS} +N 560 -450 560 -380 { +lab=row} +N 1220 -450 1220 -380 { +lab=row} +N 270 -450 560 -450 { +lab=row} +N 560 -450 850 -450 { +lab=row} +N 690 -540 690 -450 { +lab=row} +N 170 -220 170 -180 { +lab=Vrplus} +N 90 -250 130 -250 { +lab=Vgpr} +N 170 -250 230 -250 { +lab=VP} +N 1220 -250 1270 -250 { +lab=VSUBS} +N 1150 -250 1180 -250 { +lab=Vgnr} +N 1220 -220 1220 -180 { +lab=Vrminus} +N 690 -170 790 -170 { +lab=#net2} +N 450 -110 450 -60 { +lab=Vref} +N 340 -140 370 -140 { +lab=#net4} +N 300 -140 300 -60 { +lab=WR} +N 1010 -140 1010 -60 { +lab=SAMPLE} +N 880 -110 880 -60 { +lab=Vsample} +N 690 -280 690 -170 { +lab=#net2} +N 810 -450 810 -380 { +lab=row} +N 850 -450 1220 -450 { +lab=row} +N 560 -320 810 -320 { +lab=#net2} +N 850 -350 880 -350 { +lab=SWrefb} +N 940 -140 970 -140 { +lab=VSUBS} +N 340 -170 510 -170 { +lab=#net2} +N 340 -110 540 -110 { +lab=Vref} +N 170 -450 270 -450 { +lab=row} +N 520 -140 550 -140 { +lab=VP} +N 770 -350 810 -350 { +lab=VP} +N 790 -140 820 -140 { +lab=VP} +N 790 -170 970 -170 { +lab=#net2} +N 610 -170 690 -170 { +lab=#net2} +N 590 -140 590 -60 { +lab=WRb} +N 540 -110 550 -110 { +lab=Vref} +N 510 -170 610 -170 { +lab=#net2} +N 790 -110 970 -110 { +lab=Vsample} +N 750 -140 750 -60 { +lab=SAMPLEb} +C {devices/iopin.sym} 450 -70 1 0 {name=p1 lab=Vref} +C {devices/iopin.sym} 170 -180 1 0 {name=p2 lab=Vrplus} +C {devices/iopin.sym} 1220 -180 3 1 {name=p3 lab=Vrminus} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 150 -350 2 1 {name=M4 +L=0.5 +W=1 +nf=1 +mult=30 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 170 -510 0 0 {name=p4 lab=VP} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 540 -350 0 0 {name=M1 +L=0.5 +W=1 +nf=1 +mult=11 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 230 -350 2 0 {name=l1 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 100 -350 2 0 {name=p5 lab=SWrplus} +C {devices/iopin.sym} 490 -350 2 0 {name=p6 lab=SWref} +C {devices/iopin.sym} 170 -490 0 0 {name=p7 lab=VSUBS} +C {devices/lab_pin.sym} 610 -350 2 0 {name=l2 sig_type=std_logic lab=VSUBS} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1200 -350 0 0 {name=M2 +L=0.5 +W=1 +nf=1 +mult=15 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 1150 -350 2 0 {name=p8 lab=SWrminus} +C {devices/iopin.sym} 690 -540 3 0 {name=p9 lab=row} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 150 -250 2 1 {name=M3 +L=0.5 +W=1 +nf=1 +mult=30 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 100 -250 2 0 {name=p10 lab=Vgpr} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 1200 -250 0 0 {name=M5 +L=0.5 +W=1 +nf=1 +mult=15 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 230 -250 2 0 {name=l4 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 1150 -250 2 0 {name=p11 lab=Vgnr} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 990 -140 0 1 {name=M7 +L=0.5 +W=1 +nf=1 +mult=11 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {sky130_fd_pr/nfet_g5v0d10v5.sym} 320 -140 0 0 {name=M6 +L=0.5 +W=1 +nf=1 +mult=11 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=nfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 1010 -70 1 0 {name=p12 lab=SAMPLE} +C {devices/iopin.sym} 300 -70 1 0 {name=p13 lab=WR} +C {devices/iopin.sym} 880 -70 1 0 {name=p14 lab=Vsample} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 830 -350 2 0 {name=M8 +L=0.5 +W=1 +nf=1 +mult=22 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 880 -350 2 1 {name=p15 lab=SWrefb} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 570 -140 2 0 {name=M9 +L=0.5 +W=1 +nf=1 +mult=22 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/iopin.sym} 590 -70 3 1 {name=p16 lab=WRb} +C {devices/lab_pin.sym} 770 -350 2 1 {name=l8 sig_type=std_logic lab=VP} +C {devices/lab_pin.sym} 520 -140 2 1 {name=l9 sig_type=std_logic lab=VP} +C {sky130_fd_pr/pfet_g5v0d10v5.sym} 770 -140 2 1 {name=M10 +L=0.5 +W=1 +nf=1 +mult=22 +ad="'int((nf+1)/2) * W/nf * 0.29'" +pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" +as="'int((nf+2)/2) * W/nf * 0.29'" +ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" +nrd="'0.29 / W'" nrs="'0.29 / W'" +sa=0 sb=0 sd=0 +model=pfet_g5v0d10v5 +spiceprefix=X +} +C {devices/lab_pin.sym} 820 -140 2 0 {name=l10 sig_type=std_logic lab=VP} +C {devices/iopin.sym} 750 -70 3 1 {name=p17 lab=SAMPLEb} +C {devices/lab_pin.sym} 1270 -350 2 0 {name=l3 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 1270 -250 2 0 {name=l5 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 940 -140 2 1 {name=l11 sig_type=std_logic lab=VSUBS} +C {devices/lab_pin.sym} 370 -140 2 0 {name=l7 sig_type=std_logic lab=VSUBS}
diff --git a/xschem/row_driver_x30.sym b/xschem/row_driver_x30.sym new file mode 100755 index 0000000..495e121 --- /dev/null +++ b/xschem/row_driver_x30.sym
@@ -0,0 +1,63 @@ +v {xschem version=3.0.0 file_version=1.2} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -81 -6 0 0 0.3 0.3 {} +T {@name} 135 -182 0 0 0.2 0.2 {} +L 4 -130 -170 130 -170 {} +L 4 -130 170 130 170 {} +L 4 -130 -170 -130 170 {} +L 4 130 -170 130 170 {} +B 5 147.5 -162.5 152.5 -157.5 {name=row dir=inout } +L 7 130 -160 150 -160 {} +T {row} 125 -164 0 1 0.2 0.2 {} +B 5 147.5 -142.5 152.5 -137.5 {name=VP dir=inout } +L 7 130 -140 150 -140 {} +T {VP} 125 -144 0 1 0.2 0.2 {} +B 5 147.5 -122.5 152.5 -117.5 {name=VSUBS dir=inout } +L 7 130 -120 150 -120 {} +T {VSUBS} 125 -124 0 1 0.2 0.2 {} +B 5 147.5 -102.5 152.5 -97.5 {name=SWref dir=inout } +L 7 130 -100 150 -100 {} +T {SWref} 125 -104 0 1 0.2 0.2 {} +B 5 147.5 -82.5 152.5 -77.5 {name=SWrefb dir=inout } +L 7 130 -80 150 -80 {} +T {SWrefb} 125 -84 0 1 0.2 0.2 {} +B 5 147.5 -62.5 152.5 -57.5 {name=SWrplus dir=inout } +L 7 130 -60 150 -60 {} +T {SWrplus} 125 -64 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=SWrminus dir=inout } +L 7 130 -40 150 -40 {} +T {SWrminus} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=Vgnr dir=inout } +L 7 130 -20 150 -20 {} +T {Vgnr} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=Vgpr dir=inout } +L 7 130 0 150 0 {} +T {Vgpr} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vrminus dir=inout } +L 7 130 20 150 20 {} +T {Vrminus} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=Vrplus dir=inout } +L 7 130 40 150 40 {} +T {Vrplus} 125 36 0 1 0.2 0.2 {} +B 5 147.5 57.5 152.5 62.5 {name=Vsample dir=inout } +L 7 130 60 150 60 {} +T {Vsample} 125 56 0 1 0.2 0.2 {} +B 5 147.5 77.5 152.5 82.5 {name=WR dir=inout } +L 7 130 80 150 80 {} +T {WR} 125 76 0 1 0.2 0.2 {} +B 5 147.5 97.5 152.5 102.5 {name=SAMPLE dir=inout } +L 7 130 100 150 100 {} +T {SAMPLE} 125 96 0 1 0.2 0.2 {} +B 5 147.5 117.5 152.5 122.5 {name=SAMPLEb dir=inout } +L 7 130 120 150 120 {} +T {SAMPLEb} 125 116 0 1 0.2 0.2 {} +B 5 147.5 137.5 152.5 142.5 {name=WRb dir=inout } +L 7 130 140 150 140 {} +T {WRb} 125 136 0 1 0.2 0.2 {} +B 5 147.5 157.5 152.5 162.5 {name=Vref dir=inout } +L 7 130 160 150 160 {} +T {Vref} 125 156 0 1 0.2 0.2 {}
diff --git a/xschem/row_drivers_16x1.sch b/xschem/row_drivers_16x1.sch new file mode 100755 index 0000000..1c82201 --- /dev/null +++ b/xschem/row_drivers_16x1.sch
@@ -0,0 +1,964 @@ +v {xschem version=3.0.0 file_version=1.2 } +G {} +K {} +V {} +S {} +E {} +N 740 -780 740 -500 { +lab=vdda1} +N 720 -800 720 -520 { +lab=vccd1} +N 760 -1500 760 -1210 { +lab=Vref} +N 720 -1090 720 -800 { +lab=vccd1} +N 740 -1070 740 -780 { +lab=vdda1} +N 640 -210 740 -210 { +lab=vdda1} +N 780 -1460 780 -1170 { +lab=Vrplus} +N 780 -1170 780 -880 { +lab=Vrplus} +N 800 -1480 800 -1190 { +lab=Vsample} +N 700 -250 700 -90 { +lab=VSUBS} +N 700 -820 700 -540 { +lab=VSUBS} +N 700 -1110 700 -820 { +lab=VSUBS} +N 640 -230 720 -230 { +lab=vccd1} +N 640 -250 700 -250 { +lab=VSUBS} +N 640 -500 740 -500 { +lab=vdda1} +N 640 -520 720 -520 { +lab=vccd1} +N 640 -540 700 -540 { +lab=VSUBS} +N 740 -210 740 -90 { +lab=vdda1} +N 720 -230 720 -90 { +lab=vccd1} +N 640 -330 800 -330 { +lab=Vsample} +N 640 -350 760 -350 { +lab=Vref} +N 640 -310 780 -310 { +lab=Vrplus} +N 640 -270 850 -270 { +lab=row0} +N 640 -620 800 -620 { +lab=Vsample} +N 640 -640 760 -640 { +lab=Vref} +N 640 -600 780 -600 { +lab=Vrplus} +N 640 -560 850 -560 { +lab=row1} +N 640 -780 740 -780 { +lab=vdda1} +N 640 -800 720 -800 { +lab=vccd1} +N 640 -820 700 -820 { +lab=VSUBS} +N 640 -900 800 -900 { +lab=Vsample} +N 640 -920 760 -920 { +lab=Vref} +N 640 -840 850 -840 { +lab=row2} +N 640 -1070 740 -1070 { +lab=vdda1} +N 640 -1090 720 -1090 { +lab=vccd1} +N 640 -1110 700 -1110 { +lab=VSUBS} +N 640 -1170 780 -1170 { +lab=Vrplus} +N 640 -1130 850 -1130 { +lab=row3} +N 640 -1360 740 -1360 { +lab=vdda1} +N 640 -1380 720 -1380 { +lab=vccd1} +N 640 -1400 700 -1400 { +lab=VSUBS} +N 640 -1480 800 -1480 { +lab=Vsample} +N 640 -1500 760 -1500 { +lab=Vref} +N 640 -1460 780 -1460 { +lab=Vrplus} +N 640 -1420 850 -1420 { +lab=row4} +N 800 -330 800 -90 { +lab=Vsample} +N 760 -350 760 -90 { +lab=Vref} +N 780 -310 780 -90 { +lab=Vrplus} +N 800 -620 800 -330 { +lab=Vsample} +N 760 -640 760 -350 { +lab=Vref} +N 780 -600 780 -310 { +lab=Vrplus} +N 740 -500 740 -210 { +lab=vdda1} +N 720 -520 720 -230 { +lab=vccd1} +N 700 -540 700 -250 { +lab=VSUBS} +N 800 -900 800 -620 { +lab=Vsample} +N 760 -920 760 -640 { +lab=Vref} +N 640 -880 780 -880 { +lab=Vrplus} +N 780 -880 780 -600 { +lab=Vrplus} +N 640 -1190 800 -1190 { +lab=Vsample} +N 800 -1190 800 -900 { +lab=Vsample} +N 640 -1210 760 -1210 { +lab=Vref} +N 640 -1650 740 -1650 { +lab=vdda1} +N 640 -1670 720 -1670 { +lab=vccd1} +N 640 -1690 700 -1690 { +lab=VSUBS} +N 640 -1770 800 -1770 { +lab=Vsample} +N 640 -1790 760 -1790 { +lab=Vref} +N 640 -1750 780 -1750 { +lab=Vrplus} +N 640 -1710 850 -1710 { +lab=row5} +N 640 -1930 740 -1930 { +lab=vdda1} +N 640 -1950 720 -1950 { +lab=vccd1} +N 640 -1970 700 -1970 { +lab=VSUBS} +N 640 -2050 800 -2050 { +lab=Vsample} +N 640 -2070 760 -2070 { +lab=Vref} +N 640 -1990 850 -1990 { +lab=row6} +N 640 -2220 740 -2220 { +lab=vdda1} +N 640 -2240 720 -2240 { +lab=vccd1} +N 640 -2260 700 -2260 { +lab=VSUBS} +N 640 -2320 780 -2320 { +lab=Vrplus} +N 640 -2280 850 -2280 { +lab=row7} +N 640 -2030 780 -2030 { +lab=Vrplus} +N 640 -2340 800 -2340 { +lab=Vsample} +N 640 -2360 760 -2360 { +lab=Vref} +N 740 -3080 740 -2800 { +lab=vdda1} +N 640 -2510 740 -2510 { +lab=vdda1} +N 640 -2530 720 -2530 { +lab=vccd1} +N 640 -2550 700 -2550 { +lab=VSUBS} +N 640 -2800 740 -2800 { +lab=vdda1} +N 640 -2820 720 -2820 { +lab=vccd1} +N 640 -2840 700 -2840 { +lab=VSUBS} +N 640 -2630 800 -2630 { +lab=Vsample} +N 640 -2650 760 -2650 { +lab=Vref} +N 640 -2610 780 -2610 { +lab=Vrplus} +N 640 -2570 850 -2570 { +lab=row8} +N 640 -2920 800 -2920 { +lab=Vsample} +N 640 -2940 760 -2940 { +lab=Vref} +N 640 -2900 780 -2900 { +lab=Vrplus} +N 640 -2860 850 -2860 { +lab=row9} +N 640 -3080 740 -3080 { +lab=vdda1} +N 640 -3100 720 -3100 { +lab=vccd1} +N 640 -3120 700 -3120 { +lab=VSUBS} +N 640 -3200 800 -3200 { +lab=Vsample} +N 640 -3220 760 -3220 { +lab=Vref} +N 640 -3140 850 -3140 { +lab=row10} +N 640 -3370 740 -3370 { +lab=vdda1} +N 640 -3390 720 -3390 { +lab=vccd1} +N 640 -3410 700 -3410 { +lab=VSUBS} +N 640 -3470 780 -3470 { +lab=Vrplus} +N 640 -3430 850 -3430 { +lab=row11} +N 640 -3660 740 -3660 { +lab=vdda1} +N 640 -3680 720 -3680 { +lab=vccd1} +N 640 -3700 700 -3700 { +lab=VSUBS} +N 640 -3780 800 -3780 { +lab=Vsample} +N 640 -3800 760 -3800 { +lab=Vref} +N 640 -3760 780 -3760 { +lab=Vrplus} +N 640 -3720 850 -3720 { +lab=row12} +N 640 -3180 780 -3180 { +lab=Vrplus} +N 640 -3490 800 -3490 { +lab=Vsample} +N 640 -3510 760 -3510 { +lab=Vref} +N 640 -3950 740 -3950 { +lab=vdda1} +N 640 -3970 720 -3970 { +lab=vccd1} +N 640 -3990 700 -3990 { +lab=VSUBS} +N 640 -4070 800 -4070 { +lab=Vsample} +N 640 -4090 760 -4090 { +lab=Vref} +N 640 -4050 780 -4050 { +lab=Vrplus} +N 640 -4010 850 -4010 { +lab=row13} +N 640 -4230 740 -4230 { +lab=vdda1} +N 640 -4250 720 -4250 { +lab=vccd1} +N 640 -4270 700 -4270 { +lab=VSUBS} +N 640 -4350 800 -4350 { +lab=Vsample} +N 640 -4370 760 -4370 { +lab=Vref} +N 640 -4290 850 -4290 { +lab=row14} +N 640 -4520 740 -4520 { +lab=vdda1} +N 640 -4540 720 -4540 { +lab=vccd1} +N 640 -4560 700 -4560 { +lab=VSUBS} +N 640 -4620 780 -4620 { +lab=Vrplus} +N 640 -4580 850 -4580 { +lab=row15} +N 640 -4330 780 -4330 { +lab=Vrplus} +N 640 -4640 800 -4640 { +lab=Vsample} +N 640 -4660 760 -4660 { +lab=Vref} +N 760 -1210 760 -920 { +lab=Vref} +N 740 -1360 740 -1070 { +lab=vdda1} +N 720 -1380 720 -1090 { +lab=vccd1} +N 700 -1400 700 -1110 { +lab=VSUBS} +N 800 -1770 800 -1480 { +lab=Vsample} +N 760 -1790 760 -1500 { +lab=Vref} +N 780 -1750 780 -1460 { +lab=Vrplus} +N 740 -1650 740 -1360 { +lab=vdda1} +N 720 -1670 720 -1380 { +lab=vccd1} +N 700 -1690 700 -1400 { +lab=VSUBS} +N 800 -2050 800 -1770 { +lab=Vsample} +N 760 -2070 760 -1790 { +lab=Vref} +N 740 -1930 740 -1650 { +lab=vdda1} +N 720 -1950 720 -1670 { +lab=vccd1} +N 700 -1970 700 -1690 { +lab=VSUBS} +N 780 -2320 780 -2030 { +lab=Vrplus} +N 780 -2030 780 -1750 { +lab=Vrplus} +N 800 -2340 800 -2050 { +lab=Vsample} +N 760 -2360 760 -2070 { +lab=Vref} +N 740 -2800 740 -2510 { +lab=vdda1} +N 740 -2220 740 -1930 { +lab=vdda1} +N 720 -2240 720 -1950 { +lab=vccd1} +N 700 -2260 700 -1970 { +lab=VSUBS} +N 740 -2510 740 -2220 { +lab=vdda1} +N 720 -2530 720 -2240 { +lab=vccd1} +N 700 -2550 700 -2260 { +lab=VSUBS} +N 800 -2630 800 -2340 { +lab=Vsample} +N 760 -2650 760 -2360 { +lab=Vref} +N 780 -2610 780 -2320 { +lab=Vrplus} +N 800 -2920 800 -2630 { +lab=Vsample} +N 760 -2940 760 -2650 { +lab=Vref} +N 780 -2900 780 -2610 { +lab=Vrplus} +N 720 -2820 720 -2530 { +lab=vccd1} +N 700 -2840 700 -2550 { +lab=VSUBS} +N 800 -3200 800 -2920 { +lab=Vsample} +N 760 -3220 760 -2940 { +lab=Vref} +N 720 -3100 720 -2820 { +lab=vccd1} +N 700 -3120 700 -2840 { +lab=VSUBS} +N 780 -3470 780 -3180 { +lab=Vrplus} +N 740 -3370 740 -3080 { +lab=vdda1} +N 720 -3390 720 -3100 { +lab=vccd1} +N 700 -3410 700 -3120 { +lab=VSUBS} +N 800 -3780 800 -3490 { +lab=Vsample} +N 760 -3800 760 -3510 { +lab=Vref} +N 780 -3760 780 -3470 { +lab=Vrplus} +N 780 -3180 780 -2900 { +lab=Vrplus} +N 800 -3490 800 -3200 { +lab=Vsample} +N 760 -3510 760 -3220 { +lab=Vref} +N 740 -3660 740 -3370 { +lab=vdda1} +N 720 -3680 720 -3390 { +lab=vccd1} +N 700 -3700 700 -3410 { +lab=VSUBS} +N 800 -4070 800 -3780 { +lab=Vsample} +N 760 -4090 760 -3800 { +lab=Vref} +N 780 -4050 780 -3760 { +lab=Vrplus} +N 740 -3950 740 -3660 { +lab=vdda1} +N 720 -3970 720 -3680 { +lab=vccd1} +N 700 -3990 700 -3700 { +lab=VSUBS} +N 800 -4350 800 -4070 { +lab=Vsample} +N 760 -4370 760 -4090 { +lab=Vref} +N 740 -4230 740 -3950 { +lab=vdda1} +N 720 -4250 720 -3970 { +lab=vccd1} +N 700 -4270 700 -3990 { +lab=VSUBS} +N 780 -4620 780 -4330 { +lab=Vrplus} +N 780 -4330 780 -4050 { +lab=Vrplus} +N 800 -4640 800 -4350 { +lab=Vsample} +N 760 -4660 760 -4370 { +lab=Vref} +N 280 -4520 340 -4520 { +lab=A15} +N 280 -4560 340 -4560 { +lab=B15} +N 280 -4230 340 -4230 { +lab=A14} +N 280 -4270 340 -4270 { +lab=B14} +N 280 -3950 340 -3950 { +lab=A13} +N 280 -3990 340 -3990 { +lab=B13} +N 280 -3660 340 -3660 { +lab=A12} +N 280 -3700 340 -3700 { +lab=B12} +N 280 -3370 340 -3370 { +lab=A11} +N 280 -3410 340 -3410 { +lab=B11} +N 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-3160 0 0 {name=l73 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -3180 0 0 {name=l74 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -3200 0 0 {name=l75 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -3220 0 0 {name=l76 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -3240 0 0 {name=l77 sig_type=std_logic lab=WRb} +C {devices/lab_pin.sym} 280 -3390 0 0 {name=l78 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 280 -3430 0 0 {name=l79 sig_type=std_logic lab=Vgnr} +C {devices/lab_pin.sym} 280 -3450 0 0 {name=l80 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -3470 0 0 {name=l81 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -3490 0 0 {name=l82 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -3510 0 0 {name=l83 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -3530 0 0 {name=l84 sig_type=std_logic lab=WRb} +C {devices/lab_pin.sym} 280 -3680 0 0 {name=l85 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 280 -3720 0 0 {name=l86 sig_type=std_logic lab=Vgnr} +C {devices/lab_pin.sym} 280 -3740 0 0 {name=l87 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -3760 0 0 {name=l88 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -3780 0 0 {name=l89 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -3800 0 0 {name=l90 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -3820 0 0 {name=l91 sig_type=std_logic lab=WRb} +C {devices/lab_pin.sym} 280 -3970 0 0 {name=l92 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 280 -4010 0 0 {name=l93 sig_type=std_logic lab=Vgnr} +C {devices/lab_pin.sym} 280 -4030 0 0 {name=l94 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -4050 0 0 {name=l95 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -4070 0 0 {name=l96 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -4090 0 0 {name=l97 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -4110 0 0 {name=l98 sig_type=std_logic lab=WRb} +C {devices/lab_pin.sym} 280 -4250 0 0 {name=l99 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 280 -4290 0 0 {name=l100 sig_type=std_logic lab=Vgnr} +C {devices/lab_pin.sym} 280 -4310 0 0 {name=l101 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -4330 0 0 {name=l102 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -4350 0 0 {name=l103 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -4370 0 0 {name=l104 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -4390 0 0 {name=l105 sig_type=std_logic lab=WRb} +C {devices/lab_pin.sym} 280 -4540 0 0 {name=l106 sig_type=std_logic lab=SEL} +C {devices/lab_pin.sym} 280 -4580 0 0 {name=l107 sig_type=std_logic lab=Vgnr} +C {devices/lab_pin.sym} 280 -4600 0 0 {name=l108 sig_type=std_logic lab=Vgpr} +C {devices/lab_pin.sym} 280 -4620 0 0 {name=l109 sig_type=std_logic lab=WR} +C {devices/lab_pin.sym} 280 -4640 0 0 {name=l110 sig_type=std_logic lab=SAMPLE} +C {devices/lab_pin.sym} 280 -4660 0 0 {name=l111 sig_type=std_logic lab=SAMPLEb} +C {devices/lab_pin.sym} 280 -4680 0 0 {name=l112 sig_type=std_logic lab=WRb}
diff --git a/xschem/row_drivers_16x1.sym b/xschem/row_drivers_16x1.sym new file mode 100755 index 0000000..e021cd0 --- /dev/null +++ b/xschem/row_drivers_16x1.sym
@@ -0,0 +1,199 @@ +v {xschem version=3.0.0 file_version=1.2} +G {} +K {type=subcircuit +format="@name @pinlist @symname" +template="name=x1" +} + +T {@symname} -90 -6 0 0 0.3 0.3 {} +T {@name} 135 -402 0 0 0.2 0.2 {} +L 4 -130 -390 130 -390 {} +L 4 -130 390 130 390 {} +L 4 -130 -390 -130 390 {} +L 4 130 -390 130 390 {} +B 5 -152.5 -382.5 -147.5 -377.5 {name=SEL dir=in } +L 4 -150 -380 -130 -380 {} +T {SEL} -125 -384 0 0 0.2 0.2 {} +B 5 -152.5 -362.5 -147.5 -357.5 {name=Vgnr dir=in } +L 4 -150 -360 -130 -360 {} +T {Vgnr} -125 -364 0 0 0.2 0.2 {} +B 5 -152.5 -342.5 -147.5 -337.5 {name=Vgpr dir=in } +L 4 -150 -340 -130 -340 {} +T {Vgpr} -125 -344 0 0 0.2 0.2 {} +B 5 -152.5 -322.5 -147.5 -317.5 {name=WR dir=in } +L 4 -150 -320 -130 -320 {} +T {WR} -125 -324 0 0 0.2 0.2 {} +B 5 -152.5 -302.5 -147.5 -297.5 {name=SAMPLEb dir=in } +L 4 -150 -300 -130 -300 {} +T {SAMPLEb} -125 -304 0 0 0.2 0.2 {} +B 5 -152.5 -282.5 -147.5 -277.5 {name=SAMPLE dir=in } +L 4 -150 -280 -130 -280 {} +T {SAMPLE} -125 -284 0 0 0.2 0.2 {} +B 5 -152.5 -262.5 -147.5 -257.5 {name=WRb dir=in } +L 4 -150 -260 -130 -260 {} +T {WRb} -125 -264 0 0 0.2 0.2 {} +B 5 147.5 -382.5 152.5 -377.5 {name=row15 dir=inout } +L 7 130 -380 150 -380 {} +T {row15} 125 -384 0 1 0.2 0.2 {} +B 5 -152.5 -242.5 -147.5 -237.5 {name=B15 dir=in } +L 4 -150 -240 -130 -240 {} +T {B15} -125 -244 0 0 0.2 0.2 {} +B 5 -152.5 -222.5 -147.5 -217.5 {name=A15 dir=in } +L 4 -150 -220 -130 -220 {} +T {A15} -125 -224 0 0 0.2 0.2 {} +B 5 147.5 -362.5 152.5 -357.5 {name=row14 dir=inout } +L 7 130 -360 150 -360 {} +T {row14} 125 -364 0 1 0.2 0.2 {} +B 5 -152.5 -202.5 -147.5 -197.5 {name=B14 dir=in } +L 4 -150 -200 -130 -200 {} +T {B14} -125 -204 0 0 0.2 0.2 {} +B 5 -152.5 -182.5 -147.5 -177.5 {name=A14 dir=in } +L 4 -150 -180 -130 -180 {} +T {A14} -125 -184 0 0 0.2 0.2 {} +B 5 147.5 -342.5 152.5 -337.5 {name=row13 dir=inout } +L 7 130 -340 150 -340 {} +T {row13} 125 -344 0 1 0.2 0.2 {} +B 5 -152.5 -162.5 -147.5 -157.5 {name=B13 dir=in } +L 4 -150 -160 -130 -160 {} +T {B13} -125 -164 0 0 0.2 0.2 {} +B 5 -152.5 -142.5 -147.5 -137.5 {name=A13 dir=in } +L 4 -150 -140 -130 -140 {} +T {A13} -125 -144 0 0 0.2 0.2 {} +B 5 147.5 -322.5 152.5 -317.5 {name=row12 dir=inout } +L 7 130 -320 150 -320 {} +T {row12} 125 -324 0 1 0.2 0.2 {} +B 5 -152.5 -122.5 -147.5 -117.5 {name=B12 dir=in } +L 4 -150 -120 -130 -120 {} +T {B12} -125 -124 0 0 0.2 0.2 {} +B 5 -152.5 -102.5 -147.5 -97.5 {name=A12 dir=in } +L 4 -150 -100 -130 -100 {} +T {A12} -125 -104 0 0 0.2 0.2 {} +B 5 147.5 -302.5 152.5 -297.5 {name=row11 dir=inout } +L 7 130 -300 150 -300 {} +T {row11} 125 -304 0 1 0.2 0.2 {} +B 5 -152.5 -82.5 -147.5 -77.5 {name=B11 dir=in } +L 4 -150 -80 -130 -80 {} +T {B11} -125 -84 0 0 0.2 0.2 {} +B 5 -152.5 -62.5 -147.5 -57.5 {name=A11 dir=in } +L 4 -150 -60 -130 -60 {} +T {A11} -125 -64 0 0 0.2 0.2 {} +B 5 147.5 -282.5 152.5 -277.5 {name=row10 dir=inout } +L 7 130 -280 150 -280 {} +T {row10} 125 -284 0 1 0.2 0.2 {} +B 5 -152.5 -42.5 -147.5 -37.5 {name=B10 dir=in } +L 4 -150 -40 -130 -40 {} +T {B10} -125 -44 0 0 0.2 0.2 {} +B 5 -152.5 -22.5 -147.5 -17.5 {name=A10 dir=in } +L 4 -150 -20 -130 -20 {} +T {A10} -125 -24 0 0 0.2 0.2 {} +B 5 147.5 -262.5 152.5 -257.5 {name=row9 dir=inout } +L 7 130 -260 150 -260 {} +T {row9} 125 -264 0 1 0.2 0.2 {} +B 5 -152.5 -2.5 -147.5 2.5 {name=B9 dir=in } +L 4 -150 0 -130 0 {} +T {B9} -125 -4 0 0 0.2 0.2 {} +B 5 -152.5 17.5 -147.5 22.5 {name=A9 dir=in } +L 4 -150 20 -130 20 {} +T {A9} -125 16 0 0 0.2 0.2 {} +B 5 147.5 -242.5 152.5 -237.5 {name=row8 dir=inout } +L 7 130 -240 150 -240 {} +T {row8} 125 -244 0 1 0.2 0.2 {} +B 5 -152.5 37.5 -147.5 42.5 {name=B8 dir=in } +L 4 -150 40 -130 40 {} +T {B8} -125 36 0 0 0.2 0.2 {} +B 5 -152.5 57.5 -147.5 62.5 {name=A8 dir=in } +L 4 -150 60 -130 60 {} +T {A8} -125 56 0 0 0.2 0.2 {} +B 5 147.5 -222.5 152.5 -217.5 {name=row7 dir=inout } +L 7 130 -220 150 -220 {} +T {row7} 125 -224 0 1 0.2 0.2 {} +B 5 -152.5 77.5 -147.5 82.5 {name=B7 dir=in } +L 4 -150 80 -130 80 {} +T {B7} -125 76 0 0 0.2 0.2 {} +B 5 -152.5 97.5 -147.5 102.5 {name=A7 dir=in } +L 4 -150 100 -130 100 {} +T {A7} -125 96 0 0 0.2 0.2 {} +B 5 147.5 -202.5 152.5 -197.5 {name=row6 dir=inout } +L 7 130 -200 150 -200 {} +T {row6} 125 -204 0 1 0.2 0.2 {} +B 5 -152.5 117.5 -147.5 122.5 {name=B6 dir=in } +L 4 -150 120 -130 120 {} +T {B6} -125 116 0 0 0.2 0.2 {} +B 5 -152.5 137.5 -147.5 142.5 {name=A6 dir=in } +L 4 -150 140 -130 140 {} +T {A6} -125 136 0 0 0.2 0.2 {} +B 5 147.5 -182.5 152.5 -177.5 {name=row5 dir=inout } +L 7 130 -180 150 -180 {} +T {row5} 125 -184 0 1 0.2 0.2 {} +B 5 -152.5 157.5 -147.5 162.5 {name=B5 dir=in } +L 4 -150 160 -130 160 {} +T {B5} -125 156 0 0 0.2 0.2 {} +B 5 -152.5 177.5 -147.5 182.5 {name=A5 dir=in } +L 4 -150 180 -130 180 {} +T {A5} -125 176 0 0 0.2 0.2 {} +B 5 147.5 -162.5 152.5 -157.5 {name=row4 dir=inout } +L 7 130 -160 150 -160 {} +T {row4} 125 -164 0 1 0.2 0.2 {} +B 5 -152.5 197.5 -147.5 202.5 {name=B4 dir=in } +L 4 -150 200 -130 200 {} +T {B4} -125 196 0 0 0.2 0.2 {} +B 5 -152.5 217.5 -147.5 222.5 {name=A4 dir=in } +L 4 -150 220 -130 220 {} +T {A4} -125 216 0 0 0.2 0.2 {} +B 5 147.5 -142.5 152.5 -137.5 {name=row3 dir=inout } +L 7 130 -140 150 -140 {} +T {row3} 125 -144 0 1 0.2 0.2 {} +B 5 -152.5 237.5 -147.5 242.5 {name=B3 dir=in } +L 4 -150 240 -130 240 {} +T {B3} -125 236 0 0 0.2 0.2 {} +B 5 -152.5 257.5 -147.5 262.5 {name=A3 dir=in } +L 4 -150 260 -130 260 {} +T {A3} -125 256 0 0 0.2 0.2 {} +B 5 147.5 -122.5 152.5 -117.5 {name=row2 dir=inout } +L 7 130 -120 150 -120 {} +T {row2} 125 -124 0 1 0.2 0.2 {} +B 5 -152.5 277.5 -147.5 282.5 {name=B2 dir=in } +L 4 -150 280 -130 280 {} +T {B2} -125 276 0 0 0.2 0.2 {} +B 5 -152.5 297.5 -147.5 302.5 {name=A2 dir=in } +L 4 -150 300 -130 300 {} +T {A2} -125 296 0 0 0.2 0.2 {} +B 5 147.5 -102.5 152.5 -97.5 {name=row1 dir=inout } +L 7 130 -100 150 -100 {} +T {row1} 125 -104 0 1 0.2 0.2 {} +B 5 -152.5 317.5 -147.5 322.5 {name=B1 dir=in } +L 4 -150 320 -130 320 {} +T {B1} -125 316 0 0 0.2 0.2 {} +B 5 -152.5 337.5 -147.5 342.5 {name=A1 dir=in } +L 4 -150 340 -130 340 {} +T {A1} -125 336 0 0 0.2 0.2 {} +B 5 147.5 -82.5 152.5 -77.5 {name=row0 dir=inout } +L 7 130 -80 150 -80 {} +T {row0} 125 -84 0 1 0.2 0.2 {} +B 5 -152.5 357.5 -147.5 362.5 {name=B0 dir=in } +L 4 -150 360 -130 360 {} +T {B0} -125 356 0 0 0.2 0.2 {} +B 5 -152.5 377.5 -147.5 382.5 {name=A0 dir=in } +L 4 -150 380 -130 380 {} +T {A0} -125 376 0 0 0.2 0.2 {} +B 5 147.5 -62.5 152.5 -57.5 {name=Vsample dir=inout } +L 7 130 -60 150 -60 {} +T {Vsample} 125 -64 0 1 0.2 0.2 {} +B 5 147.5 -42.5 152.5 -37.5 {name=vccd1 dir=inout } +L 7 130 -40 150 -40 {} +T {vccd1} 125 -44 0 1 0.2 0.2 {} +B 5 147.5 -22.5 152.5 -17.5 {name=Vref dir=inout } +L 7 130 -20 150 -20 {} +T {Vref} 125 -24 0 1 0.2 0.2 {} +B 5 147.5 -2.5 152.5 2.5 {name=Vrminus dir=inout } +L 7 130 0 150 0 {} +T {Vrminus} 125 -4 0 1 0.2 0.2 {} +B 5 147.5 17.5 152.5 22.5 {name=Vrplus dir=inout } +L 7 130 20 150 20 {} +T {Vrplus} 125 16 0 1 0.2 0.2 {} +B 5 147.5 37.5 152.5 42.5 {name=VSUBS dir=inout } +L 7 130 40 150 40 {} +T {VSUBS} 125 36 0 1 0.2 0.2 {} +B 5 147.5 57.5 152.5 62.5 {name=vdda1 dir=inout } +L 7 130 60 150 60 {} +T {vdda1} 125 56 0 1 0.2 0.2 {}
diff --git a/xschem/test.data b/xschem/test.data deleted file mode 100644 index c9cde37..0000000 --- a/xschem/test.data +++ /dev/null
@@ -1,101 +0,0 @@ - 7.00000000e-01 -8.93059159e-08 7.00000000e-01 7.00000000e-01 - 7.01000000e-01 -9.08452852e-08 7.01000000e-01 7.01000000e-01 - 7.02000000e-01 -9.24385447e-08 7.02000000e-01 7.02000000e-01 - 7.03000000e-01 -9.40459956e-08 7.03000000e-01 7.03000000e-01 - 7.04000000e-01 -9.56814959e-08 7.04000000e-01 7.04000000e-01 - 7.05000000e-01 -9.73455368e-08 7.05000000e-01 7.05000000e-01 - 7.06000000e-01 -9.90386085e-08 7.06000000e-01 7.06000000e-01 - 7.07000000e-01 -1.00761227e-07 7.07000000e-01 7.07000000e-01 - 7.08000000e-01 -1.02513882e-07 7.08000000e-01 7.08000000e-01 - 7.09000000e-01 -1.04297110e-07 7.09000000e-01 7.09000000e-01 - 7.10000000e-01 -1.06111443e-07 7.10000000e-01 7.10000000e-01 - 7.11000000e-01 -1.07957415e-07 7.11000000e-01 7.11000000e-01 - 7.12000000e-01 -1.09835552e-07 7.12000000e-01 7.12000000e-01 - 7.13000000e-01 -1.11746436e-07 7.13000000e-01 7.13000000e-01 - 7.14000000e-01 -1.13690603e-07 7.14000000e-01 7.14000000e-01 - 7.15000000e-01 -1.15668634e-07 7.15000000e-01 7.15000000e-01 - 7.16000000e-01 -1.17681129e-07 7.16000000e-01 7.16000000e-01 - 7.17000000e-01 -1.19728657e-07 7.17000000e-01 7.17000000e-01 - 7.18000000e-01 -1.21811839e-07 7.18000000e-01 7.18000000e-01 - 7.19000000e-01 -1.23931259e-07 7.19000000e-01 7.19000000e-01 - 7.20000000e-01 -1.26087554e-07 7.20000000e-01 7.20000000e-01 - 7.21000000e-01 -1.28281358e-07 7.21000000e-01 7.21000000e-01 - 7.22000000e-01 -1.30513286e-07 7.22000000e-01 7.22000000e-01 - 7.23000000e-01 -1.32784003e-07 7.23000000e-01 7.23000000e-01 - 7.24000000e-01 -1.35094165e-07 7.24000000e-01 7.24000000e-01 - 7.25000000e-01 -1.37444453e-07 7.25000000e-01 7.25000000e-01 - 7.26000000e-01 -1.39835535e-07 7.26000000e-01 7.26000000e-01 - 7.27000000e-01 -1.42268085e-07 7.27000000e-01 7.27000000e-01 - 7.28000000e-01 -1.44742842e-07 7.28000000e-01 7.28000000e-01 - 7.29000000e-01 -1.47260486e-07 7.29000000e-01 7.29000000e-01 - 7.30000000e-01 -1.49821761e-07 7.30000000e-01 7.30000000e-01 - 7.31000000e-01 -1.52427364e-07 7.31000000e-01 7.31000000e-01 - 7.32000000e-01 -1.55078077e-07 7.32000000e-01 7.32000000e-01 - 7.33000000e-01 -1.57774611e-07 7.33000000e-01 7.33000000e-01 - 7.34000000e-01 -1.60517775e-07 7.34000000e-01 7.34000000e-01 - 7.35000000e-01 -1.63308337e-07 7.35000000e-01 7.35000000e-01 - 7.36000000e-01 -1.66147061e-07 7.36000000e-01 7.36000000e-01 - 7.37000000e-01 -1.69034765e-07 7.37000000e-01 7.37000000e-01 - 7.38000000e-01 -1.71972266e-07 7.38000000e-01 7.38000000e-01 - 7.39000000e-01 -1.74960357e-07 7.39000000e-01 7.39000000e-01 - 7.40000000e-01 -1.77999888e-07 7.40000000e-01 7.40000000e-01 - 7.41000000e-01 -1.81091703e-07 7.41000000e-01 7.41000000e-01 - 7.42000000e-01 -1.84236664e-07 7.42000000e-01 7.42000000e-01 - 7.43000000e-01 -1.87435634e-07 7.43000000e-01 7.43000000e-01 - 7.44000000e-01 -1.90689493e-07 7.44000000e-01 7.44000000e-01 - 7.45000000e-01 -1.93999127e-07 7.45000000e-01 7.45000000e-01 - 7.46000000e-01 -1.97365464e-07 7.46000000e-01 7.46000000e-01 - 7.47000000e-01 -2.00789378e-07 7.47000000e-01 7.47000000e-01 - 7.48000000e-01 -2.04271837e-07 7.48000000e-01 7.48000000e-01 - 7.49000000e-01 -2.07813739e-07 7.49000000e-01 7.49000000e-01 - 7.50000000e-01 -2.11416073e-07 7.50000000e-01 7.50000000e-01 - 7.51000000e-01 -2.15079797e-07 7.51000000e-01 7.51000000e-01 - 7.52000000e-01 -2.18805863e-07 7.52000000e-01 7.52000000e-01 - 7.53000000e-01 -2.22595278e-07 7.53000000e-01 7.53000000e-01 - 7.54000000e-01 -2.26449036e-07 7.54000000e-01 7.54000000e-01 - 7.55000000e-01 -2.30368144e-07 7.55000000e-01 7.55000000e-01 - 7.56000000e-01 -2.34353630e-07 7.56000000e-01 7.56000000e-01 - 7.57000000e-01 -2.38406548e-07 7.57000000e-01 7.57000000e-01 - 7.58000000e-01 -2.42527913e-07 7.58000000e-01 7.58000000e-01 - 7.59000000e-01 -2.46718795e-07 7.59000000e-01 7.59000000e-01 - 7.60000000e-01 -2.50980278e-07 7.60000000e-01 7.60000000e-01 - 7.61000000e-01 -2.55313430e-07 7.61000000e-01 7.61000000e-01 - 7.62000000e-01 -2.59719344e-07 7.62000000e-01 7.62000000e-01 - 7.63000000e-01 -2.64199148e-07 7.63000000e-01 7.63000000e-01 - 7.64000000e-01 -2.68753946e-07 7.64000000e-01 7.64000000e-01 - 7.65000000e-01 -2.73384860e-07 7.65000000e-01 7.65000000e-01 - 7.66000000e-01 -2.78093044e-07 7.66000000e-01 7.66000000e-01 - 7.67000000e-01 -2.82879650e-07 7.67000000e-01 7.67000000e-01 - 7.68000000e-01 -2.87745826e-07 7.68000000e-01 7.68000000e-01 - 7.69000000e-01 -2.92692776e-07 7.69000000e-01 7.69000000e-01 - 7.70000000e-01 -2.97721660e-07 7.70000000e-01 7.70000000e-01 - 7.71000000e-01 -3.02833688e-07 7.71000000e-01 7.71000000e-01 - 7.72000000e-01 -3.08030053e-07 7.72000000e-01 7.72000000e-01 - 7.73000000e-01 -3.13311974e-07 7.73000000e-01 7.73000000e-01 - 7.74000000e-01 -3.18680710e-07 7.74000000e-01 7.74000000e-01 - 7.75000000e-01 -3.24137468e-07 7.75000000e-01 7.75000000e-01 - 7.76000000e-01 -3.29683509e-07 7.76000000e-01 7.76000000e-01 - 7.77000000e-01 -3.35320078e-07 7.77000000e-01 7.77000000e-01 - 7.78000000e-01 -3.41048451e-07 7.78000000e-01 7.78000000e-01 - 7.79000000e-01 -3.46869908e-07 7.79000000e-01 7.79000000e-01 - 7.80000000e-01 -3.52785731e-07 7.80000000e-01 7.80000000e-01 - 7.81000000e-01 -3.58797218e-07 7.81000000e-01 7.81000000e-01 - 7.82000000e-01 -3.64905663e-07 7.82000000e-01 7.82000000e-01 - 7.83000000e-01 -3.71112381e-07 7.83000000e-01 7.83000000e-01 - 7.84000000e-01 -3.77418703e-07 7.84000000e-01 7.84000000e-01 - 7.85000000e-01 -3.83825919e-07 7.85000000e-01 7.85000000e-01 - 7.86000000e-01 -3.90335390e-07 7.86000000e-01 7.86000000e-01 - 7.87000000e-01 -3.96948455e-07 7.87000000e-01 7.87000000e-01 - 7.88000000e-01 -4.03666461e-07 7.88000000e-01 7.88000000e-01 - 7.89000000e-01 -4.10490750e-07 7.89000000e-01 7.89000000e-01 - 7.90000000e-01 -4.17422681e-07 7.90000000e-01 7.90000000e-01 - 7.91000000e-01 -4.24463629e-07 7.91000000e-01 7.91000000e-01 - 7.92000000e-01 -4.31614946e-07 7.92000000e-01 7.92000000e-01 - 7.93000000e-01 -4.38878017e-07 7.93000000e-01 7.93000000e-01 - 7.94000000e-01 -4.46254218e-07 7.94000000e-01 7.94000000e-01 - 7.95000000e-01 -4.53744916e-07 7.95000000e-01 7.95000000e-01 - 7.96000000e-01 -4.61351506e-07 7.96000000e-01 7.96000000e-01 - 7.97000000e-01 -4.69075369e-07 7.97000000e-01 7.97000000e-01 - 7.98000000e-01 -4.76917893e-07 7.98000000e-01 7.98000000e-01 - 7.99000000e-01 -4.84880471e-07 7.99000000e-01 7.99000000e-01 - 8.00000000e-01 -4.92964482e-07 8.00000000e-01 8.00000000e-01
diff --git a/xschem/threshold_test_tb.spice b/xschem/threshold_test_tb.spice deleted file mode 100644 index 3e9804c..0000000 --- a/xschem/threshold_test_tb.spice +++ /dev/null
@@ -1,46 +0,0 @@ -*--------------------------------------------------------------------------- -* SPDX-FileCopyrightText: 2020 Efabless Corporation -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* https://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -* -* SPDX-License-Identifier: Apache-2.0 -*--------------------------------------------------------------------------- -* Threshold test for POR circuit -* Determine gate voltage at which the HV NFET draws 240nA nominal -* -* Result: 0.7575V -*------------------------------------------------------------------- - -.lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt - -*---------------------------- -* Testbench circuit -*---------------------------- -Rtest vdda mir1 1MEG -Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 - -Vgate vin vss DC=0 -Vpwr vdda vss DC=3.3 -Rgnd vss 0 0.1 - -*---------------------------- -* Testbench control -*---------------------------- -.control -* DC sweep from 0.7 to 0.8V -dc Vgate 0.7 0.8 0.001 -wrdata test.data Vpwr#branch vin - -.endc - -.end -
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch index e3cbcec..df8f89d 100644 --- a/xschem/user_analog_project_wrapper.sch +++ b/xschem/user_analog_project_wrapper.sch
@@ -1,180 +1,22257 @@ -v {xschem version=2.9.9 file_version=1.2 } +v {xschem version=3.1.0 file_version=1.2 } G {} K {} V {} S {} E {} -N 3830 -460 3830 -390 { lab=vdda1} -N 3730 -460 3830 -460 { lab=vdda1} -N 3860 -230 3860 -180 { lab=vssa1} -N 3770 -180 3860 -180 { lab=vssa1} -N 3890 -460 3890 -390 { lab=vccd1} -N 3890 -460 3960 -460 { lab=vccd1} -N 3890 -130 3890 -60 { lab=vccd1} -N 3890 -130 3950 -130 { lab=vccd1} -N 3830 -130 3830 -60 { lab=io_analog[4]} -N 3790 -130 3830 -130 { lab=io_analog[4]} -N 3860 100 3860 150 { lab=vssa1} -N 3800 150 3860 150 { lab=vssa1} -N 4010 -10 4110 -10 { lab=gpio_analog[7]} -N 4010 20 4110 20 { lab=io_out[15]} -N 4010 50 4110 50 { lab=io_out[16]} -N 4010 -340 4130 -340 { lab=gpio_analog[3]} -N 4010 -310 4130 -310 { lab=io_out[11]} -N 4010 -280 4130 -280 { lab=io_out[12]} -N 3670 300 3670 340 { lab=io_clamp_low[2]} -N 3670 400 3670 420 { lab=vssa1} -N 3670 440 3670 460 { lab=io_clamp_high[2]} -N 3670 520 3670 530 { lab=vssa1} -N 3670 570 3670 590 { lab=io_clamp_low[1]} -N 3670 650 3670 670 { lab=vssa1} -N 4160 300 4160 330 { lab=io_clamp_high[1]} -N 4160 390 4160 410 { lab=vssa1} -N 4160 440 4160 460 { lab=io_clamp_low[0]} -N 4160 520 4160 530 { lab=vssa1} -N 4160 550 4160 560 { lab=io_clamp_high[0]} -N 4160 620 4160 640 { lab=io_analog[4]} -N 3630 300 3670 300 { lab=io_clamp_low[2]} -N 3630 420 3670 420 { lab=vssa1} -N 3630 440 3670 440 { lab=io_clamp_high[2]} -N 3630 530 3670 530 { lab=vssa1} -N 3630 570 3670 570 { lab=io_clamp_low[1]} -N 3630 670 3670 670 { lab=vssa1} -N 4130 300 4160 300 { lab=io_clamp_high[1]} -N 4130 410 4160 410 { lab=vssa1} -N 4130 440 4160 440 { lab=io_clamp_low[0]} -N 4130 530 4160 530 { lab=vssa1} -N 4130 550 4160 550 { lab=io_clamp_high[0]} -N 4130 640 4160 640 { lab=io_analog[4]} -N 3670 710 3670 750 { lab=io_oeb[12]} -N 3670 810 3670 830 { lab=vssd1} -N 3670 850 3670 870 { lab=io_oeb[16]} -N 3670 930 3670 940 { lab=vssd1} -N 4160 710 4160 740 { lab=io_oeb[11]} -N 4160 800 4160 820 { lab=vssd1} -N 4160 850 4160 870 { lab=#net1} -N 4160 930 4160 940 { lab=vssd1} -N 3630 710 3670 710 { lab=io_oeb[12]} -N 3630 830 3670 830 { lab=vssd1} -N 3630 850 3670 850 { lab=io_oeb[16]} -N 3630 940 3670 940 { lab=vssd1} -N 4130 710 4160 710 { lab=io_oeb[11]} -N 4130 820 4160 820 { lab=vssd1} -N 4130 850 4160 850 { lab=#net1} -N 4130 940 4160 940 { lab=vssd1} -C {example_por.sym} 3860 -310 0 0 {name=x1} -C {example_por.sym} 3860 20 0 0 {name=x2} -C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1} -C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2} -C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1} -C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2} -C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1} -C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2} -C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1} -C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2} -C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i} -C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i} -C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i} -C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i} -C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i} -C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]} -C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]} -C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]} -C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o} -C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]} -C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]} -C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]} -C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]} -C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]} -C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2} -C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]} -C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]} -C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]} -C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]} -C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]} -C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]} -C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]} -C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]} -C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]} -C {devices/lab_pin.sym} 3730 -460 0 0 {name=l1 sig_type=std_logic lab=vdda1} -C {devices/lab_pin.sym} 3770 -180 0 0 {name=l2 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3960 -460 0 1 {name=l3 sig_type=std_logic lab=vccd1} -C {devices/lab_pin.sym} 3950 -130 0 1 {name=l4 sig_type=std_logic lab=vccd1} -C {devices/lab_pin.sym} 3790 -130 0 0 {name=l5 sig_type=std_logic lab=io_analog[4]} -C {devices/lab_pin.sym} 3800 150 0 0 {name=l6 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 -340 0 1 {name=l7 sig_type=std_logic lab=gpio_analog[3]} -C {devices/lab_pin.sym} 4130 -310 0 1 {name=l8 sig_type=std_logic lab=io_out[11]} -C {devices/lab_pin.sym} 4130 -280 0 1 {name=l9 sig_type=std_logic lab=io_out[12]} -C {devices/lab_pin.sym} 4110 -10 0 1 {name=l10 sig_type=std_logic lab=gpio_analog[7]} -C {devices/lab_pin.sym} 4110 20 0 1 {name=l11 sig_type=std_logic lab=io_out[15]} -C {devices/lab_pin.sym} 4110 50 0 1 {name=l12 sig_type=std_logic lab=io_out[16]} -C {sky130_fd_pr/res_generic_m1.sym} 3670 370 0 0 {name=R1 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 490 0 0 {name=R2 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 620 0 0 {name=R4 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 360 0 0 {name=R5 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 490 0 0 {name=R6 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 590 0 0 {name=R7 -W=11 -L=0.25 -model=res_generic_m3 -mult=1} -C {devices/lab_pin.sym} 3630 300 0 0 {name=l13 sig_type=std_logic lab=io_clamp_low[2]} -C {devices/lab_pin.sym} 3630 440 0 0 {name=l14 sig_type=std_logic lab=io_clamp_high[2]} -C {devices/lab_pin.sym} 3630 570 0 0 {name=l15 sig_type=std_logic lab=io_clamp_low[1]} -C {devices/lab_pin.sym} 4130 300 0 0 {name=l16 sig_type=std_logic lab=io_clamp_high[1]} -C {devices/lab_pin.sym} 4130 440 0 0 {name=l17 sig_type=std_logic lab=io_clamp_low[0]} -C {devices/lab_pin.sym} 3630 420 0 0 {name=l18 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3630 530 0 0 {name=l19 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 410 0 0 {name=l20 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 530 0 0 {name=l21 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 3630 670 0 0 {name=l22 sig_type=std_logic lab=vssa1} -C {devices/lab_pin.sym} 4130 550 0 0 {name=l23 sig_type=std_logic lab=io_clamp_high[0]} -C {devices/lab_pin.sym} 4130 640 0 0 {name=l24 sig_type=std_logic lab=io_analog[4]} -C {sky130_fd_pr/res_generic_m1.sym} 3670 780 0 0 {name=R8 -W=0.56 -L=0.49 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 3670 900 0 0 {name=R9 -W=0.56 -L=0.31 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 770 0 0 {name=R11 -W=0.56 -L=0.58 -model=res_generic_m3 -mult=1} -C {sky130_fd_pr/res_generic_m1.sym} 4160 900 0 0 {name=R12 -W=0.56 -L=0.6 -model=res_generic_m3 -mult=1} -C {devices/lab_pin.sym} 4130 850 0 0 {name=l25 sig_type=std_logic lab=io_oeb[15]} -C {devices/lab_pin.sym} 3630 850 0 0 {name=l26 sig_type=std_logic lab=io_oeb[16]} -C {devices/lab_pin.sym} 4130 710 0 0 {name=l27 sig_type=std_logic lab=io_oeb[11]} -C {devices/lab_pin.sym} 3630 710 0 0 {name=l28 sig_type=std_logic lab=io_oeb[12]} -C {devices/lab_pin.sym} 3630 830 0 0 {name=l29 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 3630 940 0 0 {name=l30 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 4130 820 0 0 {name=l31 sig_type=std_logic lab=vssd1} -C {devices/lab_pin.sym} 4130 940 0 0 {name=l32 sig_type=std_logic lab=vssd1} +N 190 -1210 250 -1210 { +lab=rA0} +N 600 -1210 660 -1210 { +lab=rB0} +N 600 -1230 660 -1230 { +lab=rB1} +N 600 -1250 660 -1250 { +lab=rB2} +N 600 -1270 660 -1270 { +lab=rB3} +N 600 -1290 660 -1290 { +lab=rB4} +N 600 -1310 660 -1310 { +lab=rB5} +N 600 -1330 660 -1330 { +lab=rB6} +N 600 -1350 660 -1350 { +lab=rB7} +N 600 -1370 660 -1370 { +lab=rB8} +N 600 -1390 660 -1390 { +lab=rB9} +N 600 -1410 660 -1410 { +lab=rB10} +N 600 -1430 660 -1430 { +lab=rB11} +N 600 -1450 660 -1450 { +lab=rB12} +N 600 -1470 660 -1470 { +lab=rB13} +N 600 -1490 660 -1490 { +lab=rB14} +N 600 -1510 660 -1510 { +lab=rB15} +N 190 -870 250 -870 { +lab=WL0} +N 190 -890 250 -890 { +lab=WL1} +N 190 -910 250 -910 { +lab=WL2} +N 190 -930 250 -930 { +lab=WL3} +N 190 -950 250 -950 { +lab=WL4} +N 190 -970 250 -970 { +lab=WL5} +N 190 -990 250 -990 { +lab=WL6} +N 190 -1010 250 -1010 { +lab=WL7} +N 190 -1030 250 -1030 { +lab=WL8} +N 190 -1050 250 -1050 { +lab=WL9} +N 190 -1070 250 -1070 { +lab=WL10} +N 190 -1090 250 -1090 { +lab=WL11} +N 190 -1110 250 -1110 { +lab=WL12} +N 190 -1130 250 -1130 { +lab=WL13} +N 190 -1150 250 -1150 { +lab=WL14} +N 190 -1170 250 -1170 { +lab=WL15} +N 190 -530 250 -530 { +lab=cA0} +N 190 -550 250 -550 { +lab=cA1} +N 190 -570 250 -570 { +lab=cA2} +N 190 -590 250 -590 { +lab=cA3} +N 190 -610 250 -610 { +lab=cA4} +N 190 -630 250 -630 { +lab=cA5} +N 190 -650 250 -650 { +lab=cA6} +N 190 -670 250 -670 { +lab=cA7} +N 190 -690 250 -690 { +lab=cA8} +N 190 -710 250 -710 { +lab=cA9} +N 190 -730 250 -730 { +lab=cA10} +N 190 -750 250 -750 { +lab=cA11} +N 190 -770 250 -770 { +lab=cA12} +N 190 -790 250 -790 { +lab=cA13} +N 190 -810 250 -810 { +lab=cA14} +N 190 -830 250 -830 { +lab=cA15} +N 190 -1790 250 -1790 { +lab=col0_sel} +N 190 -1810 250 -1810 { +lab=row0_sel} +N 190 -1750 250 -1750 { +lab=WR} +N 190 -1770 250 -1770 { +lab=Vgnr} +N 190 -1730 250 -1730 { +lab=Vgpr} +N 190 -1570 250 -1570 { +lab=Vcplus} +N 190 -1590 250 -1590 { +lab=Vcminus} +N 190 -1610 250 -1610 { +lab=Vref} +N 190 -1630 250 -1630 { +lab=Vref_comp} +N 190 -1650 250 -1650 { +lab=RISC_CLK} +N 550 -1750 610 -1750 { +lab=vssa1} +N 550 -1770 610 -1770 { +lab=vdda1} +N 550 -1790 610 -1790 { +lab=vccd1} +N 550 -1810 610 -1810 { +lab=latch_high0} +N 1970 -1800 2030 -1800 { +lab=latch_high2} +N 2700 -1750 2760 -1750 { +lab=vssd1} +N 2700 -1770 2760 -1770 { +lab=vdda1} +N 2700 -1790 2760 -1790 { +lab=vccd1} +N 2700 -1810 2760 -1810 { +lab=latch_high3} +N 3400 -1740 3460 -1740 { +lab=vssd1} +N 3400 -1760 3460 -1760 { +lab=vdda1} +N 3400 -1780 3460 -1780 { +lab=vccd1} +N 3400 -1800 3460 -1800 { +lab=latch_high4} +N 4110 -1740 4170 -1740 { +lab=vssd1} +N 4110 -1760 4170 -1760 { +lab=vdda1} +N 4110 -1780 4170 -1780 { +lab=vccd1} +N 4110 -1800 4170 -1800 { +lab=latch_high5} +N -400 -1700 -340 -1700 { +lab=col0_sel} +N -400 -1680 -340 -1680 { +lab=col1_sel} +N -400 -1660 -340 -1660 { +lab=col2_sel} +N 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{devices/lab_pin.sym} 190 -5940 0 0 {name=l1057 lab=row2_sel} +C {devices/lab_pin.sym} 190 -5920 0 0 {name=l1058 lab=col0_sel} +C {devices/lab_pin.sym} 910 -5820 2 1 {name=l1059 lab=Vrminus} +C {devices/lab_pin.sym} 910 -5840 0 0 {name=l1060 lab=SAMPLE} +C {devices/lab_pin.sym} 2760 -5900 2 0 {name=l1061 lab=vdda1} +C {devices/lab_pin.sym} 2760 -5920 2 0 {name=l1063 lab=vccd1} +C {devices/lab_pin.sym} 3460 -5890 2 0 {name=l1064 lab=vdda1} +C {devices/lab_pin.sym} 3460 -5910 2 0 {name=l1066 lab=vccd1} +C {devices/lab_pin.sym} 4170 -5890 2 0 {name=l1067 lab=vdda1} +C {devices/lab_pin.sym} 4170 -5910 2 0 {name=l1069 lab=vccd1} +C {devices/lab_wire.sym} 130 -5300 0 0 {name=l1070 sig_type=std_logic lab=WL15} +C {devices/lab_wire.sym} 130 -5280 0 0 {name=l1071 sig_type=std_logic lab=WL14} +C {devices/lab_wire.sym} 130 -5260 0 0 {name=l1072 sig_type=std_logic lab=WL13} +C {devices/lab_wire.sym} 130 -5240 0 0 {name=l1073 sig_type=std_logic lab=WL12} +C {devices/lab_wire.sym} 130 -5220 0 0 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lab=RISC_CLK} +C {devices/lab_pin.sym} 1330 -5900 2 0 {name=l1287 lab=vdda1} +C {devices/lab_pin.sym} 1330 -5920 2 0 {name=l1289 lab=vccd1} +C {devices/lab_pin.sym} 1610 -5810 2 1 {name=l1290 lab=Vrminus} +C {devices/lab_pin.sym} 1610 -5830 0 0 {name=l1291 lab=SAMPLE} +C {devices/lab_pin.sym} 1610 -5930 0 0 {name=l1292 lab=row2_sel} +C {devices/lab_pin.sym} 1610 -5910 0 0 {name=l1293 lab=col2_sel} +C {devices/lab_pin.sym} 1610 -5850 0 0 {name=l1294 lab=Vgpr} +C {devices/lab_pin.sym} 1610 -5890 0 0 {name=l1295 lab=Vgnr} +C {devices/lab_pin.sym} 1610 -5870 0 0 {name=l1296 lab=WR} +C {devices/lab_pin.sym} 1610 -5790 2 1 {name=l1297 lab=Vrplus} +C {devices/lab_pin.sym} 1610 -5730 0 0 {name=l1298 lab=Vref} +C {devices/lab_pin.sym} 1610 -5690 0 0 {name=l1299 lab=Vcplus} +C {devices/lab_pin.sym} 1610 -5710 0 0 {name=l1300 lab=Vcminus} +C {devices/lab_pin.sym} 1610 -5750 2 1 {name=l1301 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 1610 -5770 2 1 {name=l1302 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 2030 -5890 2 0 {name=l1303 lab=vdda1} +C {devices/lab_pin.sym} 2030 -5910 2 0 {name=l1305 lab=vccd1} +C {devices/bus_connect_nolab.sym} 1460 -5330 2 0 {name=r391} +C {devices/bus_connect_nolab.sym} 1460 -5350 2 0 {name=r392} +C {devices/bus_connect_nolab.sym} 1460 -5370 2 0 {name=r393} +C {devices/bus_connect_nolab.sym} 1460 -5390 2 0 {name=r394} +C {devices/bus_connect_nolab.sym} 1460 -5410 2 0 {name=r395} +C {devices/bus_connect_nolab.sym} 1460 -5430 2 0 {name=r396} +C {devices/bus_connect_nolab.sym} 1460 -5450 2 0 {name=r397} +C {devices/bus_connect_nolab.sym} 1460 -5470 2 0 {name=r398} +C {devices/bus_connect_nolab.sym} 1460 -5490 2 0 {name=r399} +C {devices/bus_connect_nolab.sym} 1460 -5510 2 0 {name=r400} +C {devices/bus_connect_nolab.sym} 1460 -5550 2 0 {name=r401} +C {devices/bus_connect_nolab.sym} 1460 -5530 2 0 {name=r402} +C {devices/bus_connect_nolab.sym} 1460 -5590 2 0 {name=r403} +C {devices/bus_connect_nolab.sym} 1460 -5570 2 0 {name=r404} +C {devices/bus_connect_nolab.sym} 1460 -5630 2 0 {name=r405} +C {devices/bus_connect_nolab.sym} 1460 -5610 2 0 {name=r406} +C {devices/lab_wire.sym} 1510 -5330 0 0 {name=l1306 sig_type=std_logic lab=rA0} +C {devices/lab_wire.sym} 1510 -5350 0 0 {name=l1307 sig_type=std_logic lab=rA1} +C {devices/lab_wire.sym} 1510 -5370 0 0 {name=l1308 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 1510 -5370 0 0 {name=l1309 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 1510 -5390 0 0 {name=l1310 sig_type=std_logic lab=rA3} +C {devices/lab_wire.sym} 1510 -5410 0 0 {name=l1311 sig_type=std_logic lab=rA4} +C {devices/lab_wire.sym} 1510 -5430 0 0 {name=l1312 sig_type=std_logic lab=rA5} +C {devices/lab_wire.sym} 1510 -5450 0 0 {name=l1313 sig_type=std_logic lab=rA6} +C {devices/lab_wire.sym} 1510 -5470 0 0 {name=l1314 sig_type=std_logic lab=rA7} +C {devices/lab_wire.sym} 1510 -5490 0 0 {name=l1315 sig_type=std_logic lab=rA8} +C {devices/lab_wire.sym} 1510 -5510 0 0 {name=l1316 sig_type=std_logic lab=rA9} +C {devices/lab_wire.sym} 1510 -5550 0 0 {name=l1317 sig_type=std_logic lab=rA11} +C {devices/lab_wire.sym} 1510 -5530 0 0 {name=l1318 sig_type=std_logic lab=rA10} +C {devices/lab_wire.sym} 1510 -5570 0 0 {name=l1319 sig_type=std_logic lab=rA12} +C {devices/lab_wire.sym} 1510 -5590 0 0 {name=l1320 sig_type=std_logic lab=rA13} +C {devices/lab_wire.sym} 1510 -5610 0 0 {name=l1321 sig_type=std_logic lab=rA14} +C {devices/lab_wire.sym} 1510 -5630 0 0 {name=l1322 sig_type=std_logic lab=rA15} +C {devices/lab_pin.sym} 1450 -5280 3 0 {name=l1323 sig_type=std_logic lab=rA[0..15]} +C {devices/bus_connect_nolab.sym} 2080 -5330 2 1 {name=r407} +C {devices/bus_connect_nolab.sym} 2080 -5350 2 1 {name=r408} +C {devices/bus_connect_nolab.sym} 2080 -5370 2 1 {name=r409} +C {devices/bus_connect_nolab.sym} 2080 -5390 2 1 {name=r410} +C {devices/bus_connect_nolab.sym} 2080 -5410 2 1 {name=r411} +C {devices/bus_connect_nolab.sym} 2080 -5430 2 1 {name=r412} +C {devices/bus_connect_nolab.sym} 2080 -5450 2 1 {name=r413} +C {devices/bus_connect_nolab.sym} 2080 -5470 2 1 {name=r414} +C {devices/bus_connect_nolab.sym} 2080 -5490 2 1 {name=r415} +C {devices/bus_connect_nolab.sym} 2080 -5510 2 1 {name=r416} +C {devices/bus_connect_nolab.sym} 2080 -5530 2 1 {name=r417} +C {devices/bus_connect_nolab.sym} 2080 -5550 2 1 {name=r418} +C {devices/bus_connect_nolab.sym} 2080 -5570 2 1 {name=r419} +C {devices/bus_connect_nolab.sym} 2080 -5590 2 1 {name=r420} +C {devices/bus_connect_nolab.sym} 2080 -5610 2 1 {name=r421} +C {devices/bus_connect_nolab.sym} 2080 -5630 2 1 {name=r422} +C {devices/lab_pin.sym} 2090 -5280 3 0 {name=l1324 sig_type=std_logic lab=rB[0..15]} +C {devices/lab_wire.sym} 2030 -5630 0 1 {name=l1325 sig_type=std_logic lab=rB15} +C {devices/lab_wire.sym} 2030 -5610 0 1 {name=l1326 sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 2030 -5590 0 1 {name=l1327 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 2030 -5570 0 1 {name=l1328 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 2030 -5550 0 1 {name=l1329 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 2030 -5530 0 1 {name=l1330 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 2030 -5510 0 1 {name=l1331 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 2030 -5490 0 1 {name=l1332 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 2030 -5470 0 1 {name=l1333 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 2030 -5450 0 1 {name=l1334 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 2030 -5430 0 1 {name=l1335 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 2030 -5410 0 1 {name=l1336 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 2030 -5390 0 1 {name=l1337 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 2030 -5370 0 1 {name=l1338 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 2030 -5350 0 1 {name=l1339 sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 2030 -5330 0 1 {name=l1340 sig_type=std_logic lab=rB0} +C {devices/bus_connect_nolab.sym} 910 -4660 2 0 {name=r423} +C {devices/bus_connect_nolab.sym} 910 -4680 2 0 {name=r424} +C {devices/bus_connect_nolab.sym} 910 -4700 2 0 {name=r425} +C {devices/bus_connect_nolab.sym} 910 -4720 2 0 {name=r426} +C {devices/bus_connect_nolab.sym} 910 -4740 2 0 {name=r427} +C {devices/bus_connect_nolab.sym} 910 -4760 2 0 {name=r428} +C {devices/bus_connect_nolab.sym} 910 -4780 2 0 {name=r429} +C {devices/bus_connect_nolab.sym} 910 -4800 2 0 {name=r430} +C {devices/bus_connect_nolab.sym} 910 -4820 2 0 {name=r431} +C {devices/bus_connect_nolab.sym} 910 -4840 2 0 {name=r432} +C {devices/bus_connect_nolab.sym} 910 -4860 2 0 {name=r433} +C {devices/bus_connect_nolab.sym} 910 -4880 2 0 {name=r434} +C {devices/bus_connect_nolab.sym} 910 -4900 2 0 {name=r435} +C {devices/bus_connect_nolab.sym} 910 -4920 2 0 {name=r436} +C {devices/bus_connect_nolab.sym} 910 -4940 2 0 {name=r437} +C {devices/bus_connect_nolab.sym} 910 -4960 2 0 {name=r438} +C {devices/lab_pin.sym} 900 -4620 3 0 {name=l1341 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 1330 -4660 2 1 {name=r439} +C {devices/bus_connect_nolab.sym} 1330 -4680 2 1 {name=r440} +C {devices/bus_connect_nolab.sym} 1330 -4700 2 1 {name=r441} +C {devices/bus_connect_nolab.sym} 1330 -4720 2 1 {name=r442} +C {devices/bus_connect_nolab.sym} 1330 -4740 2 1 {name=r443} +C {devices/bus_connect_nolab.sym} 1330 -4760 2 1 {name=r444} +C {devices/bus_connect_nolab.sym} 1330 -4780 2 1 {name=r445} +C {devices/bus_connect_nolab.sym} 1330 -4800 2 1 {name=r446} +C {devices/bus_connect_nolab.sym} 1330 -4820 2 1 {name=r447} +C {devices/bus_connect_nolab.sym} 1330 -4840 2 1 {name=r448} +C {devices/bus_connect_nolab.sym} 1330 -4860 2 1 {name=r449} +C {devices/bus_connect_nolab.sym} 1330 -4880 2 1 {name=r450} +C {devices/bus_connect_nolab.sym} 1330 -4900 2 1 {name=r451} +C {devices/bus_connect_nolab.sym} 1330 -4920 2 1 {name=r452} +C {devices/bus_connect_nolab.sym} 1330 -4940 2 1 {name=r453} +C {devices/bus_connect_nolab.sym} 1330 -4960 2 1 {name=r454} +C {devices/lab_pin.sym} 1340 -4620 1 1 {name=l1342 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 950 -4680 0 0 {name=l1343 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 950 -4700 0 0 {name=l1344 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 950 -4720 0 0 {name=l1345 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 950 -4740 0 0 {name=l1346 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 950 -4760 0 0 {name=l1347 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 950 -4780 0 0 {name=l1348 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 950 -4800 0 0 {name=l1349 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 950 -4820 0 0 {name=l1350 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 950 -4840 0 0 {name=l1351 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 950 -4880 0 0 {name=l1352 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 950 -4860 0 0 {name=l1353 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 950 -4900 0 0 {name=l1354 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 950 -4920 0 0 {name=l1355 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 950 -4940 0 0 {name=l1356 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 950 -4960 0 0 {name=l1357 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 950 -4660 0 0 {name=l1358 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1290 -4680 0 1 {name=l1359 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1290 -4700 0 1 {name=l1360 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1290 -4720 0 1 {name=l1361 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1290 -4740 0 1 {name=l1362 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1290 -4760 0 1 {name=l1363 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1290 -4780 0 1 {name=l1364 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1290 -4800 0 1 {name=l1365 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1290 -4820 0 1 {name=l1366 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1290 -4840 0 1 {name=l1367 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1290 -4880 0 1 {name=l1368 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1290 -4860 0 1 {name=l1369 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1290 -4900 0 1 {name=l1370 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1290 -4920 0 1 {name=l1371 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1290 -4940 0 1 {name=l1372 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1290 -4960 0 1 {name=l1373 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1290 -4660 0 1 {name=l1374 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 1610 -4650 2 0 {name=r455} +C {devices/bus_connect_nolab.sym} 1610 -4670 2 0 {name=r456} +C {devices/bus_connect_nolab.sym} 1610 -4690 2 0 {name=r457} +C {devices/bus_connect_nolab.sym} 1610 -4710 2 0 {name=r458} +C {devices/bus_connect_nolab.sym} 1610 -4730 2 0 {name=r459} +C {devices/bus_connect_nolab.sym} 1610 -4750 2 0 {name=r460} +C {devices/bus_connect_nolab.sym} 1610 -4770 2 0 {name=r461} +C {devices/bus_connect_nolab.sym} 1610 -4790 2 0 {name=r462} +C {devices/bus_connect_nolab.sym} 1610 -4810 2 0 {name=r463} +C {devices/bus_connect_nolab.sym} 1610 -4830 2 0 {name=r464} +C {devices/bus_connect_nolab.sym} 1610 -4850 2 0 {name=r465} +C {devices/bus_connect_nolab.sym} 1610 -4870 2 0 {name=r466} +C {devices/bus_connect_nolab.sym} 1610 -4890 2 0 {name=r467} +C {devices/bus_connect_nolab.sym} 1610 -4910 2 0 {name=r468} +C {devices/bus_connect_nolab.sym} 1610 -4930 2 0 {name=r469} +C {devices/bus_connect_nolab.sym} 1610 -4950 2 0 {name=r470} +C {devices/lab_pin.sym} 1600 -4610 3 0 {name=l1375 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 2030 -4650 2 1 {name=r471} +C {devices/bus_connect_nolab.sym} 2030 -4670 2 1 {name=r472} +C {devices/bus_connect_nolab.sym} 2030 -4690 2 1 {name=r473} +C {devices/bus_connect_nolab.sym} 2030 -4710 2 1 {name=r474} +C {devices/bus_connect_nolab.sym} 2030 -4730 2 1 {name=r475} +C {devices/bus_connect_nolab.sym} 2030 -4750 2 1 {name=r476} +C {devices/bus_connect_nolab.sym} 2030 -4770 2 1 {name=r477} +C {devices/bus_connect_nolab.sym} 2030 -4790 2 1 {name=r478} +C {devices/bus_connect_nolab.sym} 2030 -4810 2 1 {name=r479} +C {devices/bus_connect_nolab.sym} 2030 -4830 2 1 {name=r480} +C {devices/bus_connect_nolab.sym} 2030 -4850 2 1 {name=r481} +C {devices/bus_connect_nolab.sym} 2030 -4870 2 1 {name=r482} +C {devices/bus_connect_nolab.sym} 2030 -4890 2 1 {name=r483} +C {devices/bus_connect_nolab.sym} 2030 -4910 2 1 {name=r484} +C {devices/bus_connect_nolab.sym} 2030 -4930 2 1 {name=r485} +C {devices/bus_connect_nolab.sym} 2030 -4950 2 1 {name=r486} +C {devices/lab_pin.sym} 2040 -4610 1 1 {name=l1376 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 1650 -4670 0 0 {name=l1377 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 1650 -4690 0 0 {name=l1378 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 1650 -4710 0 0 {name=l1379 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 1650 -4730 0 0 {name=l1380 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 1650 -4750 0 0 {name=l1381 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 1650 -4770 0 0 {name=l1382 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 1650 -4790 0 0 {name=l1383 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 1650 -4810 0 0 {name=l1384 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 1650 -4830 0 0 {name=l1385 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 1650 -4870 0 0 {name=l1386 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 1650 -4850 0 0 {name=l1387 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 1650 -4890 0 0 {name=l1388 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 1650 -4910 0 0 {name=l1389 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 1650 -4930 0 0 {name=l1390 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 1650 -4950 0 0 {name=l1391 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 1650 -4650 0 0 {name=l1392 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1990 -4670 0 1 {name=l1393 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1990 -4690 0 1 {name=l1394 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1990 -4710 0 1 {name=l1395 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1990 -4730 0 1 {name=l1396 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1990 -4750 0 1 {name=l1397 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1990 -4770 0 1 {name=l1398 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1990 -4790 0 1 {name=l1399 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1990 -4810 0 1 {name=l1400 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1990 -4830 0 1 {name=l1401 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1990 -4870 0 1 {name=l1402 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1990 -4850 0 1 {name=l1403 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1990 -4890 0 1 {name=l1404 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1990 -4910 0 1 {name=l1405 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1990 -4930 0 1 {name=l1406 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1990 -4950 0 1 {name=l1407 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1990 -4650 0 1 {name=l1408 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 2190 -5340 2 0 {name=r487} +C {devices/bus_connect_nolab.sym} 2190 -5360 2 0 {name=r488} +C {devices/bus_connect_nolab.sym} 2190 -5380 2 0 {name=r489} +C {devices/bus_connect_nolab.sym} 2190 -5400 2 0 {name=r490} +C {devices/bus_connect_nolab.sym} 2190 -5420 2 0 {name=r491} +C {devices/bus_connect_nolab.sym} 2190 -5440 2 0 {name=r492} +C {devices/bus_connect_nolab.sym} 2190 -5460 2 0 {name=r493} +C {devices/bus_connect_nolab.sym} 2190 -5480 2 0 {name=r494} +C {devices/bus_connect_nolab.sym} 2190 -5500 2 0 {name=r495} +C {devices/bus_connect_nolab.sym} 2190 -5520 2 0 {name=r496} +C {devices/bus_connect_nolab.sym} 2190 -5560 2 0 {name=r497} +C {devices/bus_connect_nolab.sym} 2190 -5540 2 0 {name=r498} +C {devices/bus_connect_nolab.sym} 2190 -5600 2 0 {name=r499} +C {devices/bus_connect_nolab.sym} 2190 -5580 2 0 {name=r500} +C {devices/bus_connect_nolab.sym} 2190 -5640 2 0 {name=r501} +C {devices/bus_connect_nolab.sym} 2190 -5620 2 0 {name=r502} +C {devices/lab_wire.sym} 2240 -5340 0 0 {name=l1409 sig_type=std_logic lab=rA0} +C {devices/lab_wire.sym} 2240 -5360 0 0 {name=l1410 sig_type=std_logic lab=rA1} +C {devices/lab_wire.sym} 2240 -5380 0 0 {name=l1411 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 2240 -5380 0 0 {name=l1412 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 2240 -5400 0 0 {name=l1413 sig_type=std_logic lab=rA3} +C {devices/lab_wire.sym} 2240 -5420 0 0 {name=l1414 sig_type=std_logic lab=rA4} +C {devices/lab_wire.sym} 2240 -5440 0 0 {name=l1415 sig_type=std_logic lab=rA5} +C {devices/lab_wire.sym} 2240 -5460 0 0 {name=l1416 sig_type=std_logic lab=rA6} +C {devices/lab_wire.sym} 2240 -5480 0 0 {name=l1417 sig_type=std_logic lab=rA7} +C {devices/lab_wire.sym} 2240 -5500 0 0 {name=l1418 sig_type=std_logic lab=rA8} +C {devices/lab_wire.sym} 2240 -5520 0 0 {name=l1419 sig_type=std_logic lab=rA9} +C {devices/lab_wire.sym} 2240 -5560 0 0 {name=l1420 sig_type=std_logic lab=rA11} +C {devices/lab_wire.sym} 2240 -5540 0 0 {name=l1421 sig_type=std_logic lab=rA10} +C {devices/lab_wire.sym} 2240 -5580 0 0 {name=l1422 sig_type=std_logic lab=rA12} +C {devices/lab_wire.sym} 2240 -5600 0 0 {name=l1423 sig_type=std_logic lab=rA13} +C {devices/lab_wire.sym} 2240 -5620 0 0 {name=l1424 sig_type=std_logic lab=rA14} +C {devices/lab_wire.sym} 2240 -5640 0 0 {name=l1425 sig_type=std_logic lab=rA15} +C {devices/lab_pin.sym} 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{devices/bus_connect_nolab.sym} 2810 -5640 2 1 {name=r518} +C {devices/lab_pin.sym} 2820 -5290 3 0 {name=l1427 sig_type=std_logic lab=rB[0..15]} +C {devices/lab_wire.sym} 2760 -5640 0 1 {name=l1428 sig_type=std_logic lab=rB15} +C {devices/lab_wire.sym} 2760 -5620 0 1 {name=l1429 sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 2760 -5600 0 1 {name=l1430 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 2760 -5580 0 1 {name=l1431 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 2760 -5560 0 1 {name=l1432 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 2760 -5540 0 1 {name=l1433 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 2760 -5520 0 1 {name=l1434 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 2760 -5500 0 1 {name=l1435 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 2760 -5480 0 1 {name=l1436 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 2760 -5460 0 1 {name=l1437 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 2760 -5440 0 1 {name=l1438 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 2760 -5420 0 1 {name=l1439 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 2760 -5400 0 1 {name=l1440 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 2760 -5380 0 1 {name=l1441 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 2760 -5360 0 1 {name=l1442 sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 2760 -5340 0 1 {name=l1443 sig_type=std_logic lab=rB0} +C {devices/bus_connect_nolab.sym} 2340 -4660 2 0 {name=r519} +C {devices/bus_connect_nolab.sym} 2340 -4680 2 0 {name=r520} +C {devices/bus_connect_nolab.sym} 2340 -4700 2 0 {name=r521} +C {devices/bus_connect_nolab.sym} 2340 -4720 2 0 {name=r522} +C {devices/bus_connect_nolab.sym} 2340 -4740 2 0 {name=r523} +C {devices/bus_connect_nolab.sym} 2340 -4760 2 0 {name=r524} +C {devices/bus_connect_nolab.sym} 2340 -4780 2 0 {name=r525} +C {devices/bus_connect_nolab.sym} 2340 -4800 2 0 {name=r526} +C {devices/bus_connect_nolab.sym} 2340 -4820 2 0 {name=r527} +C {devices/bus_connect_nolab.sym} 2340 -4840 2 0 {name=r528} +C {devices/bus_connect_nolab.sym} 2340 -4860 2 0 {name=r529} +C {devices/bus_connect_nolab.sym} 2340 -4880 2 0 {name=r530} +C {devices/bus_connect_nolab.sym} 2340 -4900 2 0 {name=r531} +C {devices/bus_connect_nolab.sym} 2340 -4920 2 0 {name=r532} +C {devices/bus_connect_nolab.sym} 2340 -4940 2 0 {name=r533} +C {devices/bus_connect_nolab.sym} 2340 -4960 2 0 {name=r534} +C {devices/lab_pin.sym} 2330 -4620 3 0 {name=l1444 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 2760 -4660 2 1 {name=r535} +C {devices/bus_connect_nolab.sym} 2760 -4680 2 1 {name=r536} +C {devices/bus_connect_nolab.sym} 2760 -4700 2 1 {name=r537} +C {devices/bus_connect_nolab.sym} 2760 -4720 2 1 {name=r538} +C {devices/bus_connect_nolab.sym} 2760 -4740 2 1 {name=r539} +C {devices/bus_connect_nolab.sym} 2760 -4760 2 1 {name=r540} +C {devices/bus_connect_nolab.sym} 2760 -4780 2 1 {name=r541} +C {devices/bus_connect_nolab.sym} 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sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 2380 -4780 0 0 {name=l1451 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 2380 -4800 0 0 {name=l1452 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 2380 -4820 0 0 {name=l1453 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 2380 -4840 0 0 {name=l1454 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 2380 -4880 0 0 {name=l1455 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 2380 -4860 0 0 {name=l1456 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 2380 -4900 0 0 {name=l1457 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 2380 -4920 0 0 {name=l1458 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 2380 -4940 0 0 {name=l1459 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 2380 -4960 0 0 {name=l1460 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 2380 -4660 0 0 {name=l1461 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 2720 -4680 0 1 {name=l1462 sig_type=std_logic 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{name=l1499 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 3460 -5570 0 1 {name=l1500 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 3460 -5550 0 1 {name=l1501 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 3460 -5530 0 1 {name=l1502 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 3460 -5510 0 1 {name=l1503 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 3460 -5490 0 1 {name=l1504 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 3460 -5470 0 1 {name=l1505 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 3460 -5450 0 1 {name=l1506 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 3460 -5430 0 1 {name=l1507 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 3460 -5410 0 1 {name=l1508 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 3460 -5390 0 1 {name=l1509 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 3460 -5370 0 1 {name=l1510 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 3460 -5350 0 1 {name=l1511 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{devices/lab_pin.sym} 2340 -5880 0 0 {name=l1622 lab=WR} +C {devices/lab_pin.sym} 2340 -5800 2 1 {name=l1623 lab=Vrplus} +C {devices/lab_pin.sym} 2340 -5740 0 0 {name=l1624 lab=Vref} +C {devices/lab_pin.sym} 2340 -5700 0 0 {name=l1625 lab=Vcplus} +C {devices/lab_pin.sym} 2340 -5720 0 0 {name=l1626 lab=Vcminus} +C {devices/lab_pin.sym} 2340 -5760 2 1 {name=l1627 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 2340 -5780 2 1 {name=l1628 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 3040 -5810 2 1 {name=l1629 lab=Vrminus} +C {devices/lab_pin.sym} 3040 -5830 0 0 {name=l1630 lab=SAMPLE} +C {devices/lab_pin.sym} 3040 -5930 0 0 {name=l1631 lab=row2_sel} +C {devices/lab_pin.sym} 3040 -5910 0 0 {name=l1632 lab=col4_sel} +C {devices/lab_pin.sym} 3040 -5850 0 0 {name=l1633 lab=Vgpr} +C {devices/lab_pin.sym} 3040 -5890 0 0 {name=l1634 lab=Vgnr} +C {devices/lab_pin.sym} 3040 -5870 0 0 {name=l1635 lab=WR} +C {devices/lab_pin.sym} 3040 -5790 2 1 {name=l1636 lab=Vrplus} +C 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sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 1510 -7410 0 0 {name=l1948 sig_type=std_logic lab=rA3} +C {devices/lab_wire.sym} 1510 -7430 0 0 {name=l1949 sig_type=std_logic lab=rA4} +C {devices/lab_wire.sym} 1510 -7450 0 0 {name=l1950 sig_type=std_logic lab=rA5} +C {devices/lab_wire.sym} 1510 -7470 0 0 {name=l1951 sig_type=std_logic lab=rA6} +C {devices/lab_wire.sym} 1510 -7490 0 0 {name=l1952 sig_type=std_logic lab=rA7} +C {devices/lab_wire.sym} 1510 -7510 0 0 {name=l1953 sig_type=std_logic lab=rA8} +C {devices/lab_wire.sym} 1510 -7530 0 0 {name=l1954 sig_type=std_logic lab=rA9} +C {devices/lab_wire.sym} 1510 -7570 0 0 {name=l1955 sig_type=std_logic lab=rA11} +C {devices/lab_wire.sym} 1510 -7550 0 0 {name=l1956 sig_type=std_logic lab=rA10} +C {devices/lab_wire.sym} 1510 -7590 0 0 {name=l1957 sig_type=std_logic lab=rA12} +C {devices/lab_wire.sym} 1510 -7610 0 0 {name=l1958 sig_type=std_logic lab=rA13} +C {devices/lab_wire.sym} 1510 -7630 0 0 {name=l1959 sig_type=std_logic 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{name=r1677} +C {devices/bus_connect_nolab.sym} 910 -6820 2 0 {name=r1678} +C {devices/bus_connect_nolab.sym} 910 -6840 2 0 {name=r1679} +C {devices/bus_connect_nolab.sym} 910 -6860 2 0 {name=r1680} +C {devices/bus_connect_nolab.sym} 910 -6880 2 0 {name=r1681} +C {devices/bus_connect_nolab.sym} 910 -6900 2 0 {name=r1682} +C {devices/bus_connect_nolab.sym} 910 -6920 2 0 {name=r1683} +C {devices/bus_connect_nolab.sym} 910 -6940 2 0 {name=r1684} +C {devices/bus_connect_nolab.sym} 910 -6960 2 0 {name=r1685} +C {devices/bus_connect_nolab.sym} 910 -6980 2 0 {name=r1686} +C {devices/lab_pin.sym} 900 -6640 3 0 {name=l1979 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 1330 -6680 2 1 {name=r1687} +C {devices/bus_connect_nolab.sym} 1330 -6700 2 1 {name=r1688} +C {devices/bus_connect_nolab.sym} 1330 -6720 2 1 {name=r1689} +C {devices/bus_connect_nolab.sym} 1330 -6740 2 1 {name=r1690} +C {devices/bus_connect_nolab.sym} 1330 -6760 2 1 {name=r1691} +C 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{devices/lab_wire.sym} 950 -6680 0 0 {name=l1996 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1290 -6700 0 1 {name=l1997 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1290 -6720 0 1 {name=l1998 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1290 -6740 0 1 {name=l1999 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1290 -6760 0 1 {name=l2000 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1290 -6780 0 1 {name=l2001 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1290 -6800 0 1 {name=l2002 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1290 -6820 0 1 {name=l2003 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1290 -6840 0 1 {name=l2004 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1290 -6860 0 1 {name=l2005 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1290 -6900 0 1 {name=l2006 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1290 -6880 0 1 {name=l2007 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1290 -6920 0 1 {name=l2008 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1290 -6940 0 1 {name=l2009 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1290 -6960 0 1 {name=l2010 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1290 -6980 0 1 {name=l2011 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1290 -6680 0 1 {name=l2012 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 1610 -6670 2 0 {name=r1703} +C {devices/bus_connect_nolab.sym} 1610 -6690 2 0 {name=r1704} +C {devices/bus_connect_nolab.sym} 1610 -6710 2 0 {name=r1705} +C {devices/bus_connect_nolab.sym} 1610 -6730 2 0 {name=r1706} +C {devices/bus_connect_nolab.sym} 1610 -6750 2 0 {name=r1707} +C {devices/bus_connect_nolab.sym} 1610 -6770 2 0 {name=r1708} +C {devices/bus_connect_nolab.sym} 1610 -6790 2 0 {name=r1709} +C {devices/bus_connect_nolab.sym} 1610 -6810 2 0 {name=r1710} +C {devices/bus_connect_nolab.sym} 1610 -6830 2 0 {name=r1711} +C {devices/bus_connect_nolab.sym} 1610 -6850 2 0 {name=r1712} +C {devices/bus_connect_nolab.sym} 1610 -6870 2 0 {name=r1713} +C {devices/bus_connect_nolab.sym} 1610 -6890 2 0 {name=r1714} +C {devices/bus_connect_nolab.sym} 1610 -6910 2 0 {name=r1715} +C {devices/bus_connect_nolab.sym} 1610 -6930 2 0 {name=r1716} +C {devices/bus_connect_nolab.sym} 1610 -6950 2 0 {name=r1717} +C {devices/bus_connect_nolab.sym} 1610 -6970 2 0 {name=r1718} +C {devices/lab_pin.sym} 1600 -6630 3 0 {name=l2013 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 2030 -6670 2 1 {name=r1719} +C {devices/bus_connect_nolab.sym} 2030 -6690 2 1 {name=r1720} +C {devices/bus_connect_nolab.sym} 2030 -6710 2 1 {name=r1721} +C {devices/bus_connect_nolab.sym} 2030 -6730 2 1 {name=r1722} +C {devices/bus_connect_nolab.sym} 2030 -6750 2 1 {name=r1723} +C {devices/bus_connect_nolab.sym} 2030 -6770 2 1 {name=r1724} +C {devices/bus_connect_nolab.sym} 2030 -6790 2 1 {name=r1725} +C {devices/bus_connect_nolab.sym} 2030 -6810 2 1 {name=r1726} +C {devices/bus_connect_nolab.sym} 2030 -6830 2 1 {name=r1727} +C {devices/bus_connect_nolab.sym} 2030 -6850 2 1 {name=r1728} +C {devices/bus_connect_nolab.sym} 2030 -6870 2 1 {name=r1729} +C {devices/bus_connect_nolab.sym} 2030 -6890 2 1 {name=r1730} +C {devices/bus_connect_nolab.sym} 2030 -6910 2 1 {name=r1731} +C {devices/bus_connect_nolab.sym} 2030 -6930 2 1 {name=r1732} +C {devices/bus_connect_nolab.sym} 2030 -6950 2 1 {name=r1733} +C {devices/bus_connect_nolab.sym} 2030 -6970 2 1 {name=r1734} +C {devices/lab_pin.sym} 2040 -6630 1 1 {name=l2014 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 1650 -6690 0 0 {name=l2015 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 1650 -6710 0 0 {name=l2016 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 1650 -6730 0 0 {name=l2017 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 1650 -6750 0 0 {name=l2018 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 1650 -6770 0 0 {name=l2019 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 1650 -6790 0 0 {name=l2020 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 1650 -6810 0 0 {name=l2021 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 1650 -6830 0 0 {name=l2022 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 1650 -6850 0 0 {name=l2023 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 1650 -6890 0 0 {name=l2024 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 1650 -6870 0 0 {name=l2025 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 1650 -6910 0 0 {name=l2026 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 1650 -6930 0 0 {name=l2027 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 1650 -6950 0 0 {name=l2028 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 1650 -6970 0 0 {name=l2029 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 1650 -6670 0 0 {name=l2030 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1990 -6690 0 1 {name=l2031 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1990 -6710 0 1 {name=l2032 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1990 -6730 0 1 {name=l2033 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1990 -6750 0 1 {name=l2034 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1990 -6770 0 1 {name=l2035 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1990 -6790 0 1 {name=l2036 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1990 -6810 0 1 {name=l2037 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1990 -6830 0 1 {name=l2038 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1990 -6850 0 1 {name=l2039 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1990 -6890 0 1 {name=l2040 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1990 -6870 0 1 {name=l2041 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1990 -6910 0 1 {name=l2042 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1990 -6930 0 1 {name=l2043 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1990 -6950 0 1 {name=l2044 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1990 -6970 0 1 {name=l2045 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1990 -6670 0 1 {name=l2046 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 2190 -7360 2 0 {name=r1735} +C {devices/bus_connect_nolab.sym} 2190 -7380 2 0 {name=r1736} +C {devices/bus_connect_nolab.sym} 2190 -7400 2 0 {name=r1737} +C {devices/bus_connect_nolab.sym} 2190 -7420 2 0 {name=r1738} +C {devices/bus_connect_nolab.sym} 2190 -7440 2 0 {name=r1739} +C {devices/bus_connect_nolab.sym} 2190 -7460 2 0 {name=r1740} +C {devices/bus_connect_nolab.sym} 2190 -7480 2 0 {name=r1741} +C {devices/bus_connect_nolab.sym} 2190 -7500 2 0 {name=r1742} +C {devices/bus_connect_nolab.sym} 2190 -7520 2 0 {name=r1743} +C {devices/bus_connect_nolab.sym} 2190 -7540 2 0 {name=r1744} +C {devices/bus_connect_nolab.sym} 2190 -7580 2 0 {name=r1745} +C {devices/bus_connect_nolab.sym} 2190 -7560 2 0 {name=r1746} +C {devices/bus_connect_nolab.sym} 2190 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{name=l2537 lab=Vrplus} +C {devices/lab_pin.sym} 910 -9750 0 0 {name=l2538 lab=Vref} +C {devices/lab_pin.sym} 910 -9710 0 0 {name=l2539 lab=Vcplus} +C {devices/lab_pin.sym} 910 -9730 0 0 {name=l2540 lab=Vcminus} +C {devices/lab_pin.sym} 910 -9770 2 1 {name=l2541 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 910 -9790 2 1 {name=l2542 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 1330 -9910 2 0 {name=l2543 lab=vdda1} +C {devices/lab_pin.sym} 1330 -9930 2 0 {name=l2545 lab=vccd1} +C {devices/lab_pin.sym} 1610 -9820 2 1 {name=l2546 lab=Vrminus} +C {devices/lab_pin.sym} 1610 -9840 0 0 {name=l2547 lab=SAMPLE} +C {devices/lab_pin.sym} 1610 -9940 0 0 {name=l2548 lab=row4_sel} +C {devices/lab_pin.sym} 1610 -9920 0 0 {name=l2549 lab=col2_sel} +C {devices/lab_pin.sym} 1610 -9860 0 0 {name=l2550 lab=Vgpr} +C {devices/lab_pin.sym} 1610 -9900 0 0 {name=l2551 lab=Vgnr} +C {devices/lab_pin.sym} 1610 -9880 0 0 {name=l2552 lab=WR} +C {devices/lab_pin.sym} 1610 -9800 2 1 {name=l2553 lab=Vrplus} +C {devices/lab_pin.sym} 1610 -9740 0 0 {name=l2554 lab=Vref} +C {devices/lab_pin.sym} 1610 -9700 0 0 {name=l2555 lab=Vcplus} +C {devices/lab_pin.sym} 1610 -9720 0 0 {name=l2556 lab=Vcminus} +C {devices/lab_pin.sym} 1610 -9760 2 1 {name=l2557 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 1610 -9780 2 1 {name=l2558 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 2030 -9900 2 0 {name=l2559 lab=vdda1} +C {devices/lab_pin.sym} 2030 -9920 2 0 {name=l2561 lab=vccd1} +C {devices/bus_connect_nolab.sym} 1460 -9340 2 0 {name=r2119} +C {devices/bus_connect_nolab.sym} 1460 -9360 2 0 {name=r2120} +C {devices/bus_connect_nolab.sym} 1460 -9380 2 0 {name=r2121} +C {devices/bus_connect_nolab.sym} 1460 -9400 2 0 {name=r2122} +C {devices/bus_connect_nolab.sym} 1460 -9420 2 0 {name=r2123} +C {devices/bus_connect_nolab.sym} 1460 -9440 2 0 {name=r2124} +C {devices/bus_connect_nolab.sym} 1460 -9460 2 0 {name=r2125} +C {devices/bus_connect_nolab.sym} 1460 -9480 2 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lab=rA4} +C {devices/lab_wire.sym} 1510 -9440 0 0 {name=l2568 sig_type=std_logic lab=rA5} +C {devices/lab_wire.sym} 1510 -9460 0 0 {name=l2569 sig_type=std_logic lab=rA6} +C {devices/lab_wire.sym} 1510 -9480 0 0 {name=l2570 sig_type=std_logic lab=rA7} +C {devices/lab_wire.sym} 1510 -9500 0 0 {name=l2571 sig_type=std_logic lab=rA8} +C {devices/lab_wire.sym} 1510 -9520 0 0 {name=l2572 sig_type=std_logic lab=rA9} +C {devices/lab_wire.sym} 1510 -9560 0 0 {name=l2573 sig_type=std_logic lab=rA11} +C {devices/lab_wire.sym} 1510 -9540 0 0 {name=l2574 sig_type=std_logic lab=rA10} +C {devices/lab_wire.sym} 1510 -9580 0 0 {name=l2575 sig_type=std_logic lab=rA12} +C {devices/lab_wire.sym} 1510 -9600 0 0 {name=l2576 sig_type=std_logic lab=rA13} +C {devices/lab_wire.sym} 1510 -9620 0 0 {name=l2577 sig_type=std_logic lab=rA14} +C {devices/lab_wire.sym} 1510 -9640 0 0 {name=l2578 sig_type=std_logic lab=rA15} +C {devices/lab_pin.sym} 1450 -9290 3 0 {name=l2579 sig_type=std_logic lab=rA[0..15]} +C {devices/bus_connect_nolab.sym} 2080 -9340 2 1 {name=r2135} +C {devices/bus_connect_nolab.sym} 2080 -9360 2 1 {name=r2136} +C {devices/bus_connect_nolab.sym} 2080 -9380 2 1 {name=r2137} +C {devices/bus_connect_nolab.sym} 2080 -9400 2 1 {name=r2138} +C {devices/bus_connect_nolab.sym} 2080 -9420 2 1 {name=r2139} +C {devices/bus_connect_nolab.sym} 2080 -9440 2 1 {name=r2140} +C {devices/bus_connect_nolab.sym} 2080 -9460 2 1 {name=r2141} +C {devices/bus_connect_nolab.sym} 2080 -9480 2 1 {name=r2142} +C {devices/bus_connect_nolab.sym} 2080 -9500 2 1 {name=r2143} +C {devices/bus_connect_nolab.sym} 2080 -9520 2 1 {name=r2144} +C {devices/bus_connect_nolab.sym} 2080 -9540 2 1 {name=r2145} +C {devices/bus_connect_nolab.sym} 2080 -9560 2 1 {name=r2146} +C {devices/bus_connect_nolab.sym} 2080 -9580 2 1 {name=r2147} +C {devices/bus_connect_nolab.sym} 2080 -9600 2 1 {name=r2148} +C {devices/bus_connect_nolab.sym} 2080 -9620 2 1 {name=r2149} +C {devices/bus_connect_nolab.sym} 2080 -9640 2 1 {name=r2150} +C {devices/lab_pin.sym} 2090 -9290 3 0 {name=l2580 sig_type=std_logic lab=rB[0..15]} +C {devices/lab_wire.sym} 2030 -9640 0 1 {name=l2581 sig_type=std_logic lab=rB15} +C {devices/lab_wire.sym} 2030 -9620 0 1 {name=l2582 sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 2030 -9600 0 1 {name=l2583 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 2030 -9580 0 1 {name=l2584 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 2030 -9560 0 1 {name=l2585 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 2030 -9540 0 1 {name=l2586 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 2030 -9520 0 1 {name=l2587 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 2030 -9500 0 1 {name=l2588 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 2030 -9480 0 1 {name=l2589 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 2030 -9460 0 1 {name=l2590 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 2030 -9440 0 1 {name=l2591 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 2030 -9420 0 1 {name=l2592 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 2030 -9400 0 1 {name=l2593 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 2030 -9380 0 1 {name=l2594 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 2030 -9360 0 1 {name=l2595 sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 2030 -9340 0 1 {name=l2596 sig_type=std_logic lab=rB0} +C {devices/bus_connect_nolab.sym} 910 -8670 2 0 {name=r2151} +C {devices/bus_connect_nolab.sym} 910 -8690 2 0 {name=r2152} +C {devices/bus_connect_nolab.sym} 910 -8710 2 0 {name=r2153} +C {devices/bus_connect_nolab.sym} 910 -8730 2 0 {name=r2154} +C {devices/bus_connect_nolab.sym} 910 -8750 2 0 {name=r2155} +C {devices/bus_connect_nolab.sym} 910 -8770 2 0 {name=r2156} +C {devices/bus_connect_nolab.sym} 910 -8790 2 0 {name=r2157} +C {devices/bus_connect_nolab.sym} 910 -8810 2 0 {name=r2158} +C {devices/bus_connect_nolab.sym} 910 -8830 2 0 {name=r2159} +C {devices/bus_connect_nolab.sym} 910 -8850 2 0 {name=r2160} +C {devices/bus_connect_nolab.sym} 910 -8870 2 0 {name=r2161} +C {devices/bus_connect_nolab.sym} 910 -8890 2 0 {name=r2162} +C {devices/bus_connect_nolab.sym} 910 -8910 2 0 {name=r2163} +C {devices/bus_connect_nolab.sym} 910 -8930 2 0 {name=r2164} +C {devices/bus_connect_nolab.sym} 910 -8950 2 0 {name=r2165} +C {devices/bus_connect_nolab.sym} 910 -8970 2 0 {name=r2166} +C {devices/lab_pin.sym} 900 -8630 3 0 {name=l2597 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 1330 -8670 2 1 {name=r2167} +C {devices/bus_connect_nolab.sym} 1330 -8690 2 1 {name=r2168} +C {devices/bus_connect_nolab.sym} 1330 -8710 2 1 {name=r2169} +C {devices/bus_connect_nolab.sym} 1330 -8730 2 1 {name=r2170} +C {devices/bus_connect_nolab.sym} 1330 -8750 2 1 {name=r2171} +C {devices/bus_connect_nolab.sym} 1330 -8770 2 1 {name=r2172} +C {devices/bus_connect_nolab.sym} 1330 -8790 2 1 {name=r2173} +C {devices/bus_connect_nolab.sym} 1330 -8810 2 1 {name=r2174} +C {devices/bus_connect_nolab.sym} 1330 -8830 2 1 {name=r2175} +C {devices/bus_connect_nolab.sym} 1330 -8850 2 1 {name=r2176} +C {devices/bus_connect_nolab.sym} 1330 -8870 2 1 {name=r2177} +C {devices/bus_connect_nolab.sym} 1330 -8890 2 1 {name=r2178} +C {devices/bus_connect_nolab.sym} 1330 -8910 2 1 {name=r2179} +C {devices/bus_connect_nolab.sym} 1330 -8930 2 1 {name=r2180} +C {devices/bus_connect_nolab.sym} 1330 -8950 2 1 {name=r2181} +C {devices/bus_connect_nolab.sym} 1330 -8970 2 1 {name=r2182} +C {devices/lab_pin.sym} 1340 -8630 1 1 {name=l2598 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 950 -8690 0 0 {name=l2599 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 950 -8710 0 0 {name=l2600 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 950 -8730 0 0 {name=l2601 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 950 -8750 0 0 {name=l2602 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 950 -8770 0 0 {name=l2603 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 950 -8790 0 0 {name=l2604 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 950 -8810 0 0 {name=l2605 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 950 -8830 0 0 {name=l2606 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 950 -8850 0 0 {name=l2607 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 950 -8890 0 0 {name=l2608 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 950 -8870 0 0 {name=l2609 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 950 -8910 0 0 {name=l2610 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 950 -8930 0 0 {name=l2611 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 950 -8950 0 0 {name=l2612 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 950 -8970 0 0 {name=l2613 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 950 -8670 0 0 {name=l2614 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1290 -8690 0 1 {name=l2615 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1290 -8710 0 1 {name=l2616 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1290 -8730 0 1 {name=l2617 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1290 -8750 0 1 {name=l2618 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1290 -8770 0 1 {name=l2619 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1290 -8790 0 1 {name=l2620 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1290 -8810 0 1 {name=l2621 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1290 -8830 0 1 {name=l2622 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1290 -8850 0 1 {name=l2623 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1290 -8890 0 1 {name=l2624 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1290 -8870 0 1 {name=l2625 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1290 -8910 0 1 {name=l2626 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1290 -8930 0 1 {name=l2627 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1290 -8950 0 1 {name=l2628 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1290 -8970 0 1 {name=l2629 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1290 -8670 0 1 {name=l2630 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 1610 -8660 2 0 {name=r2183} +C {devices/bus_connect_nolab.sym} 1610 -8680 2 0 {name=r2184} +C {devices/bus_connect_nolab.sym} 1610 -8700 2 0 {name=r2185} +C {devices/bus_connect_nolab.sym} 1610 -8720 2 0 {name=r2186} +C {devices/bus_connect_nolab.sym} 1610 -8740 2 0 {name=r2187} +C {devices/bus_connect_nolab.sym} 1610 -8760 2 0 {name=r2188} +C {devices/bus_connect_nolab.sym} 1610 -8780 2 0 {name=r2189} +C {devices/bus_connect_nolab.sym} 1610 -8800 2 0 {name=r2190} +C {devices/bus_connect_nolab.sym} 1610 -8820 2 0 {name=r2191} +C {devices/bus_connect_nolab.sym} 1610 -8840 2 0 {name=r2192} +C {devices/bus_connect_nolab.sym} 1610 -8860 2 0 {name=r2193} +C {devices/bus_connect_nolab.sym} 1610 -8880 2 0 {name=r2194} +C {devices/bus_connect_nolab.sym} 1610 -8900 2 0 {name=r2195} +C {devices/bus_connect_nolab.sym} 1610 -8920 2 0 {name=r2196} +C {devices/bus_connect_nolab.sym} 1610 -8940 2 0 {name=r2197} +C {devices/bus_connect_nolab.sym} 1610 -8960 2 0 {name=r2198} +C {devices/lab_pin.sym} 1600 -8620 3 0 {name=l2631 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 2030 -8660 2 1 {name=r2199} +C {devices/bus_connect_nolab.sym} 2030 -8680 2 1 {name=r2200} +C {devices/bus_connect_nolab.sym} 2030 -8700 2 1 {name=r2201} +C {devices/bus_connect_nolab.sym} 2030 -8720 2 1 {name=r2202} +C {devices/bus_connect_nolab.sym} 2030 -8740 2 1 {name=r2203} +C {devices/bus_connect_nolab.sym} 2030 -8760 2 1 {name=r2204} +C {devices/bus_connect_nolab.sym} 2030 -8780 2 1 {name=r2205} +C {devices/bus_connect_nolab.sym} 2030 -8800 2 1 {name=r2206} +C {devices/bus_connect_nolab.sym} 2030 -8820 2 1 {name=r2207} +C {devices/bus_connect_nolab.sym} 2030 -8840 2 1 {name=r2208} +C {devices/bus_connect_nolab.sym} 2030 -8860 2 1 {name=r2209} +C {devices/bus_connect_nolab.sym} 2030 -8880 2 1 {name=r2210} +C {devices/bus_connect_nolab.sym} 2030 -8900 2 1 {name=r2211} +C {devices/bus_connect_nolab.sym} 2030 -8920 2 1 {name=r2212} +C {devices/bus_connect_nolab.sym} 2030 -8940 2 1 {name=r2213} +C {devices/bus_connect_nolab.sym} 2030 -8960 2 1 {name=r2214} +C {devices/lab_pin.sym} 2040 -8620 1 1 {name=l2632 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 1650 -8680 0 0 {name=l2633 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 1650 -8700 0 0 {name=l2634 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 1650 -8720 0 0 {name=l2635 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 1650 -8740 0 0 {name=l2636 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 1650 -8760 0 0 {name=l2637 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 1650 -8780 0 0 {name=l2638 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 1650 -8800 0 0 {name=l2639 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 1650 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sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1990 -8760 0 1 {name=l2653 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1990 -8780 0 1 {name=l2654 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1990 -8800 0 1 {name=l2655 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1990 -8820 0 1 {name=l2656 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1990 -8840 0 1 {name=l2657 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1990 -8880 0 1 {name=l2658 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1990 -8860 0 1 {name=l2659 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1990 -8900 0 1 {name=l2660 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1990 -8920 0 1 {name=l2661 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1990 -8940 0 1 {name=l2662 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1990 -8960 0 1 {name=l2663 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1990 -8660 0 1 {name=l2664 sig_type=std_logic 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sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 610 -11680 0 1 {name=l3067 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 610 -11660 0 1 {name=l3068 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 610 -11640 0 1 {name=l3069 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 610 -11620 0 1 {name=l3070 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 610 -11600 0 1 {name=l3071 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 610 -11580 0 1 {name=l3072 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 610 -11560 0 1 {name=l3073 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 610 -11540 0 1 {name=l3074 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 610 -11520 0 1 {name=l3075 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 610 -11500 0 1 {name=l3076 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 610 -11480 0 1 {name=l3077 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 610 -11460 0 1 {name=l3078 sig_type=std_logic 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lab=row5_sel} +C {devices/lab_pin.sym} 1610 -11990 0 0 {name=l3167 lab=col2_sel} +C {devices/lab_pin.sym} 1610 -11930 0 0 {name=l3168 lab=Vgpr} +C {devices/lab_pin.sym} 1610 -11970 0 0 {name=l3169 lab=Vgnr} +C {devices/lab_pin.sym} 1610 -11950 0 0 {name=l3170 lab=WR} +C {devices/lab_pin.sym} 1610 -11870 2 1 {name=l3171 lab=Vrplus} +C {devices/lab_pin.sym} 1610 -11810 0 0 {name=l3172 lab=Vref} +C {devices/lab_pin.sym} 1610 -11770 0 0 {name=l3173 lab=Vcplus} +C {devices/lab_pin.sym} 1610 -11790 0 0 {name=l3174 lab=Vcminus} +C {devices/lab_pin.sym} 1610 -11830 2 1 {name=l3175 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 1610 -11850 2 1 {name=l3176 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 2030 -11970 2 0 {name=l3177 lab=vdda1} +C {devices/lab_pin.sym} 2030 -11990 2 0 {name=l3179 lab=vccd1} +C {devices/bus_connect_nolab.sym} 1460 -11410 2 0 {name=r2599} +C {devices/bus_connect_nolab.sym} 1460 -11430 2 0 {name=r2600} +C {devices/bus_connect_nolab.sym} 1460 -11450 2 0 {name=r2601} +C {devices/bus_connect_nolab.sym} 1460 -11470 2 0 {name=r2602} +C {devices/bus_connect_nolab.sym} 1460 -11490 2 0 {name=r2603} +C {devices/bus_connect_nolab.sym} 1460 -11510 2 0 {name=r2604} +C {devices/bus_connect_nolab.sym} 1460 -11530 2 0 {name=r2605} +C {devices/bus_connect_nolab.sym} 1460 -11550 2 0 {name=r2606} +C {devices/bus_connect_nolab.sym} 1460 -11570 2 0 {name=r2607} +C {devices/bus_connect_nolab.sym} 1460 -11590 2 0 {name=r2608} +C {devices/bus_connect_nolab.sym} 1460 -11630 2 0 {name=r2609} +C {devices/bus_connect_nolab.sym} 1460 -11610 2 0 {name=r2610} +C {devices/bus_connect_nolab.sym} 1460 -11670 2 0 {name=r2611} +C {devices/bus_connect_nolab.sym} 1460 -11650 2 0 {name=r2612} +C {devices/bus_connect_nolab.sym} 1460 -11710 2 0 {name=r2613} +C {devices/bus_connect_nolab.sym} 1460 -11690 2 0 {name=r2614} +C {devices/lab_wire.sym} 1510 -11410 0 0 {name=l3180 sig_type=std_logic lab=rA0} +C {devices/lab_wire.sym} 1510 -11430 0 0 {name=l3181 sig_type=std_logic lab=rA1} +C {devices/lab_wire.sym} 1510 -11450 0 0 {name=l3182 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 1510 -11450 0 0 {name=l3183 sig_type=std_logic lab=rA2} +C {devices/lab_wire.sym} 1510 -11470 0 0 {name=l3184 sig_type=std_logic lab=rA3} +C {devices/lab_wire.sym} 1510 -11490 0 0 {name=l3185 sig_type=std_logic lab=rA4} +C {devices/lab_wire.sym} 1510 -11510 0 0 {name=l3186 sig_type=std_logic lab=rA5} +C {devices/lab_wire.sym} 1510 -11530 0 0 {name=l3187 sig_type=std_logic lab=rA6} +C {devices/lab_wire.sym} 1510 -11550 0 0 {name=l3188 sig_type=std_logic lab=rA7} +C {devices/lab_wire.sym} 1510 -11570 0 0 {name=l3189 sig_type=std_logic lab=rA8} +C {devices/lab_wire.sym} 1510 -11590 0 0 {name=l3190 sig_type=std_logic lab=rA9} +C {devices/lab_wire.sym} 1510 -11630 0 0 {name=l3191 sig_type=std_logic lab=rA11} +C {devices/lab_wire.sym} 1510 -11610 0 0 {name=l3192 sig_type=std_logic lab=rA10} +C {devices/lab_wire.sym} 1510 -11650 0 0 {name=l3193 sig_type=std_logic lab=rA12} +C {devices/lab_wire.sym} 1510 -11670 0 0 {name=l3194 sig_type=std_logic lab=rA13} +C {devices/lab_wire.sym} 1510 -11690 0 0 {name=l3195 sig_type=std_logic lab=rA14} +C {devices/lab_wire.sym} 1510 -11710 0 0 {name=l3196 sig_type=std_logic lab=rA15} +C {devices/lab_pin.sym} 1450 -11360 3 0 {name=l3197 sig_type=std_logic lab=rA[0..15]} +C {devices/bus_connect_nolab.sym} 2080 -11410 2 1 {name=r2615} +C {devices/bus_connect_nolab.sym} 2080 -11430 2 1 {name=r2616} +C {devices/bus_connect_nolab.sym} 2080 -11450 2 1 {name=r2617} +C {devices/bus_connect_nolab.sym} 2080 -11470 2 1 {name=r2618} +C {devices/bus_connect_nolab.sym} 2080 -11490 2 1 {name=r2619} +C {devices/bus_connect_nolab.sym} 2080 -11510 2 1 {name=r2620} +C {devices/bus_connect_nolab.sym} 2080 -11530 2 1 {name=r2621} +C {devices/bus_connect_nolab.sym} 2080 -11550 2 1 {name=r2622} +C {devices/bus_connect_nolab.sym} 2080 -11570 2 1 {name=r2623} +C {devices/bus_connect_nolab.sym} 2080 -11590 2 1 {name=r2624} +C {devices/bus_connect_nolab.sym} 2080 -11610 2 1 {name=r2625} +C {devices/bus_connect_nolab.sym} 2080 -11630 2 1 {name=r2626} +C {devices/bus_connect_nolab.sym} 2080 -11650 2 1 {name=r2627} +C {devices/bus_connect_nolab.sym} 2080 -11670 2 1 {name=r2628} +C {devices/bus_connect_nolab.sym} 2080 -11690 2 1 {name=r2629} +C {devices/bus_connect_nolab.sym} 2080 -11710 2 1 {name=r2630} +C {devices/lab_pin.sym} 2090 -11360 3 0 {name=l3198 sig_type=std_logic lab=rB[0..15]} +C {devices/lab_wire.sym} 2030 -11710 0 1 {name=l3199 sig_type=std_logic lab=rB15} +C {devices/lab_wire.sym} 2030 -11690 0 1 {name=l3200 sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 2030 -11670 0 1 {name=l3201 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 2030 -11650 0 1 {name=l3202 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 2030 -11630 0 1 {name=l3203 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 2030 -11610 0 1 {name=l3204 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 2030 -11590 0 1 {name=l3205 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 2030 -11570 0 1 {name=l3206 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 2030 -11550 0 1 {name=l3207 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 2030 -11530 0 1 {name=l3208 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 2030 -11510 0 1 {name=l3209 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 2030 -11490 0 1 {name=l3210 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 2030 -11470 0 1 {name=l3211 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 2030 -11450 0 1 {name=l3212 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 2030 -11430 0 1 {name=l3213 sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 2030 -11410 0 1 {name=l3214 sig_type=std_logic lab=rB0} +C {devices/bus_connect_nolab.sym} 910 -10740 2 0 {name=r2631} +C {devices/bus_connect_nolab.sym} 910 -10760 2 0 {name=r2632} +C {devices/bus_connect_nolab.sym} 910 -10780 2 0 {name=r2633} +C {devices/bus_connect_nolab.sym} 910 -10800 2 0 {name=r2634} +C {devices/bus_connect_nolab.sym} 910 -10820 2 0 {name=r2635} +C {devices/bus_connect_nolab.sym} 910 -10840 2 0 {name=r2636} +C {devices/bus_connect_nolab.sym} 910 -10860 2 0 {name=r2637} +C {devices/bus_connect_nolab.sym} 910 -10880 2 0 {name=r2638} +C {devices/bus_connect_nolab.sym} 910 -10900 2 0 {name=r2639} +C {devices/bus_connect_nolab.sym} 910 -10920 2 0 {name=r2640} +C {devices/bus_connect_nolab.sym} 910 -10940 2 0 {name=r2641} +C {devices/bus_connect_nolab.sym} 910 -10960 2 0 {name=r2642} +C {devices/bus_connect_nolab.sym} 910 -10980 2 0 {name=r2643} +C {devices/bus_connect_nolab.sym} 910 -11000 2 0 {name=r2644} +C {devices/bus_connect_nolab.sym} 910 -11020 2 0 {name=r2645} +C {devices/bus_connect_nolab.sym} 910 -11040 2 0 {name=r2646} +C {devices/lab_pin.sym} 900 -10700 3 0 {name=l3215 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 1330 -10740 2 1 {name=r2647} +C {devices/bus_connect_nolab.sym} 1330 -10760 2 1 {name=r2648} +C {devices/bus_connect_nolab.sym} 1330 -10780 2 1 {name=r2649} +C {devices/bus_connect_nolab.sym} 1330 -10800 2 1 {name=r2650} +C {devices/bus_connect_nolab.sym} 1330 -10820 2 1 {name=r2651} +C {devices/bus_connect_nolab.sym} 1330 -10840 2 1 {name=r2652} +C {devices/bus_connect_nolab.sym} 1330 -10860 2 1 {name=r2653} +C {devices/bus_connect_nolab.sym} 1330 -10880 2 1 {name=r2654} +C {devices/bus_connect_nolab.sym} 1330 -10900 2 1 {name=r2655} +C {devices/bus_connect_nolab.sym} 1330 -10920 2 1 {name=r2656} +C {devices/bus_connect_nolab.sym} 1330 -10940 2 1 {name=r2657} +C {devices/bus_connect_nolab.sym} 1330 -10960 2 1 {name=r2658} +C {devices/bus_connect_nolab.sym} 1330 -10980 2 1 {name=r2659} +C {devices/bus_connect_nolab.sym} 1330 -11000 2 1 {name=r2660} +C {devices/bus_connect_nolab.sym} 1330 -11020 2 1 {name=r2661} +C {devices/bus_connect_nolab.sym} 1330 -11040 2 1 {name=r2662} +C {devices/lab_pin.sym} 1340 -10700 1 1 {name=l3216 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 950 -10760 0 0 {name=l3217 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 950 -10780 0 0 {name=l3218 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 950 -10800 0 0 {name=l3219 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 950 -10820 0 0 {name=l3220 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 950 -10840 0 0 {name=l3221 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 950 -10860 0 0 {name=l3222 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 950 -10880 0 0 {name=l3223 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 950 -10900 0 0 {name=l3224 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 950 -10920 0 0 {name=l3225 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 950 -10960 0 0 {name=l3226 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 950 -10940 0 0 {name=l3227 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 950 -10980 0 0 {name=l3228 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 950 -11000 0 0 {name=l3229 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 950 -11020 0 0 {name=l3230 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 950 -11040 0 0 {name=l3231 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 950 -10740 0 0 {name=l3232 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1290 -10760 0 1 {name=l3233 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1290 -10780 0 1 {name=l3234 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1290 -10800 0 1 {name=l3235 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1290 -10820 0 1 {name=l3236 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1290 -10840 0 1 {name=l3237 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1290 -10860 0 1 {name=l3238 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1290 -10880 0 1 {name=l3239 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1290 -10900 0 1 {name=l3240 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1290 -10920 0 1 {name=l3241 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1290 -10960 0 1 {name=l3242 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1290 -10940 0 1 {name=l3243 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1290 -10980 0 1 {name=l3244 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1290 -11000 0 1 {name=l3245 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1290 -11020 0 1 {name=l3246 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1290 -11040 0 1 {name=l3247 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1290 -10740 0 1 {name=l3248 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 1610 -10730 2 0 {name=r2663} +C {devices/bus_connect_nolab.sym} 1610 -10750 2 0 {name=r2664} +C {devices/bus_connect_nolab.sym} 1610 -10770 2 0 {name=r2665} +C {devices/bus_connect_nolab.sym} 1610 -10790 2 0 {name=r2666} +C {devices/bus_connect_nolab.sym} 1610 -10810 2 0 {name=r2667} +C {devices/bus_connect_nolab.sym} 1610 -10830 2 0 {name=r2668} +C {devices/bus_connect_nolab.sym} 1610 -10850 2 0 {name=r2669} +C {devices/bus_connect_nolab.sym} 1610 -10870 2 0 {name=r2670} +C {devices/bus_connect_nolab.sym} 1610 -10890 2 0 {name=r2671} +C {devices/bus_connect_nolab.sym} 1610 -10910 2 0 {name=r2672} +C {devices/bus_connect_nolab.sym} 1610 -10930 2 0 {name=r2673} +C {devices/bus_connect_nolab.sym} 1610 -10950 2 0 {name=r2674} +C {devices/bus_connect_nolab.sym} 1610 -10970 2 0 {name=r2675} +C {devices/bus_connect_nolab.sym} 1610 -10990 2 0 {name=r2676} +C {devices/bus_connect_nolab.sym} 1610 -11010 2 0 {name=r2677} +C {devices/bus_connect_nolab.sym} 1610 -11030 2 0 {name=r2678} +C {devices/lab_pin.sym} 1600 -10690 3 0 {name=l3249 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 2030 -10730 2 1 {name=r2679} +C {devices/bus_connect_nolab.sym} 2030 -10750 2 1 {name=r2680} +C {devices/bus_connect_nolab.sym} 2030 -10770 2 1 {name=r2681} +C {devices/bus_connect_nolab.sym} 2030 -10790 2 1 {name=r2682} +C {devices/bus_connect_nolab.sym} 2030 -10810 2 1 {name=r2683} +C {devices/bus_connect_nolab.sym} 2030 -10830 2 1 {name=r2684} +C {devices/bus_connect_nolab.sym} 2030 -10850 2 1 {name=r2685} +C {devices/bus_connect_nolab.sym} 2030 -10870 2 1 {name=r2686} +C {devices/bus_connect_nolab.sym} 2030 -10890 2 1 {name=r2687} +C {devices/bus_connect_nolab.sym} 2030 -10910 2 1 {name=r2688} +C {devices/bus_connect_nolab.sym} 2030 -10930 2 1 {name=r2689} +C {devices/bus_connect_nolab.sym} 2030 -10950 2 1 {name=r2690} +C {devices/bus_connect_nolab.sym} 2030 -10970 2 1 {name=r2691} +C {devices/bus_connect_nolab.sym} 2030 -10990 2 1 {name=r2692} +C {devices/bus_connect_nolab.sym} 2030 -11010 2 1 {name=r2693} +C {devices/bus_connect_nolab.sym} 2030 -11030 2 1 {name=r2694} +C {devices/lab_pin.sym} 2040 -10690 1 1 {name=l3250 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 1650 -10750 0 0 {name=l3251 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 1650 -10770 0 0 {name=l3252 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 1650 -10790 0 0 {name=l3253 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 1650 -10810 0 0 {name=l3254 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 1650 -10830 0 0 {name=l3255 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 1650 -10850 0 0 {name=l3256 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 1650 -10870 0 0 {name=l3257 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 1650 -10890 0 0 {name=l3258 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 1650 -10910 0 0 {name=l3259 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 1650 -10950 0 0 {name=l3260 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 1650 -10930 0 0 {name=l3261 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 1650 -10970 0 0 {name=l3262 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 1650 -10990 0 0 {name=l3263 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 1650 -11010 0 0 {name=l3264 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 1650 -11030 0 0 {name=l3265 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 1650 -10730 0 0 {name=l3266 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1990 -10750 0 1 {name=l3267 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1990 -10770 0 1 {name=l3268 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1990 -10790 0 1 {name=l3269 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1990 -10810 0 1 {name=l3270 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1990 -10830 0 1 {name=l3271 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1990 -10850 0 1 {name=l3272 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1990 -10870 0 1 {name=l3273 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1990 -10890 0 1 {name=l3274 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1990 -10910 0 1 {name=l3275 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1990 -10950 0 1 {name=l3276 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1990 -10930 0 1 {name=l3277 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1990 -10970 0 1 {name=l3278 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1990 -10990 0 1 {name=l3279 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1990 -11010 0 1 {name=l3280 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1990 -11030 0 1 {name=l3281 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1990 -10730 0 1 {name=l3282 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 2190 -11420 2 0 {name=r2695} +C {devices/bus_connect_nolab.sym} 2190 -11440 2 0 {name=r2696} +C {devices/bus_connect_nolab.sym} 2190 -11460 2 0 {name=r2697} +C {devices/bus_connect_nolab.sym} 2190 -11480 2 0 {name=r2698} +C {devices/bus_connect_nolab.sym} 2190 -11500 2 0 {name=r2699} +C {devices/bus_connect_nolab.sym} 2190 -11520 2 0 {name=r2700} +C {devices/bus_connect_nolab.sym} 2190 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sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 1330 -13490 0 1 {name=l3769 sig_type=std_logic lab=rB0} +C {devices/lab_pin.sym} 910 -14010 0 0 {name=l3770 lab=Vgpr} +C {devices/lab_pin.sym} 910 -14050 0 0 {name=l3771 lab=Vgnr} +C {devices/lab_pin.sym} 910 -14030 0 0 {name=l3772 lab=WR} +C {devices/lab_pin.sym} 910 -13950 2 1 {name=l3773 lab=Vrplus} +C {devices/lab_pin.sym} 910 -13890 0 0 {name=l3774 lab=Vref} +C {devices/lab_pin.sym} 910 -13850 0 0 {name=l3775 lab=Vcplus} +C {devices/lab_pin.sym} 910 -13870 0 0 {name=l3776 lab=Vcminus} +C {devices/lab_pin.sym} 910 -13910 2 1 {name=l3777 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 910 -13930 2 1 {name=l3778 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 1330 -14050 2 0 {name=l3779 lab=vdda1} +C {devices/lab_pin.sym} 1330 -14070 2 0 {name=l3781 lab=vccd1} +C {devices/lab_pin.sym} 1610 -13960 2 1 {name=l3782 lab=Vrminus} +C {devices/lab_pin.sym} 1610 -13980 0 0 {name=l3783 lab=SAMPLE} +C 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{devices/bus_connect_nolab.sym} 2080 -13660 2 1 {name=r3104} +C {devices/bus_connect_nolab.sym} 2080 -13680 2 1 {name=r3105} +C {devices/bus_connect_nolab.sym} 2080 -13700 2 1 {name=r3106} +C {devices/bus_connect_nolab.sym} 2080 -13720 2 1 {name=r3107} +C {devices/bus_connect_nolab.sym} 2080 -13740 2 1 {name=r3108} +C {devices/bus_connect_nolab.sym} 2080 -13760 2 1 {name=r3109} +C {devices/bus_connect_nolab.sym} 2080 -13780 2 1 {name=r3110} +C {devices/lab_pin.sym} 2090 -13430 3 0 {name=l3816 sig_type=std_logic lab=rB[0..15]} +C {devices/lab_wire.sym} 2030 -13780 0 1 {name=l3817 sig_type=std_logic lab=rB15} +C {devices/lab_wire.sym} 2030 -13760 0 1 {name=l3818 sig_type=std_logic lab=rB14} +C {devices/lab_wire.sym} 2030 -13740 0 1 {name=l3819 sig_type=std_logic lab=rB13} +C {devices/lab_wire.sym} 2030 -13720 0 1 {name=l3820 sig_type=std_logic lab=rB12} +C {devices/lab_wire.sym} 2030 -13700 0 1 {name=l3821 sig_type=std_logic lab=rB11} +C {devices/lab_wire.sym} 2030 -13680 0 1 {name=l3822 sig_type=std_logic lab=rB10} +C {devices/lab_wire.sym} 2030 -13660 0 1 {name=l3823 sig_type=std_logic lab=rB9} +C {devices/lab_wire.sym} 2030 -13640 0 1 {name=l3824 sig_type=std_logic lab=rB8} +C {devices/lab_wire.sym} 2030 -13620 0 1 {name=l3825 sig_type=std_logic lab=rB7} +C {devices/lab_wire.sym} 2030 -13600 0 1 {name=l3826 sig_type=std_logic lab=rB6} +C {devices/lab_wire.sym} 2030 -13580 0 1 {name=l3827 sig_type=std_logic lab=rB5} +C {devices/lab_wire.sym} 2030 -13560 0 1 {name=l3828 sig_type=std_logic lab=rB4} +C {devices/lab_wire.sym} 2030 -13540 0 1 {name=l3829 sig_type=std_logic lab=rB3} +C {devices/lab_wire.sym} 2030 -13520 0 1 {name=l3830 sig_type=std_logic lab=rB2} +C {devices/lab_wire.sym} 2030 -13500 0 1 {name=l3831 sig_type=std_logic lab=rB1} +C {devices/lab_wire.sym} 2030 -13480 0 1 {name=l3832 sig_type=std_logic lab=rB0} +C {devices/bus_connect_nolab.sym} 910 -12810 2 0 {name=r3111} +C {devices/bus_connect_nolab.sym} 910 -12830 2 0 {name=r3112} +C {devices/bus_connect_nolab.sym} 910 -12850 2 0 {name=r3113} +C {devices/bus_connect_nolab.sym} 910 -12870 2 0 {name=r3114} +C {devices/bus_connect_nolab.sym} 910 -12890 2 0 {name=r3115} +C {devices/bus_connect_nolab.sym} 910 -12910 2 0 {name=r3116} +C {devices/bus_connect_nolab.sym} 910 -12930 2 0 {name=r3117} +C {devices/bus_connect_nolab.sym} 910 -12950 2 0 {name=r3118} +C {devices/bus_connect_nolab.sym} 910 -12970 2 0 {name=r3119} +C {devices/bus_connect_nolab.sym} 910 -12990 2 0 {name=r3120} +C {devices/bus_connect_nolab.sym} 910 -13010 2 0 {name=r3121} +C {devices/bus_connect_nolab.sym} 910 -13030 2 0 {name=r3122} +C {devices/bus_connect_nolab.sym} 910 -13050 2 0 {name=r3123} +C {devices/bus_connect_nolab.sym} 910 -13070 2 0 {name=r3124} +C {devices/bus_connect_nolab.sym} 910 -13090 2 0 {name=r3125} +C {devices/bus_connect_nolab.sym} 910 -13110 2 0 {name=r3126} +C {devices/lab_pin.sym} 900 -12770 3 0 {name=l3833 sig_type=std_logic lab=cA[0..15]} +C {devices/bus_connect_nolab.sym} 1330 -12810 2 1 {name=r3127} +C {devices/bus_connect_nolab.sym} 1330 -12830 2 1 {name=r3128} +C {devices/bus_connect_nolab.sym} 1330 -12850 2 1 {name=r3129} +C {devices/bus_connect_nolab.sym} 1330 -12870 2 1 {name=r3130} +C {devices/bus_connect_nolab.sym} 1330 -12890 2 1 {name=r3131} +C {devices/bus_connect_nolab.sym} 1330 -12910 2 1 {name=r3132} +C {devices/bus_connect_nolab.sym} 1330 -12930 2 1 {name=r3133} +C {devices/bus_connect_nolab.sym} 1330 -12950 2 1 {name=r3134} +C {devices/bus_connect_nolab.sym} 1330 -12970 2 1 {name=r3135} +C {devices/bus_connect_nolab.sym} 1330 -12990 2 1 {name=r3136} +C {devices/bus_connect_nolab.sym} 1330 -13010 2 1 {name=r3137} +C {devices/bus_connect_nolab.sym} 1330 -13030 2 1 {name=r3138} +C {devices/bus_connect_nolab.sym} 1330 -13050 2 1 {name=r3139} +C {devices/bus_connect_nolab.sym} 1330 -13070 2 1 {name=r3140} +C {devices/bus_connect_nolab.sym} 1330 -13090 2 1 {name=r3141} +C {devices/bus_connect_nolab.sym} 1330 -13110 2 1 {name=r3142} +C {devices/lab_pin.sym} 1340 -12770 1 1 {name=l3834 sig_type=std_logic lab=cB[0..15]} +C {devices/lab_wire.sym} 950 -12830 0 0 {name=l3835 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 950 -12850 0 0 {name=l3836 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 950 -12870 0 0 {name=l3837 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 950 -12890 0 0 {name=l3838 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 950 -12910 0 0 {name=l3839 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 950 -12930 0 0 {name=l3840 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 950 -12950 0 0 {name=l3841 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 950 -12970 0 0 {name=l3842 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 950 -12990 0 0 {name=l3843 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 950 -13030 0 0 {name=l3844 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 950 -13010 0 0 {name=l3845 sig_type=std_logic lab=cA10} +C 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{devices/lab_wire.sym} 1290 -12970 0 1 {name=l3858 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1290 -12990 0 1 {name=l3859 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1290 -13030 0 1 {name=l3860 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1290 -13010 0 1 {name=l3861 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1290 -13050 0 1 {name=l3862 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1290 -13070 0 1 {name=l3863 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1290 -13090 0 1 {name=l3864 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1290 -13110 0 1 {name=l3865 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1290 -12810 0 1 {name=l3866 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 1610 -12800 2 0 {name=r3143} +C {devices/bus_connect_nolab.sym} 1610 -12820 2 0 {name=r3144} +C {devices/bus_connect_nolab.sym} 1610 -12840 2 0 {name=r3145} +C {devices/bus_connect_nolab.sym} 1610 -12860 2 0 {name=r3146} +C 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{devices/lab_wire.sym} 1650 -12820 0 0 {name=l3869 sig_type=std_logic lab=cA1} +C {devices/lab_wire.sym} 1650 -12840 0 0 {name=l3870 sig_type=std_logic lab=cA2} +C {devices/lab_wire.sym} 1650 -12860 0 0 {name=l3871 sig_type=std_logic lab=cA3} +C {devices/lab_wire.sym} 1650 -12880 0 0 {name=l3872 sig_type=std_logic lab=cA4} +C {devices/lab_wire.sym} 1650 -12900 0 0 {name=l3873 sig_type=std_logic lab=cA5} +C {devices/lab_wire.sym} 1650 -12920 0 0 {name=l3874 sig_type=std_logic lab=cA6} +C {devices/lab_wire.sym} 1650 -12940 0 0 {name=l3875 sig_type=std_logic lab=cA7} +C {devices/lab_wire.sym} 1650 -12960 0 0 {name=l3876 sig_type=std_logic lab=cA8} +C {devices/lab_wire.sym} 1650 -12980 0 0 {name=l3877 sig_type=std_logic lab=cA9} +C {devices/lab_wire.sym} 1650 -13020 0 0 {name=l3878 sig_type=std_logic lab=cA11} +C {devices/lab_wire.sym} 1650 -13000 0 0 {name=l3879 sig_type=std_logic lab=cA10} +C {devices/lab_wire.sym} 1650 -13040 0 0 {name=l3880 sig_type=std_logic lab=cA12} +C {devices/lab_wire.sym} 1650 -13060 0 0 {name=l3881 sig_type=std_logic lab=cA13} +C {devices/lab_wire.sym} 1650 -13080 0 0 {name=l3882 sig_type=std_logic lab=cA14} +C {devices/lab_wire.sym} 1650 -13100 0 0 {name=l3883 sig_type=std_logic lab=cA15} +C {devices/lab_wire.sym} 1650 -12800 0 0 {name=l3884 sig_type=std_logic lab=cA0} +C {devices/lab_wire.sym} 1990 -12820 0 1 {name=l3885 sig_type=std_logic lab=cB1} +C {devices/lab_wire.sym} 1990 -12840 0 1 {name=l3886 sig_type=std_logic lab=cB2} +C {devices/lab_wire.sym} 1990 -12860 0 1 {name=l3887 sig_type=std_logic lab=cB3} +C {devices/lab_wire.sym} 1990 -12880 0 1 {name=l3888 sig_type=std_logic lab=cB4} +C {devices/lab_wire.sym} 1990 -12900 0 1 {name=l3889 sig_type=std_logic lab=cB5} +C {devices/lab_wire.sym} 1990 -12920 0 1 {name=l3890 sig_type=std_logic lab=cB6} +C {devices/lab_wire.sym} 1990 -12940 0 1 {name=l3891 sig_type=std_logic lab=cB7} +C {devices/lab_wire.sym} 1990 -12960 0 1 {name=l3892 sig_type=std_logic lab=cB8} +C {devices/lab_wire.sym} 1990 -12980 0 1 {name=l3893 sig_type=std_logic lab=cB9} +C {devices/lab_wire.sym} 1990 -13020 0 1 {name=l3894 sig_type=std_logic lab=cB11} +C {devices/lab_wire.sym} 1990 -13000 0 1 {name=l3895 sig_type=std_logic lab=cB10} +C {devices/lab_wire.sym} 1990 -13040 0 1 {name=l3896 sig_type=std_logic lab=cB12} +C {devices/lab_wire.sym} 1990 -13060 0 1 {name=l3897 sig_type=std_logic lab=cB13} +C {devices/lab_wire.sym} 1990 -13080 0 1 {name=l3898 sig_type=std_logic lab=cB14} +C {devices/lab_wire.sym} 1990 -13100 0 1 {name=l3899 sig_type=std_logic lab=cB15} +C {devices/lab_wire.sym} 1990 -12800 0 1 {name=l3900 sig_type=std_logic lab=cB0} +C {devices/bus_connect_nolab.sym} 2190 -13490 2 0 {name=r3175} +C {devices/bus_connect_nolab.sym} 2190 -13510 2 0 {name=r3176} +C {devices/bus_connect_nolab.sym} 2190 -13530 2 0 {name=r3177} +C {devices/bus_connect_nolab.sym} 2190 -13550 2 0 {name=r3178} +C {devices/bus_connect_nolab.sym} 2190 -13570 2 0 {name=r3179} +C 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lab=Vref_comp} +C {devices/lab_pin.sym} 3040 -13920 2 1 {name=l4301 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 3750 -13960 2 1 {name=l4302 lab=Vrminus} +C {devices/lab_pin.sym} 3750 -13980 0 0 {name=l4303 lab=SAMPLE} +C {devices/lab_pin.sym} 3750 -14080 0 0 {name=l4304 lab=row6_sel} +C {devices/lab_pin.sym} 3750 -14060 0 0 {name=l4305 lab=col5_sel} +C {devices/lab_pin.sym} 3750 -14000 0 0 {name=l4306 lab=Vgpr} +C {devices/lab_pin.sym} 3750 -14040 0 0 {name=l4307 lab=Vgnr} +C {devices/lab_pin.sym} 3750 -14020 0 0 {name=l4308 lab=WR} +C {devices/lab_pin.sym} 3750 -13940 2 1 {name=l4309 lab=Vrplus} +C {devices/lab_pin.sym} 3750 -13880 0 0 {name=l4310 lab=Vref} +C {devices/lab_pin.sym} 3750 -13840 0 0 {name=l4311 lab=Vcplus} +C {devices/lab_pin.sym} 3750 -13860 0 0 {name=l4312 lab=Vcminus} +C {devices/lab_pin.sym} 3750 -13900 2 1 {name=l4313 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 3750 -13920 2 1 {name=l4314 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 190 -13970 2 1 {name=l4315 lab=Vrminus} +C {devices/lab_pin.sym} 190 -13990 0 0 {name=l4316 lab=SAMPLE} +C {devices/lab_pin.sym} 190 -14010 0 0 {name=l4317 lab=Vgpr} +C {devices/lab_pin.sym} 190 -14050 0 0 {name=l4318 lab=Vgnr} +C {devices/lab_pin.sym} 190 -14030 0 0 {name=l4319 lab=WR} +C {devices/lab_pin.sym} 190 -13950 2 1 {name=l4320 lab=Vrplus} +C {devices/lab_pin.sym} 190 -13890 0 0 {name=l4321 lab=Vref} +C {devices/lab_pin.sym} 190 -13850 0 0 {name=l4322 lab=Vcplus} +C {devices/lab_pin.sym} 190 -13870 0 0 {name=l4323 lab=Vcminus} +C {devices/lab_pin.sym} 190 -13910 2 1 {name=l4324 sig_type=std_logic lab=Vref_comp} +C {devices/lab_pin.sym} 190 -13930 2 1 {name=l4325 sig_type=std_logic lab=RISC_CLK} +C {devices/lab_pin.sym} 610 -14050 2 0 {name=l4326 lab=vdda1} +C {devices/lab_pin.sym} 610 -14070 2 0 {name=l4328 lab=vccd1} +C {devices/lab_pin.sym} 610 -14090 2 0 {name=l4329 lab=latch_high0} +C {devices/lab_pin.sym} 2030 -14080 2 0 {name=l4330 lab=latch_high2} +C {devices/lab_pin.sym} 2760 -14090 2 0 {name=l4331 lab=latch_high3} +C {devices/lab_pin.sym} 3460 -14080 2 0 {name=l4332 lab=latch_high4} +C {devices/lab_pin.sym} 4170 -14080 2 0 {name=l4333 lab=latch_high5} +C {devices/lab_pin.sym} 1330 -14090 2 0 {name=l4334 lab=latch_high1} +C {devices/lab_pin.sym} -760 -1320 2 1 {name=l4335 lab=EN} +C {devices/lab_pin.sym} 610 -1770 2 0 {name=l4133 lab=vdda1} +C {devices/lab_pin.sym} 610 -1750 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 610 -1790 2 0 {name=l4135 lab=vccd1} +C {devices/lab_pin.sym} 1330 -1750 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 2030 -1740 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 2760 -1750 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 3460 -1740 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 4170 -1740 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 610 -3880 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -3880 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -3870 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -3880 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -3870 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -3870 0 1 {name=l5 lab=vssa1} +C {devices/lab_pin.sym} 610 -5880 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -5880 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -5870 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -5880 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -5870 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -5870 0 1 {name=l5 lab=vssa1} +C {devices/lab_pin.sym} 610 -7900 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -7900 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -7890 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -7900 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -7890 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -7890 0 1 {name=l5 lab=vssa1} +C {devices/lab_pin.sym} 610 -9890 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -9890 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -9880 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -9890 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -9880 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -9880 0 1 {name=l5 lab=vssa1} +C {devices/lab_pin.sym} 610 -11960 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -11960 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -11950 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -11960 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -11950 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -11950 0 1 {name=l5 lab=vssa1} +C {devices/lab_pin.sym} 610 -14030 0 1 {name=l4134 lab=vssa1} +C {devices/lab_pin.sym} 1330 -14030 0 1 {name=l1 lab=vssa1} +C {devices/lab_pin.sym} 2030 -14020 0 1 {name=l2 lab=vssa1} +C {devices/lab_pin.sym} 2760 -14030 0 1 {name=l3 lab=vssa1} +C {devices/lab_pin.sym} 3460 -14020 0 1 {name=l4 lab=vssa1} +C {devices/lab_pin.sym} 4170 -14020 0 1 {name=l5 lab=vssa1}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice index 0dc2d20..6b581ff 100644 --- a/xschem/user_analog_project_wrapper.spice +++ b/xschem/user_analog_project_wrapper.spice
@@ -1,202 +1,4557 @@ -.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i -+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31] -+ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23] -+ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15] -+ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7] -+ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31] -+ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23] -+ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15] -+ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7] -+ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o -+ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24] -+ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16] -+ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8] -+ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0] -+ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121] -+ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114] -+ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107] -+ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100] -+ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93] -+ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86] -+ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79] -+ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72] -+ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65] -+ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58] -+ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51] -+ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44] -+ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37] -+ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30] -+ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23] -+ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16] -+ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9] -+ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1] -+ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123] -+ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117] -+ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111] -+ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105] -+ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98] -+ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91] -+ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84] -+ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77] -+ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70] -+ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63] -+ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56] -+ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49] -+ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42] -+ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35] -+ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28] -+ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21] -+ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14] -+ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7] -+ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0] io_in[26] -+ io_in[25] io_in[24] io_in[23] io_in[22] io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] -+ io_in[14] io_in[13] io_in[12] io_in[11] io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] -+ io_in[3] io_in[2] io_in[1] io_in[0] io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] -+ io_in_3v3[21] io_in_3v3[20] io_in_3v3[19] io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] -+ io_in_3v3[13] io_in_3v3[12] io_in_3v3[11] io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] -+ io_in_3v3[5] io_in_3v3[4] io_in_3v3[3] io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] user_clock2 io_out[26] io_out[25] -+ io_out[24] io_out[23] io_out[22] io_out[21] io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] -+ io_out[14] io_out[13] io_out[12] io_out[11] io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] -+ io_out[4] io_out[3] io_out[2] io_out[1] io_out[0] io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] -+ io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17] io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] -+ io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7] io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] -+ io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16] gpio_analog[15] gpio_analog[14] gpio_analog[13] -+ gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9] gpio_analog[8] gpio_analog[7] gpio_analog[6] -+ gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2] gpio_analog[1] gpio_analog[0] gpio_noesd[17] -+ gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13] gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] -+ gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5] gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] -+ gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[5] -+ io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] io_clamp_high[2] io_clamp_high[1] -+ io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_irq[2] user_irq[1] user_irq[0] la_oenb[127] -+ la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120] la_oenb[119] -+ la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112] la_oenb[111] -+ la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104] la_oenb[103] -+ la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95] la_oenb[94] -+ la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86] la_oenb[85] -+ la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77] la_oenb[76] -+ la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68] la_oenb[67] -+ la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59] la_oenb[58] -+ la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50] la_oenb[49] -+ la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41] la_oenb[40] -+ la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32] la_oenb[31] -+ la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23] la_oenb[22] -+ la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14] la_oenb[13] -+ la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5] la_oenb[4] -+ la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] -*.iopin vdda1 -*.iopin vdda2 -*.iopin vssa1 -*.iopin vssa2 -*.iopin vccd1 -*.iopin vccd2 -*.iopin vssd1 -*.iopin vssd2 -*.ipin wb_clk_i -*.ipin wb_rst_i -*.ipin wbs_stb_i -*.ipin wbs_cyc_i -*.ipin wbs_we_i -*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0] -*.ipin -*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0] -*.ipin -*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] -*.opin wbs_ack_o -*.opin -*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0] -*.ipin -*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0] -*.opin -*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0] -*.ipin -*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0] -*.ipin -*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] -*.ipin user_clock2 -*.opin -*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0] -*.opin -*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0] -*.iopin -*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0] -*.iopin -*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0] -*.iopin -*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] -*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] -*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0] -*.opin user_irq[2],user_irq[1],user_irq[0] -*.ipin -*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0] -x1 vdda1 vccd1 gpio_analog[3] io_out[11] io_out[12] vssa1 example_por -x2 io_analog[4] vccd1 gpio_analog[7] io_out[15] io_out[16] vssa1 example_por -R1 vssa1 io_clamp_low[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R2 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R3 vssa1 io_clamp_high[2] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1 -R4 vssa1 io_clamp_low[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R5 vssa1 io_clamp_high[1] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R6 vssa1 io_clamp_low[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R7 io_analog[4] io_clamp_high[0] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R8 vssd1 io_oeb[15] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R9 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R10 vssd1 io_oeb[16] sky130_fd_pr__res_generic_m1 W=1 L=1 m=1 -R11 vssd1 io_oeb[11] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 -R12 vssd1 io_oeb[12] sky130_fd_pr__res_generic_m3 W=1 L=1 m=1 +* NGSPICE file created from user_analog_project_wrapper.ext - technology: sky130B + +.subckt sky130_fd_sc_hd__and4_4 A B C D VGND VPWR X VNB VPB +X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=1.43e+12p pd=1.286e+07u as=5.4e+11p ps=5.08e+06u w=1e+06u l=150000u +X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X2 a_188_47# B a_109_47# VNB sky130_fd_pr__nfet_01v8 ad=2.1775e+11p pd=1.97e+06u as=1.5925e+11p ps=1.79e+06u w=650000u l=150000u +X3 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X4 VGND D a_285_47# VNB sky130_fd_pr__nfet_01v8 ad=5.5575e+11p pd=5.61e+06u as=2.8275e+11p ps=2.17e+06u w=650000u l=150000u +X5 VPWR D a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=7e+11p ps=5.4e+06u w=1e+06u l=150000u +X6 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.51e+11p ps=3.68e+06u w=650000u l=150000u +X8 VPWR B a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X9 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X10 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X11 a_27_47# C VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X12 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X13 a_27_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X14 a_285_47# C a_188_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X15 a_109_47# A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u .ends -* expanding symbol: example_por.sym # of pins=6 -* sym_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sym -* sch_path: /home/tim/gits/caravel_user_project_analog/xschem/example_por.sch -.subckt example_por vdd3v3 vdd1v8 porb_h porb_l por_l vss -*.iopin vdd3v3 -*.iopin vss -*.opin porb_h -*.opin porb_l -*.opin por_l -*.iopin vdd1v8 -XC1 net9 vss sky130_fd_pr__cap_mim_m3_1 W=30 L=30 MF=1 m=1 -XC2 vss net9 sky130_fd_pr__cap_mim_m3_2 W=30 L=30 MF=1 m=1 -XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM2 net2 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR1 net4 vdd3v3 vss sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1 -XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM5 net3 net3 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XR2 vss net4 vss sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1 -XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM8 net1 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM10 net7 net4 vss vss sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' -+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' -+ sa=0 sb=0 sd=0 mult=1 m=1 -XM9 net7 net7 net6 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM11 net6 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=16 nf=8 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' -+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' -+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1 -XR3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2 -x2 net10 vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 -x3 net10 vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 -x4 net10 vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 -x5 net9 vss vss vdd3v3 vdd3v3 net10 sky130_fd_sc_hvl__schmittbuf_1 +.subckt sky130_fd_sc_hd__inv_16 A VGND VPWR Y VNB VPB +X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.16e+12p pd=2.032e+07u as=2.41e+12p ps=2.282e+07u w=1e+06u l=150000u +X1 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X2 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=1.5665e+12p pd=1.652e+07u as=1.404e+12p ps=1.472e+07u w=650000u l=150000u +X3 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X4 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X5 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X6 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X8 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X9 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X10 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X11 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X12 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X13 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X14 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X15 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X16 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X17 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X18 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X19 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X20 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X21 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X22 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X23 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X24 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X25 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X26 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X27 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X28 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X29 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X30 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X31 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u .ends -** flattened .save nodes -.end +.subckt decoder_3to8_top Y5 Y6 Y7 IN1 Y4 Y1 Y0 Y3 EN Y2 IN2 IN0 VP VN +Xsky130_fd_sc_hd__and4_4_2 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_3 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_4 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_5 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_6 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_7 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_8 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_9 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_70 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_60 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_71 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_50 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_61 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_72 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_40 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_51 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_62 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_73 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_30 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_41 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_52 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_63 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_74 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_75 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_20 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_31 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_42 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_53 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_64 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_76 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_65 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_10 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_21 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_32 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_43 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_54 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_77 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_66 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_55 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_11 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_22 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_33 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_44 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_78 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_67 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_56 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_45 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_12 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_23 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_34 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_79 IN2 IN1 IN0 EN VN VP Y7 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_68 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_57 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_46 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_35 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_13 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_24 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_69 IN2 IN1 IN0b EN VN VP Y6 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_58 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_47 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_36 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_25 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_14 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_59 IN2 IN1b IN0 EN VN VP Y5 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_48 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_37 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_26 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_15 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_49 IN2 IN1b IN0b EN VN VP Y4 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_38 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_27 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_16 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_39 IN2b IN1 IN0 EN VN VP Y3 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_28 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_17 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_29 IN2b IN1 IN0b EN VN VP Y2 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_18 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_19 IN2b IN1b IN0 EN VN VP Y1 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__inv_16_0 IN0 VN VP IN0b VN VP sky130_fd_sc_hd__inv_16 +Xsky130_fd_sc_hd__inv_16_1 IN1 VN VP IN1b VN VP sky130_fd_sc_hd__inv_16 +Xsky130_fd_sc_hd__and4_4_0 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__and4_4_1 IN2b IN1b IN0b EN VN VP Y0 VN VP sky130_fd_sc_hd__and4_4 +Xsky130_fd_sc_hd__inv_16_2 IN2 VN VP IN2b VN VP sky130_fd_sc_hd__inv_16 +.ends + +.subckt top_interconnect WL4 col5_sel A2c latch_high5 row6_sel WL3 latch_high4 A3c ++ m4_556058_405560# WL2 A4c latch_high3 m2_510582_695380# col2_sel B0r power_interconnect_8/m4_556680_101952# ++ WL1 m4_555338_405560# A5c latch_high2 row3_sel B1r WL0 A6c latch_high1 WR SAMPLE ++ B2r A7c latch_high0 B3r A8c A10c power_interconnect_5/m4_555338_13760# row0_sel ++ B4r A9c A11c B5r power_interconnect_7/m4_557302_101232# A12c B6r A13c B7r A14c power_interconnect_6/m4_555960_102672# ++ Vrplus m4_557498_405560# B8r Vcminus A15c B9r m4_556778_405560# RISC_CLK power_interconnect_4/m4_557302_101232# ++ col3_sel row4_sel B10r RSEL1 B11r RSEL0 col0_sel power_interconnect_4/m4_555338_13760# ++ B12r row1_sel B0c B13r power_interconnect_4/m4_555960_102672# B1c m4_556778_499484# ++ B14r A0r RSEL2 B2c B15r A1r B3c Vref_comp power_interconnect_1/m4_556680_102672# ++ A2r m4_557498_499484# B4c power_interconnect_4/m4_556680_101952# A3r m4_556058_604820# ++ B5c A4r vssa1 m4_555338_604820# CSEL1 B6c power_interconnect_6/m4_555338_13760# ++ A5r power_interconnect_5/m4_555960_102672# B7c CSEL0 col4_sel WL15 A6r Vcplus row5_sel ++ B8c WL14 A7r Vgnr EN B9c WL13 A10r A8r power_interconnect_3/m4_557302_101232# col1_sel ++ WL12 A11r A9r Vgpr power_interconnect_1/m4_555960_101952# m4_555338_499484# row2_sel ++ WL11 A12r B10c WL10 A13r power_interconnect_6/m4_556680_101952# power_interconnect_8/m4_557302_101232# ++ power_interconnect_8/m4_555338_13760# WL9 A14r B11c vccd1 m4_557498_604820# power_interconnect_3/m4_555338_13760# ++ WL8 B12c A15r power_interconnect_1/m4_555338_13760# m4_556058_499484# Vref m4_556778_604820# ++ power_interconnect_7/m4_555960_102672# WL7 B13c Vrminus WL6 B14c A0c CSEL2 WL5 B15c ++ A1c VSUBS vdda1 m3_557498_235220# power_interconnect_3/m4_556680_101952# +Xdecoder_3to8_top_0 col5_sel decoder_3to8_top_0/Y6 decoder_3to8_top_0/Y7 CSEL1 col4_sel ++ col1_sel col0_sel col3_sel EN col2_sel CSEL2 CSEL0 vccd1 VSUBS decoder_3to8_top +Xdecoder_3to8_top_1 row5_sel row6_sel decoder_3to8_top_1/Y7 RSEL1 row4_sel row1_sel ++ row0_sel row3_sel EN row2_sel RSEL2 RSEL0 vccd1 VSUBS decoder_3to8_top +.ends + +.subckt sky130_fd_sc_hd__inv_8 A VGND VPWR Y VNB VPB +X0 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=1.33e+12p pd=1.266e+07u as=1.08e+12p ps=1.016e+07u w=1e+06u l=150000u +X1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X2 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=7.02e+11p pd=7.36e+06u as=8.645e+11p ps=9.16e+06u w=650000u l=150000u +X3 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X4 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X5 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X6 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X7 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X8 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X9 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X10 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X11 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X12 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X13 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X14 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X15 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +.ends + +.subckt comp_out_sel latch_high latch_high_col vccd1 row_sel vssd1 +Xsky130_fd_sc_hd__inv_8_0 latch_high vssd1 vccd1 sky130_fd_sc_hd__inv_8_0/Y vssd1 ++ vccd1 sky130_fd_sc_hd__inv_8 +Xsky130_fd_sc_hd__inv_8_1 row_sel vssd1 vccd1 row_selb vssd1 vccd1 sky130_fd_sc_hd__inv_8 +Xsky130_fd_sc_hd__inv_16_0 row_selb vssd1 vccd1 row_selbuff vssd1 vccd1 sky130_fd_sc_hd__inv_16 +X0 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=1.242e+13p pd=1.1284e+08u as=1.325e+13p ps=1.165e+08u w=1e+06u l=150000u +X1 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=8.05675e+12p pd=8.199e+07u as=8.59625e+12p ps=8.495e+07u w=650000u l=150000u +X2 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=5.9e+12p ps=5.18e+07u w=1e+06u l=150000u +X3 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.835e+12p ps=3.78e+07u w=650000u l=150000u +X4 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X5 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X6 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X8 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X9 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X10 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X11 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X12 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X13 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X14 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X15 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X16 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X17 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X18 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X19 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X20 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X21 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X22 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X23 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X24 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X25 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X26 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X27 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X28 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X29 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X30 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X31 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X32 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X33 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X34 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X35 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X36 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X37 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X38 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X39 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X40 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X41 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X42 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X43 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X44 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X45 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X46 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X47 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X48 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X49 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X50 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X51 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X52 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X53 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X54 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X55 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X56 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X57 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X58 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X59 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X60 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X61 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X62 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X63 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X64 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X65 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X66 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X67 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X68 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X69 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X70 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X71 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X72 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X73 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X74 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X75 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X76 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X77 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X78 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X79 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X80 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X81 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X82 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X83 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X84 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X85 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X86 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X87 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X88 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X89 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X90 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X91 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X92 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X93 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X94 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X95 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X96 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X97 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X98 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X99 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X100 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X101 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X102 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X103 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X104 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X105 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X106 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X107 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X108 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X109 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X110 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X111 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X112 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X113 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X114 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X115 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X116 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X117 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X118 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X119 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X120 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X121 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X122 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X123 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X124 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X125 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X126 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X127 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X128 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X129 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X130 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X131 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X132 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X133 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X134 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X135 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X136 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X137 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X138 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X139 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X140 vssd1 sky130_fd_sc_hd__inv_8_0/Y a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X141 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X142 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X143 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X144 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X145 latch_high_col row_selbuff a_n8997_49# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X146 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X147 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X148 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X149 a_n8998_299# row_selb latch_high_col vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X150 a_n8998_299# sky130_fd_sc_hd__inv_8_0/Y vccd1 vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X151 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X152 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X153 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X154 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X155 vccd1 sky130_fd_sc_hd__inv_8_0/Y a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X156 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X157 a_n8997_49# row_selbuff latch_high_col vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X158 latch_high_col row_selb a_n8998_299# vccd1 sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X159 a_n8997_49# sky130_fd_sc_hd__inv_8_0/Y vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +.ends + +.subckt x1T1R row WL col body +X0 row a_100_0# sky130_fd_pr__reram_reram_cell area_ox=1.6e+11p +X1 a_100_0# WL col body sky130_fd_pr__nfet_g5v0d10v5 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=500000u +.ends + +.subckt x1T1R_2x2 row0 row1 col0 WL0 col1 body WL1 +X1T1R_0 row1 WL1 col0 body x1T1R +X1T1R_1 row1 WL1 col1 body x1T1R +X1T1R_3 row0 WL0 col1 body x1T1R +X1T1R_2 row0 WL0 col0 body x1T1R +.ends + +.subckt x1T1R_16x16 row2 row3 row4 row5 row6 row8 row9 row13 row14 row15 col0 col1 ++ col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 WL5 ++ WL6 WL7 WL8 WL13 WL14 row11 row10 WL2 WL4 WL15 WL3 row7 WL0 WL11 WL10 WL9 row1 WL12 ++ row12 row0 body WL1 +X1T1R_2x2_0 row0 row1 col0 WL0 col1 body WL1 x1T1R_2x2 +X1T1R_2x2_1 row0 row1 col2 WL0 col3 body WL1 x1T1R_2x2 +X1T1R_2x2_2 row0 row1 col4 WL0 col5 body WL1 x1T1R_2x2 +X1T1R_2x2_3 row0 row1 col6 WL0 col7 body WL1 x1T1R_2x2 +X1T1R_2x2_4 row0 row1 col8 WL0 col9 body WL1 x1T1R_2x2 +X1T1R_2x2_5 row0 row1 col10 WL0 col11 body WL1 x1T1R_2x2 +X1T1R_2x2_6 row0 row1 col12 WL0 col13 body WL1 x1T1R_2x2 +X1T1R_2x2_7 row0 row1 col14 WL0 col15 body WL1 x1T1R_2x2 +X1T1R_2x2_8 row2 row3 col0 WL2 col1 body WL3 x1T1R_2x2 +X1T1R_2x2_9 row2 row3 col2 WL2 col3 body WL3 x1T1R_2x2 +X1T1R_2x2_60 row14 row15 col8 WL14 col9 body WL15 x1T1R_2x2 +X1T1R_2x2_62 row14 row15 col12 WL14 col13 body WL15 x1T1R_2x2 +X1T1R_2x2_61 row14 row15 col10 WL14 col11 body WL15 x1T1R_2x2 +X1T1R_2x2_51 row12 row13 col6 WL12 col7 body WL13 x1T1R_2x2 +X1T1R_2x2_50 row12 row13 col4 WL12 col5 body WL13 x1T1R_2x2 +X1T1R_2x2_40 row10 row11 col0 WL10 col1 body WL11 x1T1R_2x2 +X1T1R_2x2_63 row14 row15 col14 WL14 col15 body WL15 x1T1R_2x2 +X1T1R_2x2_52 row12 row13 col8 WL12 col9 body WL13 x1T1R_2x2 +X1T1R_2x2_41 row10 row11 col2 WL10 col3 body WL11 x1T1R_2x2 +X1T1R_2x2_30 row6 row7 col2 WL6 col3 body WL7 x1T1R_2x2 +X1T1R_2x2_53 row12 row13 col10 WL12 col11 body WL13 x1T1R_2x2 +X1T1R_2x2_42 row10 row11 col4 WL10 col5 body WL11 x1T1R_2x2 +X1T1R_2x2_31 row6 row7 col0 WL6 col1 body WL7 x1T1R_2x2 +X1T1R_2x2_20 row4 row5 col8 WL4 col9 body WL5 x1T1R_2x2 +X1T1R_2x2_54 row12 row13 col12 WL12 col13 body WL13 x1T1R_2x2 +X1T1R_2x2_43 row10 row11 col6 WL10 col7 body WL11 x1T1R_2x2 +X1T1R_2x2_32 row8 row9 col0 WL8 col1 body WL9 x1T1R_2x2 +X1T1R_2x2_21 row4 row5 col10 WL4 col11 body WL5 x1T1R_2x2 +X1T1R_2x2_10 row2 row3 col4 WL2 col5 body WL3 x1T1R_2x2 +X1T1R_2x2_55 row12 row13 col14 WL12 col15 body WL13 x1T1R_2x2 +X1T1R_2x2_44 row10 row11 col8 WL10 col9 body WL11 x1T1R_2x2 +X1T1R_2x2_33 row8 row9 col2 WL8 col3 body WL9 x1T1R_2x2 +X1T1R_2x2_22 row4 row5 col12 WL4 col13 body WL5 x1T1R_2x2 +X1T1R_2x2_11 row2 row3 col6 WL2 col7 body WL3 x1T1R_2x2 +X1T1R_2x2_56 row14 row15 col0 WL14 col1 body WL15 x1T1R_2x2 +X1T1R_2x2_45 row10 row11 col10 WL10 col11 body WL11 x1T1R_2x2 +X1T1R_2x2_34 row8 row9 col4 WL8 col5 body WL9 x1T1R_2x2 +X1T1R_2x2_23 row4 row5 col14 WL4 col15 body WL5 x1T1R_2x2 +X1T1R_2x2_12 row2 row3 col8 WL2 col9 body WL3 x1T1R_2x2 +X1T1R_2x2_57 row14 row15 col2 WL14 col3 body WL15 x1T1R_2x2 +X1T1R_2x2_46 row10 row11 col12 WL10 col13 body WL11 x1T1R_2x2 +X1T1R_2x2_35 row8 row9 col6 WL8 col7 body WL9 x1T1R_2x2 +X1T1R_2x2_24 row6 row7 col14 WL6 col15 body WL7 x1T1R_2x2 +X1T1R_2x2_13 row2 row3 col10 WL2 col11 body WL3 x1T1R_2x2 +X1T1R_2x2_58 row14 row15 col4 WL14 col5 body WL15 x1T1R_2x2 +X1T1R_2x2_47 row10 row11 col14 WL10 col15 body WL11 x1T1R_2x2 +X1T1R_2x2_36 row8 row9 col8 WL8 col9 body WL9 x1T1R_2x2 +X1T1R_2x2_25 row6 row7 col12 WL6 col13 body WL7 x1T1R_2x2 +X1T1R_2x2_14 row2 row3 col12 WL2 col13 body WL3 x1T1R_2x2 +X1T1R_2x2_59 row14 row15 col6 WL14 col7 body WL15 x1T1R_2x2 +X1T1R_2x2_48 row12 row13 col0 WL12 col1 body WL13 x1T1R_2x2 +X1T1R_2x2_49 row12 row13 col2 WL12 col3 body WL13 x1T1R_2x2 +X1T1R_2x2_38 row8 row9 col12 WL8 col13 body WL9 x1T1R_2x2 +X1T1R_2x2_37 row8 row9 col10 WL8 col11 body WL9 x1T1R_2x2 +X1T1R_2x2_26 row6 row7 col10 WL6 col11 body WL7 x1T1R_2x2 +X1T1R_2x2_27 row6 row7 col8 WL6 col9 body WL7 x1T1R_2x2 +X1T1R_2x2_16 row4 row5 col0 WL4 col1 body WL5 x1T1R_2x2 +X1T1R_2x2_15 row2 row3 col14 WL2 col15 body WL3 x1T1R_2x2 +X1T1R_2x2_39 row8 row9 col14 WL8 col15 body WL9 x1T1R_2x2 +X1T1R_2x2_28 row6 row7 col6 WL6 col7 body WL7 x1T1R_2x2 +X1T1R_2x2_17 row4 row5 col2 WL4 col3 body WL5 x1T1R_2x2 +X1T1R_2x2_29 row6 row7 col4 WL6 col5 body WL7 x1T1R_2x2 +X1T1R_2x2_18 row4 row5 col4 WL4 col5 body WL5 x1T1R_2x2 +X1T1R_2x2_19 row4 row5 col6 WL4 col7 body WL5 x1T1R_2x2 +.ends + +.subckt sky130_fd_sc_hd__inv_2 A VGND VPWR Y VNB VPB +X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.7e+11p pd=2.54e+06u as=5.2e+11p ps=5.04e+06u w=1e+06u l=150000u +X1 VGND A Y VNB sky130_fd_pr__nfet_01v8 ad=3.38e+11p pd=3.64e+06u as=1.755e+11p ps=1.84e+06u w=650000u l=150000u +X2 Y A VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X3 VPWR A Y VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +.ends + +.subckt sky130_fd_sc_hd__and2_4 A B VGND VPWR X VNB VPB +X0 VPWR B a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.185e+12p pd=1.037e+07u as=2.8e+11p ps=2.56e+06u w=1e+06u l=150000u +X1 a_27_47# A VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X2 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=3.64e+11p pd=3.72e+06u as=6.435e+11p ps=5.88e+06u w=650000u l=150000u +X3 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=5.6e+11p ps=5.12e+06u w=1e+06u l=150000u +X4 VGND B a_110_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.365e+11p ps=1.72e+06u w=650000u l=150000u +X5 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X6 a_110_47# A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.7225e+11p ps=1.83e+06u w=650000u l=150000u +X7 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X8 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X9 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X10 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X11 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +.ends + +.subckt and_pair SEL A B OUT_A OUT_B vssd1 vccd1 +X0 OUT_A a_n932_n2764# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4.8e+12p ps=3.36e+07u w=1e+06u l=150000u +X1 vccd1 A a_n932_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u +X2 a_n2012_n2764# B a_n2144_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u +X3 vccd1 a_n2012_n2764# OUT_B vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +X4 a_n2012_n2764# B vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=8e+11p pd=5.6e+06u as=0p ps=0u w=1e+06u l=150000u +X5 a_n2012_n2764# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X6 a_n932_n2764# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 vssd1 SEL a_n134_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=1.6e+12p pd=1.12e+07u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u +X8 vccd1 a_n932_n2764# OUT_A vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X9 vccd1 B a_n2012_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X10 a_n2144_n2764# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X11 a_n932_n2764# A vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X12 vccd1 SEL a_n2012_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X13 OUT_A a_n932_n2764# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u +X14 OUT_B a_n2012_n2764# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X15 vssd1 a_n2012_n2764# OUT_B vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +X16 vccd1 SEL a_n932_n2764# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X17 a_n134_n2764# A a_n932_n2764# vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +.ends + +.subckt col_driver_x50 Vcminus Vref Vcplus SWrefb SWref SWcminus SWcplus col VP VN +X0 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.26e+13p pd=8.12e+07u as=2.34e+13p ps=1.508e+08u w=1e+06u l=500000u +X1 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.26e+13p pd=8.12e+07u as=0p ps=0u w=1e+06u l=500000u +X2 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X3 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X4 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=6.3e+12p pd=4.06e+07u as=1.26e+13p ps=8.12e+07u w=1e+06u l=500000u +X5 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X6 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X7 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=6.3e+12p pd=4.06e+07u as=0p ps=0u w=1e+06u l=500000u +X8 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X9 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X10 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X11 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X12 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X13 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X14 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X15 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X16 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X17 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X18 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u 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col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X30 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X31 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X32 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X33 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X34 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X35 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X36 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X37 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X38 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X39 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X40 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X41 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X42 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X43 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X44 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X45 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X46 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X47 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X48 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X49 Vcminus SWcminus col VN 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sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X60 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X61 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X62 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X63 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X64 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X65 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X66 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X67 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X68 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X69 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p 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ps=0u w=1e+06u l=500000u +X80 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X81 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X82 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X83 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X84 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X85 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X86 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X87 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X88 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X89 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u 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col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X101 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X102 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X103 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X104 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X105 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X106 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X107 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X108 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X109 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X110 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X111 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X112 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X113 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X114 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X115 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X116 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X117 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X118 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X119 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X120 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X121 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X122 Vref SWref col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X123 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X124 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X125 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X126 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X127 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X128 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X129 col SWref Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X130 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X131 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X132 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X133 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X134 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X135 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X136 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X137 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X138 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X139 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X140 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X141 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X142 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X143 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X144 Vcminus SWcminus col VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X145 col SWcplus Vcplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X146 Vref SWrefb col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X147 col SWrefb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X148 col SWcminus Vcminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X149 Vcplus SWcplus col VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +.ends + +.subckt level_up_shifter_x4 in outb out vssd1 vccd1 vdda1 +X0 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=2.25e+12p pd=1.45e+07u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u +X1 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=1.8e+12p pd=1.16e+07u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u +X2 a_0_n3806# in vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=8e+11p pd=5.6e+06u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u +X3 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u +X4 out a_0_n3806# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.8e+12p pd=1.16e+07u as=0p ps=0u w=1e+06u l=500000u +X5 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.95e+12p ps=1.79e+07u w=1e+06u l=500000u +X6 outb a_0_n3806# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X7 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X8 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X9 out outb vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X10 outb out vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X11 vccd1 in a_0_n3806# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X12 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X13 vssd1 a_0_n3806# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X14 vdda1 a_0_n3806# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X15 out a_0_n3806# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X16 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X17 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X18 vccd1 in a_0_n3806# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X19 a_0_n3806# in vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +X20 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X21 outb a_0_n3806# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X22 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X23 vssd1 a_0_n3806# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X24 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X25 vdda1 a_0_n3806# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +.ends + +.subckt level_up_shifter_drivers_x4 B B_1.8 A_1.8 Ab_1.8 Bb_1.8 vccd1 vdda1 A vssd1 +Xlevel_up_shifter_x4_0 B Bb_1.8 B_1.8 vssd1 vccd1 vdda1 level_up_shifter_x4 +Xlevel_up_shifter_x4_1 A Ab_1.8 A_1.8 vssd1 vccd1 vdda1 level_up_shifter_x4 +.ends + +.subckt decoder2to4_x6 B Bb A Ab A1b A2 A0b A0 VP VN +X0 A2 a_n20_n174# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=7.18e+12p ps=4.636e+07u w=1e+06u l=500000u +X1 VN Ab a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u +X2 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=1.35e+12p pd=8.7e+06u as=1.394e+13p ps=8.988e+07u w=1e+06u l=500000u +X3 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u +X4 VN a_n20_n174# A2 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X5 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=3.15e+12p pd=2.03e+07u as=0p ps=0u w=1e+06u l=500000u +X6 a_n20_2180# Bb a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=1.34e+12p pd=8.68e+06u as=1.8e+12p ps=1.16e+07u w=1e+06u l=500000u +X7 a_100_n9284# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X8 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=2.7e+12p pd=1.74e+07u as=0p ps=0u w=1e+06u l=500000u +X9 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X10 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X11 a_100_n9284# Bb a_n20_2180# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X12 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=3.15e+12p ps=2.03e+07u w=1e+06u l=500000u +X13 A0b A0 VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=0p ps=0u w=1e+06u l=500000u +X14 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X15 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X16 VN a_n20_2180# A0 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u +X17 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X18 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X19 a_100_n2034# B A1b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=9e+11p ps=5.8e+06u w=1e+06u l=500000u +X20 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X21 a_n20_n174# Bb a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=1.34e+12p pd=8.68e+06u as=2.25e+12p ps=1.45e+07u w=1e+06u l=500000u +X22 a_n20_n174# Bb a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X23 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X24 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.8e+12p ps=1.16e+07u w=1e+06u l=500000u +X25 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X26 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X27 VN Ab a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X28 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X29 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X30 a_100_n2034# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X31 A1b B a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X32 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X33 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X34 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X35 a_n20_2180# Bb a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X36 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X37 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X38 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X39 A0b A0 VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X40 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X41 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X42 VN A0 A0b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X43 a_n20_2180# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X44 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X45 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X46 VN A a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X47 A0 a_n20_2180# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X48 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X49 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X50 VN Ab a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X51 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X52 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X53 a_100_n11182# A VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X54 VP a_n20_2180# A0 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X55 VN a_n20_2180# A0 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X56 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X57 a_100_n2034# B A1b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X58 a_100_n9284# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X59 VN A a_100_n11182# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X60 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X61 a_n20_n174# A VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X62 A1b B VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X63 A1b Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X64 a_n20_2180# Ab VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X65 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X66 VP Ab a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X67 a_100_n9284# Bb a_n20_2180# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X68 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X69 VP A0 A0b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X70 A0b A0 VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X71 VP a_n20_n174# A2 VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X72 VP Bb a_n20_2180# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X73 a_n20_n174# Bb VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X74 VN A0 A0b VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X75 A0 a_n20_2180# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X76 VN a_n20_n174# A2 VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X77 VP Bb a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X78 A0 a_n20_2180# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X79 A1b B a_100_n2034# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X80 VP B A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X81 a_100_n11182# Bb a_n20_n174# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X82 a_100_n11182# Bb a_n20_n174# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X83 VP A a_n20_n174# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X84 A2 a_n20_n174# VP VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X85 a_100_n2034# Ab VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X86 VN Ab a_100_n9284# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X87 a_100_n11182# A VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X88 A2 a_n20_n174# VN VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X89 VP Ab A1b VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +.ends + +.subckt col_driver_big Vcplus LA_B LA_A vccd1 Vref SEL col decoder2to4_x6_0/A2 decoder2to4_x6_0/A0 ++ decoder2to4_x6_0/A1b Vcminus vssd1 vdda1 +Xand_pair_0 SEL LA_A LA_B and_pair_0/OUT_A and_pair_0/OUT_B vssd1 vccd1 and_pair +Xcol_driver_x50_0 Vcminus Vref Vcplus decoder2to4_x6_0/A0b decoder2to4_x6_0/A0 decoder2to4_x6_0/A2 ++ decoder2to4_x6_0/A1b col vdda1 vssd1 col_driver_x50 +Xlevel_up_shifter_drivers_x4_0 and_pair_0/OUT_B decoder2to4_x6_0/B decoder2to4_x6_0/A ++ decoder2to4_x6_0/Ab decoder2to4_x6_0/Bb vccd1 vdda1 and_pair_0/OUT_A vssd1 level_up_shifter_drivers_x4 +Xdecoder2to4_x6_0 decoder2to4_x6_0/B decoder2to4_x6_0/Bb decoder2to4_x6_0/A decoder2to4_x6_0/Ab ++ decoder2to4_x6_0/A1b decoder2to4_x6_0/A2 decoder2to4_x6_0/A0b decoder2to4_x6_0/A0 ++ vdda1 vssd1 decoder2to4_x6 +.ends + +.subckt col_drivers_1x16 A0 A15 vdda1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 ++ B0 B1 B2 B3 B4 B5 B6 B8 B9 B10 B11 B12 B13 B14 B15 SEL col0 col2 col3 col1 col4 ++ col5 col6 col7 col8 col9 col10 col11 col12 col13 col14 col15 col_driver_big_14/decoder2to4_x6_0/A1b ++ col_driver_big_14/decoder2to4_x6_0/A2 col_driver_big_14/decoder2to4_x6_0/A0 Vcminus ++ Vcplus Vref B7 vccd1 vssd1 +Xcol_driver_big_0 Vcplus B0 A0 vccd1 Vref SEL col0 col_driver_big_0/decoder2to4_x6_0/A2 ++ col_driver_big_0/decoder2to4_x6_0/A0 col_driver_big_0/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_1 Vcplus B1 A1 vccd1 Vref SEL col1 col_driver_big_1/decoder2to4_x6_0/A2 ++ col_driver_big_1/decoder2to4_x6_0/A0 col_driver_big_1/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_2 Vcplus B3 A3 vccd1 Vref SEL col3 col_driver_big_2/decoder2to4_x6_0/A2 ++ col_driver_big_2/decoder2to4_x6_0/A0 col_driver_big_2/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_3 Vcplus B2 A2 vccd1 Vref SEL col2 col_driver_big_3/decoder2to4_x6_0/A2 ++ col_driver_big_3/decoder2to4_x6_0/A0 col_driver_big_3/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_4 Vcplus B5 A5 vccd1 Vref SEL col5 col_driver_big_4/decoder2to4_x6_0/A2 ++ col_driver_big_4/decoder2to4_x6_0/A0 col_driver_big_4/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_5 Vcplus B4 A4 vccd1 Vref SEL col4 col_driver_big_5/decoder2to4_x6_0/A2 ++ col_driver_big_5/decoder2to4_x6_0/A0 col_driver_big_5/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_6 Vcplus B7 A7 vccd1 Vref SEL col7 col_driver_big_6/decoder2to4_x6_0/A2 ++ col_driver_big_6/decoder2to4_x6_0/A0 col_driver_big_6/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_7 Vcplus B6 A6 vccd1 Vref SEL col6 col_driver_big_7/decoder2to4_x6_0/A2 ++ col_driver_big_7/decoder2to4_x6_0/A0 col_driver_big_7/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_10 Vcplus B11 A11 vccd1 Vref SEL col11 col_driver_big_10/decoder2to4_x6_0/A2 ++ col_driver_big_10/decoder2to4_x6_0/A0 col_driver_big_10/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_8 Vcplus B9 A9 vccd1 Vref SEL col9 col_driver_big_8/decoder2to4_x6_0/A2 ++ col_driver_big_8/decoder2to4_x6_0/A0 col_driver_big_8/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_9 Vcplus B8 A8 vccd1 Vref SEL col8 col_driver_big_9/decoder2to4_x6_0/A2 ++ col_driver_big_9/decoder2to4_x6_0/A0 col_driver_big_9/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_11 Vcplus B10 A10 vccd1 Vref SEL col10 col_driver_big_11/decoder2to4_x6_0/A2 ++ col_driver_big_11/decoder2to4_x6_0/A0 col_driver_big_11/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_12 Vcplus B13 A13 vccd1 Vref SEL col13 col_driver_big_12/decoder2to4_x6_0/A2 ++ col_driver_big_12/decoder2to4_x6_0/A0 col_driver_big_12/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_13 Vcplus B12 A12 vccd1 Vref SEL col12 col_driver_big_13/decoder2to4_x6_0/A2 ++ col_driver_big_13/decoder2to4_x6_0/A0 col_driver_big_13/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_14 Vcplus B15 A15 vccd1 Vref SEL col15 col_driver_big_14/decoder2to4_x6_0/A2 ++ col_driver_big_14/decoder2to4_x6_0/A0 col_driver_big_14/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +Xcol_driver_big_15 Vcplus B14 A14 vccd1 Vref SEL col14 col_driver_big_15/decoder2to4_x6_0/A2 ++ col_driver_big_15/decoder2to4_x6_0/A0 col_driver_big_15/decoder2to4_x6_0/A1b Vcminus ++ vssd1 vdda1 col_driver_big +.ends + +.subckt and_level_up_shifter_x4 SEL vdda1 outb out in vssd1 vccd1 +Xlevel_up_shifter_x4_0 level_up_shifter_x4_0/in outb out vssd1 vccd1 vdda1 level_up_shifter_x4 +X0 vccd1 SEL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=2.40003e+12p pd=1.6805e+07u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u +X1 level_up_shifter_x4_0/in a_n2010_n2765# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=1.2e+12p ps=8.4e+06u w=1e+06u l=150000u +X2 a_n2010_n2765# in a_n2142_n2765# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u +X3 a_n2010_n2765# in vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X4 level_up_shifter_x4_0/in a_n2010_n2765# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u +X5 a_n2142_n2765# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X6 a_n2010_n2765# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 vccd1 a_n2010_n2765# level_up_shifter_x4_0/in vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X8 vccd1 in a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +.ends + +.subckt level_up_shifter_2x outb in out vssd1 vccd1 vdda1 +X0 out a_195_n2770# vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u +X1 vssd1 a_195_n2770# out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X2 outb in vssd1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=9e+11p pd=5.8e+06u as=0p ps=0u w=1e+06u l=500000u +X3 outb a_195_n2770# vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=2.05e+12p ps=1.21e+07u w=1e+06u l=500000u +X4 vdda1 a_195_n2770# outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X5 out in vdda1 vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X6 a_195_n2770# in vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +X7 vdda1 in out vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X8 outb out vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=4.5e+11p pd=2.9e+06u as=1.35e+12p ps=8.7e+06u w=1e+06u l=500000u +X9 vdda1 out outb vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X10 out outb vdda1 vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=4.5e+11p pd=2.9e+06u as=0p ps=0u w=1e+06u l=500000u +X11 vdda1 outb out vdda1 sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X12 vccd1 in a_195_n2770# vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1e+06u l=150000u +X13 vssd1 in outb vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +.ends + +.subckt WL_driver SEL WL WL_out vdda1 vssd1 vccd1 +Xlevel_up_shifter_2x_0 level_up_shifter_2x_0/outb level_up_shifter_2x_0/in WL_out ++ vssd1 vccd1 vdda1 level_up_shifter_2x +X0 vccd1 SEL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=4.00025e+11p pd=2.805e+06u as=8e+11p ps=5.6e+06u w=1e+06u l=150000u +X1 level_up_shifter_2x_0/in a_n2010_n2765# vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=1.2e+12p ps=8.4e+06u w=1e+06u l=150000u +X2 a_n2010_n2765# WL a_n2142_n2765# vssd1 sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=5.1e+11p ps=3.02e+06u w=1e+06u l=150000u +X3 a_n2010_n2765# WL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X4 level_up_shifter_2x_0/in a_n2010_n2765# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=0p ps=0u w=1e+06u l=150000u +X5 a_n2142_n2765# SEL vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X6 a_n2010_n2765# SEL vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X7 vccd1 a_n2010_n2765# level_up_shifter_2x_0/in vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X8 vccd1 WL a_n2010_n2765# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +.ends + +.subckt WL_drivers_16x1 SEL vccd1 vdda1 WL15 WL14 WL13 WL12 WL11 WL10 WL9 WL8 WL7 ++ WL6 WL5 WL4 WL3 WL2 WL1 WL0 WL_out15 WL_out14 WL_out13 WL_out12 WL_out11 WL_out10 ++ WL_out9 WL_out8 WL_out7 WL_out6 WL_out5 WL_out4 WL_out3 WL_out2 WL_out1 WL_out0 ++ vssd1 +XWL_driver_0[0] SEL WL15 WL_out15 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[1] SEL WL14 WL_out14 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[2] SEL WL13 WL_out13 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[3] SEL WL12 WL_out12 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[4] SEL WL11 WL_out11 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[5] SEL WL10 WL_out10 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[6] SEL WL9 WL_out9 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[7] SEL WL8 WL_out8 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[8] SEL WL7 WL_out7 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[9] SEL WL6 WL_out6 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[10] SEL WL5 WL_out5 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[11] SEL WL4 WL_out4 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[12] SEL WL3 WL_out3 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[13] SEL WL2 WL_out2 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[14] SEL WL1 WL_out1 vdda1 vssd1 vccd1 WL_driver +XWL_driver_0[15] SEL WL0 WL_out0 vdda1 vssd1 vccd1 WL_driver +.ends + +.subckt row_driver_x30 SWref SWrminus row vgpr Vrplus Vsample SAMPLEb SAMPLE WR Vref ++ WRb SWrefb SWrplus Vgnr Vrminus VP VN +X0 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=7.65e+12p pd=4.93e+07u as=3.6e+12p ps=2.32e+07u w=1e+06u l=500000u +X1 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=7.2e+12p pd=4.64e+07u as=1.485e+13p ps=9.57e+07u w=1e+06u l=500000u +X2 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=2.7e+12p pd=1.74e+07u as=8.1e+12p ps=5.22e+07u w=1e+06u l=500000u +X3 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X4 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X5 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=5.38e+12p pd=3.476e+07u as=1.755e+13p ps=1.131e+08u w=1e+06u l=500000u +X6 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X7 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X8 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=1.301e+13p ps=8.402e+07u w=1e+06u l=500000u +X9 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=5.38e+12p pd=3.476e+07u as=0p ps=0u w=1e+06u l=500000u +X10 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X11 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X12 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X13 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X14 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X15 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X16 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X17 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X18 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X19 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X20 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X21 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X22 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X23 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=6.3e+12p ps=4.06e+07u w=1e+06u l=500000u +X24 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X25 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X26 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X27 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X28 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X29 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X30 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X31 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X32 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X33 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X34 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X35 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X36 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X37 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X38 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X39 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X40 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X41 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X42 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X43 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X44 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X45 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X46 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X47 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X48 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X49 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X50 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X51 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X52 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X53 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X54 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X55 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X56 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X57 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X58 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X59 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X60 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X61 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X62 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X63 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X64 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X65 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X66 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X67 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X68 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X69 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X70 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X71 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X72 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X73 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X74 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X75 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X76 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X77 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X78 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X79 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X80 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X81 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X82 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X83 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X84 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X85 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X86 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X87 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X88 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X89 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X90 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X91 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X92 row SWref a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X93 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X94 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X95 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X96 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X97 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X98 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X99 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X100 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X101 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X102 a_19432_n4118# SWref row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X103 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X104 row SWrminus a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X105 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X106 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X107 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X108 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=2.7e+12p pd=1.74e+07u as=0p ps=0u w=1e+06u l=500000u +X109 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X110 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X111 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X112 a_13042_n4118# SWrminus row VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X113 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X114 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X115 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X116 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X117 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X118 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X119 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X120 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X121 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X122 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X123 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X124 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X125 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X126 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X127 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X128 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X129 a_19432_n4118# SAMPLEb Vsample VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X130 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X131 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X132 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X133 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X134 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X135 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X136 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X137 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X138 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X139 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X140 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X141 Vsample SAMPLEb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X142 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X143 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X144 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X145 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X146 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X147 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X148 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X149 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X150 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X151 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X152 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X153 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X154 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X155 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X156 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X157 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X158 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X159 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X160 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X161 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X162 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X163 a_19432_n4118# WRb Vref VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X164 row SWrplus a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X165 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X166 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X167 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X168 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X169 Vsample SAMPLE a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X170 Vref WR a_19432_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X171 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X172 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X173 a_19432_n4118# SAMPLE Vsample VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X174 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X175 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X176 row SWrefb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X177 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X178 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X179 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X180 Vref WRb a_19432_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X181 a_n178_n4118# SWrplus row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X182 Vrplus vgpr a_n178_n4118# VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X183 a_n178_n4118# vgpr Vrplus VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X184 Vrminus Vgnr a_13042_n4118# VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X185 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X186 a_13042_n4118# Vgnr Vrminus VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X187 a_19432_n4118# WR Vref VN sky130_fd_pr__nfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +X188 a_19432_n4118# SWrefb row VP sky130_fd_pr__pfet_g5v0d10v5 ad=0p pd=0u as=0p ps=0u w=1e+06u l=500000u +.ends + +.subckt row_driver_big vccd1 Vref WRb Vrminus Vgnr Vgpr LA_B LA_A SEL row SAMPLE Vrplus ++ SAMPLEb decoder2to4_x6_0/Bb decoder2to4_x6_0/A Vsample WR vssd1 vdda1 +Xrow_driver_x30_0 decoder2to4_x6_0/A0 decoder2to4_x6_0/A2 row Vgpr Vrplus Vsample ++ SAMPLEb SAMPLE WR Vref WRb decoder2to4_x6_0/A0b decoder2to4_x6_0/A1b Vgnr Vrminus ++ vdda1 vssd1 row_driver_x30 +Xand_pair_0 SEL LA_A LA_B and_pair_0/OUT_A and_pair_0/OUT_B vssd1 vccd1 and_pair +Xlevel_up_shifter_drivers_x4_0 and_pair_0/OUT_B decoder2to4_x6_0/B decoder2to4_x6_0/A ++ decoder2to4_x6_0/Ab decoder2to4_x6_0/Bb vccd1 vdda1 and_pair_0/OUT_A vssd1 level_up_shifter_drivers_x4 +Xdecoder2to4_x6_0 decoder2to4_x6_0/B decoder2to4_x6_0/Bb decoder2to4_x6_0/A decoder2to4_x6_0/Ab ++ decoder2to4_x6_0/A1b decoder2to4_x6_0/A2 decoder2to4_x6_0/A0b decoder2to4_x6_0/A0 ++ vdda1 vssd1 decoder2to4_x6 +.ends + +.subckt row_drivers_16x1 Vref WRb Vrminus A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 ++ A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 row0 row1 row2 ++ row3 row4 row15 row5 row6 row7 row8 row9 row10 row11 row12 row13 row14 SAMPLE SAMPLEb ++ WR Vgpr row_driver_big_15/decoder2to4_x6_0/Bb Vsample row_driver_big_15/decoder2to4_x6_0/A ++ SEL Vgnr vccd1 vssd1 Vrplus vdda1 +Xrow_driver_big_10 vccd1 Vref WRb Vrminus Vgnr Vgpr B10 A10 SEL row10 SAMPLE Vrplus ++ SAMPLEb row_driver_big_10/decoder2to4_x6_0/Bb row_driver_big_10/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_11 vccd1 Vref WRb Vrminus Vgnr Vgpr B11 A11 SEL row11 SAMPLE Vrplus ++ SAMPLEb row_driver_big_11/decoder2to4_x6_0/Bb row_driver_big_11/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_13 vccd1 Vref WRb Vrminus Vgnr Vgpr B13 A13 SEL row13 SAMPLE Vrplus ++ SAMPLEb row_driver_big_13/decoder2to4_x6_0/Bb row_driver_big_13/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_12 vccd1 Vref WRb Vrminus Vgnr Vgpr B12 A12 SEL row12 SAMPLE Vrplus ++ SAMPLEb row_driver_big_12/decoder2to4_x6_0/Bb row_driver_big_12/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_14 vccd1 Vref WRb Vrminus Vgnr Vgpr B14 A14 SEL row14 SAMPLE Vrplus ++ SAMPLEb row_driver_big_14/decoder2to4_x6_0/Bb row_driver_big_14/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_15 vccd1 Vref WRb Vrminus Vgnr Vgpr B15 A15 SEL row15 SAMPLE Vrplus ++ SAMPLEb row_driver_big_15/decoder2to4_x6_0/Bb row_driver_big_15/decoder2to4_x6_0/A ++ Vsample WR vssd1 vdda1 row_driver_big +Xrow_driver_big_0 vccd1 Vref WRb Vrminus Vgnr Vgpr B0 A0 SEL row0 SAMPLE Vrplus SAMPLEb ++ row_driver_big_0/decoder2to4_x6_0/Bb row_driver_big_0/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_2 vccd1 Vref WRb Vrminus Vgnr Vgpr B2 A2 SEL row2 SAMPLE Vrplus SAMPLEb ++ row_driver_big_2/decoder2to4_x6_0/Bb row_driver_big_2/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_1 vccd1 Vref WRb Vrminus Vgnr Vgpr B1 A1 SEL row1 SAMPLE Vrplus SAMPLEb ++ row_driver_big_1/decoder2to4_x6_0/Bb row_driver_big_1/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_3 vccd1 Vref WRb Vrminus Vgnr Vgpr B3 A3 SEL row3 SAMPLE Vrplus SAMPLEb ++ row_driver_big_3/decoder2to4_x6_0/Bb row_driver_big_3/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_4 vccd1 Vref WRb Vrminus Vgnr Vgpr B4 A4 SEL row4 SAMPLE Vrplus SAMPLEb ++ row_driver_big_4/decoder2to4_x6_0/Bb row_driver_big_4/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_5 vccd1 Vref WRb Vrminus Vgnr Vgpr B5 A5 SEL row5 SAMPLE Vrplus SAMPLEb ++ row_driver_big_5/decoder2to4_x6_0/Bb row_driver_big_5/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_6 vccd1 Vref WRb Vrminus Vgnr Vgpr B6 A6 SEL row6 SAMPLE Vrplus SAMPLEb ++ row_driver_big_6/decoder2to4_x6_0/Bb row_driver_big_6/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_7 vccd1 Vref WRb Vrminus Vgnr Vgpr B7 A7 SEL row7 SAMPLE Vrplus SAMPLEb ++ row_driver_big_7/decoder2to4_x6_0/Bb row_driver_big_7/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_8 vccd1 Vref WRb Vrminus Vgnr Vgpr B8 A8 SEL row8 SAMPLE Vrplus SAMPLEb ++ row_driver_big_8/decoder2to4_x6_0/Bb row_driver_big_8/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +Xrow_driver_big_9 vccd1 Vref WRb Vrminus Vgnr Vgpr B9 A9 SEL row9 SAMPLE Vrplus SAMPLEb ++ row_driver_big_9/decoder2to4_x6_0/Bb row_driver_big_9/decoder2to4_x6_0/A Vsample ++ WR vssd1 vdda1 row_driver_big +.ends + +.subckt sky130_fd_sc_hd__buf_4 A VGND VPWR X VNB VPB +X0 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=8e+11p pd=7.6e+06u as=5.4e+11p ps=5.08e+06u w=1e+06u l=150000u +X1 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X2 VPWR a_27_47# X VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X3 X a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u +X4 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=3.51e+11p pd=3.68e+06u as=5.2e+11p ps=5.5e+06u w=650000u l=150000u +X5 X a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X6 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X7 VGND a_27_47# X VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u +X8 VPWR A a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.6e+11p ps=2.52e+06u w=1e+06u l=150000u +X9 VGND A a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u +.ends + +.subckt sky130_fd_sc_hd__dfxtp_1 CLK D VGND VPWR Q VNB VPB +X0 Q a_1059_315# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.69e+11p pd=1.82e+06u as=7.492e+11p ps=8.11e+06u w=650000u l=150000u +X1 a_891_413# a_193_47# a_634_159# VNB sky130_fd_pr__nfet_01v8 ad=1.368e+11p pd=1.48e+06u as=1.978e+11p ps=1.99e+06u w=360000u l=150000u +X2 a_561_413# a_27_47# a_466_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.533e+11p pd=1.57e+06u as=1.365e+11p ps=1.49e+06u w=420000u l=150000u +X3 VPWR CLK a_27_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.02105e+12p pd=9.61e+06u as=1.664e+11p ps=1.8e+06u w=640000u l=150000u +X4 Q a_1059_315# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.6e+11p pd=2.52e+06u as=0p ps=0u w=1e+06u l=150000u +X5 a_381_47# D VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=1.155e+11p pd=1.39e+06u as=0p ps=0u w=420000u l=150000u +X6 VGND a_634_159# a_592_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.392e+11p ps=1.53e+06u w=420000u l=150000u +X7 VPWR a_891_413# a_1059_315# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=2.7e+11p ps=2.54e+06u w=1e+06u l=150000u +X8 a_466_413# a_193_47# a_381_47# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X9 VPWR a_634_159# a_561_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X10 a_634_159# a_466_413# VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=640000u l=150000u +X11 a_634_159# a_466_413# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=2.19e+11p pd=2.15e+06u as=0p ps=0u w=750000u l=150000u +X12 a_975_413# a_193_47# a_891_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=1.764e+11p pd=1.68e+06u as=1.134e+11p ps=1.38e+06u w=420000u l=150000u +X13 VGND a_1059_315# a_1017_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.32e+11p ps=1.49e+06u w=420000u l=150000u +X14 a_193_47# a_27_47# VGND VNB sky130_fd_pr__nfet_01v8 ad=1.092e+11p pd=1.36e+06u as=0p ps=0u w=420000u l=150000u +X15 a_891_413# a_27_47# a_634_159# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X16 a_592_47# a_193_47# a_466_413# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.242e+11p ps=1.41e+06u w=360000u l=150000u +X17 a_1017_47# a_27_47# a_891_413# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=360000u l=150000u +X18 VPWR a_1059_315# a_975_413# VPB sky130_fd_pr__pfet_01v8_hvt ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X19 a_466_413# a_27_47# a_381_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.626e+11p ps=1.66e+06u w=360000u l=150000u +X20 a_193_47# a_27_47# VPWR VPB sky130_fd_pr__pfet_01v8_hvt ad=1.664e+11p pd=1.8e+06u as=0p ps=0u w=640000u l=150000u +X21 VGND a_891_413# a_1059_315# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.69e+11p ps=1.82e+06u w=650000u l=150000u +X22 a_381_47# D VGND VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X23 VGND CLK a_27_47# VNB sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.092e+11p ps=1.36e+06u w=420000u l=150000u +.ends + +.subckt comparator inp inm phi1 phi1b latch_high high_buff vssd1 vccd1 +Xsky130_fd_sc_hd__buf_4_0 low vssd1 vccd1 low_buff vssd1 vccd1 sky130_fd_sc_hd__buf_4 +Xsky130_fd_sc_hd__buf_4_1 high vssd1 vccd1 high_buff vssd1 vccd1 sky130_fd_sc_hd__buf_4 +Xsky130_fd_sc_hd__dfxtp_1_0 phi1b low_buff vssd1 vccd1 latch_low vssd1 vccd1 sky130_fd_sc_hd__dfxtp_1 +Xsky130_fd_sc_hd__dfxtp_1_1 phi1b high_buff vssd1 vccd1 latch_high vssd1 vccd1 sky130_fd_sc_hd__dfxtp_1 +X0 FN phi1 vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=1.155e+11p pd=1.39e+06u as=3.997e+12p ps=3.863e+07u w=420000u l=150000u +X1 pfete FN low vccd1 sky130_fd_pr__pfet_01v8 ad=2.815e+11p pd=2.65e+06u as=2.95e+11p ps=2.59e+06u w=1e+06u l=150000u +X2 high FP pfetw vccd1 sky130_fd_pr__pfet_01v8 ad=2.95e+11p pd=2.59e+06u as=2.815e+11p ps=2.65e+06u w=1e+06u l=150000u +X3 FN inm tail vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.14e+12p pd=8.57e+06u as=2.28e+12p ps=1.714e+07u w=4e+06u l=500000u +X4 vccd1 high pfete vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X5 pfetw low vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X6 tail phi1 vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=1.197e+11p pd=1.41e+06u as=3.3007e+12p ps=3.505e+07u w=420000u l=150000u +X7 vssd1 phi1b high vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.197e+11p ps=1.41e+06u w=420000u l=150000u +X8 high low vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +X9 vccd1 phi1 FP vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=1.155e+11p ps=1.39e+06u w=420000u l=150000u +X10 FP inp tail vssd1 sky130_fd_pr__nfet_g5v0d10v5 ad=1.14e+12p pd=8.57e+06u as=0p ps=0u w=4e+06u l=500000u +X11 vssd1 phi1b low vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.197e+11p ps=1.41e+06u w=420000u l=150000u +X12 low high vssd1 vssd1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=150000u +.ends + +.subckt mimcap_stacked m3_n1944_n462# c1_n1752_n412# c2_n1752_n412# +X0 c2_n1752_n412# c1_n1752_n412# sky130_fd_pr__cap_mim_m3_2 l=5e+06u w=5e+06u +X1 c1_n1752_n412# m3_n1944_n462# sky130_fd_pr__cap_mim_m3_1 l=5e+06u w=5e+06u +.ends + +.subckt mimcap_stacked_57x50 vssd1 sig +Xmimcap_stacked_0[0|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[0|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[1|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[2|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[3|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[4|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[5|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[6|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[7|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[8|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[9|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[10|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[11|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[12|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[13|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[14|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[15|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[16|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[17|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[18|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[19|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[20|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[21|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[22|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[23|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[24|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[25|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[26|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[27|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[28|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[29|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[30|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[31|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[32|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[33|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[34|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[35|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[36|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[37|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[38|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[39|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[40|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[41|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[42|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[43|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[44|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[45|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[46|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[47|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[48|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[49|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[50|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[51|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[52|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_0[53|46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[49] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[50] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[51] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[52] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_1[53] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[49] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[50] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[51] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[52] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_2[53] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[49] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[50] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[51] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[52] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_3[53] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_4[49] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_5[49] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[0] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[1] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[2] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[3] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[4] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[5] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[6] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[7] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[8] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[9] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[10] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[11] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[12] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[13] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[14] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[15] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[16] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[17] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[18] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[19] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[20] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[21] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[22] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[23] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[24] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[25] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[26] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[27] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[28] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[29] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[30] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[31] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[32] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[33] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[34] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[35] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[36] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[37] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[38] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[39] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[40] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[41] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[42] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[43] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[44] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[45] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[46] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[47] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[48] vssd1 sig vssd1 mimcap_stacked +Xmimcap_stacked_6[49] vssd1 sig vssd1 mimcap_stacked +.ends + +.subckt core A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row_sel latch_high col_sel Vref Vrplus vssd1 Vgpr +Xcomp_out_sel_0 comparator_0/latch_high latch_high vccd1 row_sel vssd1 comp_out_sel +X1T1R_16x16_0 1T1R_16x16_0/row2 1T1R_16x16_0/row3 1T1R_16x16_0/row4 1T1R_16x16_0/row5 ++ 1T1R_16x16_0/row6 1T1R_16x16_0/row8 1T1R_16x16_0/row9 1T1R_16x16_0/row13 1T1R_16x16_0/row14 ++ 1T1R_16x16_0/row15 1T1R_16x16_0/col0 1T1R_16x16_0/col1 1T1R_16x16_0/col2 1T1R_16x16_0/col3 ++ 1T1R_16x16_0/col4 1T1R_16x16_0/col5 1T1R_16x16_0/col6 1T1R_16x16_0/col7 1T1R_16x16_0/col8 ++ 1T1R_16x16_0/col9 1T1R_16x16_0/col10 1T1R_16x16_0/col11 1T1R_16x16_0/col12 1T1R_16x16_0/col13 ++ 1T1R_16x16_0/col14 1T1R_16x16_0/col15 1T1R_16x16_0/WL5 1T1R_16x16_0/WL6 1T1R_16x16_0/WL7 ++ 1T1R_16x16_0/WL8 1T1R_16x16_0/WL13 1T1R_16x16_0/WL14 1T1R_16x16_0/row11 1T1R_16x16_0/row10 ++ 1T1R_16x16_0/WL2 1T1R_16x16_0/WL4 1T1R_16x16_0/WL15 1T1R_16x16_0/WL3 1T1R_16x16_0/row7 ++ 1T1R_16x16_0/WL0 1T1R_16x16_0/WL11 1T1R_16x16_0/WL10 1T1R_16x16_0/WL9 1T1R_16x16_0/row1 ++ 1T1R_16x16_0/WL12 1T1R_16x16_0/row12 1T1R_16x16_0/row0 vssd1 1T1R_16x16_0/WL1 x1T1R_16x16 +Xsky130_fd_sc_hd__inv_2_0 phi1b vssd1 vccd1 phi1 vssd1 vccd1 sky130_fd_sc_hd__inv_2 +Xsky130_fd_sc_hd__inv_2_1 RISC_CLK vssd1 vccd1 phi1b vssd1 vccd1 sky130_fd_sc_hd__inv_2 +Xsky130_fd_sc_hd__and2_4_0 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4 +Xcol_drivers_1x16_0 A0c A15c vdda1 A1c A2c A3c A4c A5c A6c A7c A8c A9c A10c A11c A12c ++ A13c A14c B0c B1c B2c B3c B4c B5c B6c B8c B9c B10c B11c B12c B13c B14c B15c SEL ++ 1T1R_16x16_0/col0 1T1R_16x16_0/col2 1T1R_16x16_0/col3 1T1R_16x16_0/col1 1T1R_16x16_0/col4 ++ 1T1R_16x16_0/col5 1T1R_16x16_0/col6 1T1R_16x16_0/col7 1T1R_16x16_0/col8 1T1R_16x16_0/col9 ++ 1T1R_16x16_0/col10 1T1R_16x16_0/col11 1T1R_16x16_0/col12 1T1R_16x16_0/col13 1T1R_16x16_0/col14 ++ 1T1R_16x16_0/col15 col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A1b col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A2 ++ col_drivers_1x16_0/col_driver_big_14/decoder2to4_x6_0/A0 Vcminus Vcplus Vref B7c ++ vccd1 vssd1 col_drivers_1x16 +Xsky130_fd_sc_hd__and2_4_1 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4 +Xsky130_fd_sc_hd__and2_4_2 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4 +Xand_level_up_shifter_x4_0 SEL vdda1 row_drivers_16x1_0/WRb row_drivers_16x1_0/WR ++ WR vssd1 vccd1 and_level_up_shifter_x4 +Xsky130_fd_sc_hd__and2_4_3 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4 +Xand_level_up_shifter_x4_1 SEL vdda1 row_drivers_16x1_0/SAMPLEb row_drivers_16x1_0/SAMPLE ++ SAMPLE vssd1 vccd1 and_level_up_shifter_x4 +Xsky130_fd_sc_hd__and2_4_4 row_sel col_sel vssd1 vccd1 SEL vssd1 vccd1 sky130_fd_sc_hd__and2_4 +XWL_drivers_16x1_0 SEL vccd1 vdda1 WL15 WL14 WL13 WL12 WL11 WL10 WL9 WL8 WL7 WL6 WL5 ++ WL4 WL3 WL2 WL1 WL0 1T1R_16x16_0/WL15 1T1R_16x16_0/WL14 1T1R_16x16_0/WL13 1T1R_16x16_0/WL12 ++ 1T1R_16x16_0/WL11 1T1R_16x16_0/WL10 1T1R_16x16_0/WL9 1T1R_16x16_0/WL8 1T1R_16x16_0/WL7 ++ 1T1R_16x16_0/WL6 1T1R_16x16_0/WL5 1T1R_16x16_0/WL4 1T1R_16x16_0/WL3 1T1R_16x16_0/WL2 ++ 1T1R_16x16_0/WL1 1T1R_16x16_0/WL0 vssd1 WL_drivers_16x1 +Xrow_drivers_16x1_0 Vref row_drivers_16x1_0/WRb Vrminus A0r A1r A2r A3r A4r A5r A6r ++ A7r A8r A9r A10r A11r A12r A13r A14r A15r B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r ++ B10r B11r B12r B13r B14r B15r 1T1R_16x16_0/row0 1T1R_16x16_0/row1 1T1R_16x16_0/row2 ++ 1T1R_16x16_0/row3 1T1R_16x16_0/row4 1T1R_16x16_0/row15 1T1R_16x16_0/row5 1T1R_16x16_0/row6 ++ 1T1R_16x16_0/row7 1T1R_16x16_0/row8 1T1R_16x16_0/row9 1T1R_16x16_0/row10 1T1R_16x16_0/row11 ++ 1T1R_16x16_0/row12 1T1R_16x16_0/row13 1T1R_16x16_0/row14 row_drivers_16x1_0/SAMPLE ++ row_drivers_16x1_0/SAMPLEb row_drivers_16x1_0/WR Vgpr row_drivers_16x1_0/row_driver_big_15/decoder2to4_x6_0/Bb ++ Vsample row_drivers_16x1_0/row_driver_big_15/decoder2to4_x6_0/A SEL Vgnr vccd1 vssd1 ++ Vrplus vdda1 row_drivers_16x1 +Xcomparator_0 Vsample Vref_comp phi1 phi1b comparator_0/latch_high comparator_0/high_buff ++ vssd1 vccd1 comparator +Xmimcap_stacked_57x50_0 vssd1 Vsample mimcap_stacked_57x50 +.ends + +.subckt core_7x6 B0c B2c B6c B7c B9c B10c B11c B12c B14c B15c A0c A1c A12c A14c RISC_CLK ++ SAMPLE A14r A15r Vrminus Vref_comp vdda1 WL5 WL6 WL8 col4_sel row1_sel row2_sel ++ row3_sel row4_sel row5_sel core_interconnect_bottom_left_4/m4_84804_n88270# core_interconnect_bottom_left_15/m4_84084_n88270# ++ core_interconnect_bottom_left_0/m4_84084_n88270# core_interconnect_bottom_left_15/m4_83364_n88270# ++ col2_sel core_interconnect_bottom_left_0/m4_83364_n88270# WR row6_sel core_interconnect_bottom_left_11/m4_84804_n88270# ++ A5c core_interconnect_bottom_left_7/m4_84084_n88270# core_interconnect_bottom_left_12/m4_84084_n88270# ++ core_interconnect_bottom_left_7/m4_83364_n88270# core_interconnect_bottom_left_12/m4_83364_n88270# ++ Vcminus col3_sel core_interconnect_bottom_left_8/m4_84804_n88270# core_interconnect_bottom_left_3/m4_84804_n88270# ++ A15c core_interconnect_bottom_left_4/m4_84084_n88270# A13c core_interconnect_bottom_left_4/m4_83364_n88270# ++ A8c latch_high0 row0_sel B3c A6c B1c A9c col0_sel A7c Vrplus latch_high1 core_interconnect_bottom_left_15/m4_84804_n88270# ++ latch_high2 core_interconnect_bottom_left_0/m4_84804_n88270# col5_sel A2c core_interconnect_bottom_left_11/m4_84084_n88270# ++ latch_high3 core_interconnect_bottom_left_11/m4_83364_n88270# latch_high5 B13r B5r ++ B8r A4c B0r WL1 latch_high4 core_interconnect_bottom_left_7/m4_84804_n88270# core_interconnect_bottom_left_12/m4_84804_n88270# ++ A11r B12r B9r B15r col1_sel A6r B7r B4c B4r WL11 A1r B2r A10r core_interconnect_bottom_left_8/m4_84084_n88270# ++ WL3 A10c Vgnr A5r core_interconnect_bottom_left_3/m4_84084_n88270# B5c A0r A13r ++ B3r Vcplus B11r Vgpr B13c core_interconnect_bottom_left_8/m4_83364_n88270# A8r WL15 ++ B14r WL2 B6r WL13 core_interconnect_bottom_left_3/m4_83364_n88270# A3r A9r WL10 ++ B1r A12r A3c WL14 A4r vccd1 WL12 A7r WL9 WL0 B10r Vref A2r vssd1 WL7 A11c B8c WL4 +Xcore_6 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row0_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_39 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_28 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_17 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_29 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_7 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row0_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_18 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_8 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_19 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_9 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_40 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_41 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_30 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_31 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_20 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_32 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_10 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row0_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_21 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_0 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row0_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_33 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_11 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row0_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_22 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_1 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row0_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_34 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_12 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_23 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high5 col5_sel Vref Vrplus vssd1 Vgpr core +Xcore_2 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_35 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high4 col4_sel Vref Vrplus vssd1 Vgpr core +Xcore_13 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_24 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row4_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_3 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_36 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_25 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high0 col0_sel Vref Vrplus vssd1 Vgpr core +Xcore_14 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_4 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high3 col3_sel Vref Vrplus vssd1 Vgpr core +Xcore_37 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_26 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_15 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row3_sel latch_high1 col1_sel Vref Vrplus vssd1 Vgpr core +Xcore_38 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row6_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_27 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row5_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_5 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c A11c ++ A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c B14c ++ B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r B14r ++ B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r WL0 WL1 ++ WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c B4c RISC_CLK ++ Vref_comp row1_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +Xcore_16 A0c A15c vccd1 vdda1 Vcplus Vcminus A1c A2c A3c A4c A5c A6c A8c A9c A10c ++ A11c A12c A13c A14c B0c B1c B2c B3c Vgnr B5c B6c B7c B8c B9c B10c B11c B12c B13c ++ B14c B15c Vrminus WR B0r B1r B2r B3r B4r B5r B6r B7r B8r B9r B10r B11r B12r B13r ++ B14r B15r A0r A1r A2r A3r A4r A5r A6r A7r A8r A9r A10r A11r A12r A13r A14r A15r ++ WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 SAMPLE A7c ++ B4c RISC_CLK Vref_comp row2_sel latch_high2 col2_sel Vref Vrplus vssd1 Vgpr core +.ends + +.subckt top Vgnr Vrminus vccd1 vdda1 RSEL2 RSEL1 RSEL0 cA0 cA1 cA2 cA3 cA4 cA5 cA6 ++ cA7 cA8 cA9 cA10 cA11 cA12 cA13 cA14 cA15 cB0 cB1 cB2 cB3 cB4 cB5 cB6 cB7 cB8 cB9 ++ cB10 cB11 cB12 cB13 cB14 cB15 rA0 rA1 rA2 rA3 rA4 rA5 rA6 rA7 rA8 rA9 rA10 rA11 ++ rA12 rA13 rA14 rA15 rB0 rB1 rB2 rB3 rB4 rB5 rB6 rB7 rB8 rB9 rB10 rB11 rB12 rB13 ++ rB14 rB15 WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 WL8 WL9 WL10 WL11 WL12 WL13 WL14 WL15 ++ WR SAMPLE RISC_CLK CSEL2 CSEL1 CSEL0 Vref_comp EN latch_high4 latch_high0 latch_high1 ++ latch_high2 latch_high3 latch_high5 Vrplus Vgpr Vref Vcplus Vcminus vssa1 +Xtop_interconnect_0 WL4 core_7x6_0/col5_sel cA2 latch_high5 core_7x6_0/row6_sel WL3 ++ latch_high4 cA3 vccd1 WL2 cA4 latch_high3 vssa1 core_7x6_0/col2_sel rB0 Vref WL1 ++ vssa1 cA5 latch_high2 core_7x6_0/row3_sel rB1 WL0 cA6 latch_high1 WR SAMPLE rB2 ++ cA7 latch_high0 rB3 cA8 cA10 vssa1 core_7x6_0/row0_sel rB4 cA9 cA11 rB5 vdda1 cA12 ++ rB6 cA13 rB7 cA14 vccd1 Vrplus vdda1 rB8 Vcminus cA15 rB9 Vref RISC_CLK vdda1 core_7x6_0/col3_sel ++ core_7x6_0/row4_sel rB10 RSEL1 rB11 RSEL0 core_7x6_0/col0_sel vssa1 rB12 core_7x6_0/row1_sel ++ cB0 rB13 vccd1 cB1 Vref rB14 rA0 RSEL2 cB2 rB15 rA1 cB3 Vref_comp vccd1 rA2 vdda1 ++ cB4 Vref rA3 vccd1 cB5 rA4 vssa1 vssa1 CSEL1 cB6 vssa1 rA5 vccd1 cB7 CSEL0 core_7x6_0/col4_sel ++ WL15 rA6 Vcplus core_7x6_0/row5_sel cB8 WL14 rA7 Vgnr EN cB9 WL13 rA10 rA8 vdda1 ++ core_7x6_0/col1_sel WL12 rA11 rA9 Vgpr Vref vssa1 core_7x6_0/row2_sel WL11 rA12 ++ cB10 WL10 rA13 Vref vdda1 vssa1 WL9 rA14 cB11 vccd1 vdda1 vssa1 WL8 cB12 rA15 vdda1 ++ vccd1 Vref Vref vccd1 WL7 cB13 Vrminus WL6 cB14 cA0 CSEL2 WL5 cB15 cA1 vssa1 vdda1 ++ vdda1 Vref top_interconnect +Xcore_7x6_0 cB0 cB2 cB6 cB7 cB9 cB10 cB11 cB12 cB14 cB15 cA0 cA1 cA12 cA14 RISC_CLK ++ SAMPLE rA14 rA15 Vrminus Vref_comp vdda1 WL5 WL6 WL8 core_7x6_0/col4_sel core_7x6_0/row1_sel ++ core_7x6_0/row2_sel core_7x6_0/row3_sel core_7x6_0/row4_sel core_7x6_0/row5_sel ++ vdda1 Vref Vref vccd1 core_7x6_0/col2_sel vccd1 WR core_7x6_0/row6_sel vdda1 cA5 ++ Vref Vref vccd1 vccd1 Vcminus core_7x6_0/col3_sel vdda1 vdda1 cA15 Vref cA13 vccd1 ++ cA8 latch_high0 core_7x6_0/row0_sel cB3 cA6 cB1 cA9 core_7x6_0/col0_sel cA7 Vrplus ++ latch_high1 vdda1 latch_high2 vdda1 core_7x6_0/col5_sel cA2 Vref latch_high3 vccd1 ++ latch_high5 rB13 rB5 rB8 cA4 rB0 WL1 latch_high4 vdda1 vdda1 rA11 rB12 rB9 rB15 ++ core_7x6_0/col1_sel rA6 rB7 cB4 rB4 WL11 rA1 rB2 rA10 Vref WL3 cA10 Vgnr rA5 Vref ++ cB5 rA0 rA13 rB3 Vcplus rB11 Vgpr cB13 vccd1 rA8 WL15 rB14 WL2 rB6 WL13 vccd1 rA3 ++ rA9 WL10 rB1 rA12 cA3 WL14 rA4 vccd1 WL12 rA7 WL9 WL0 rB10 Vref rA2 vssa1 WL7 cA11 ++ cB8 WL4 core_7x6 +.ends + +.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11] ++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16] ++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5] ++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10] ++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16] ++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5] ++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10] ++ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4] ++ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0] ++ io_clamp_low[1] io_clamp_low[2] vssa1 io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] ++ io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] ++ io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] ++ io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14] ++ io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1] ++ io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25] ++ io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] ++ io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13] ++ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20] ++ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3] ++ io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10] ++ io_out[11] io_out[12] io_out[13] io_out[14] io_out[15] io_out[16] io_out[17] io_out[18] ++ io_out[19] io_out[1] io_out[20] io_out[21] io_out[22] io_out[23] io_out[24] io_out[25] ++ io_out[26] io_out[2] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] ++ io_out[9] la_data_in[0] la_data_in[100] la_data_in[101] la_data_in[102] la_data_in[103] ++ la_data_in[104] la_data_in[105] la_data_in[106] la_data_in[107] la_data_in[108] ++ la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111] la_data_in[112] la_data_in[113] ++ la_data_in[114] la_data_in[115] la_data_in[116] la_data_in[117] la_data_in[118] ++ la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121] la_data_in[122] la_data_in[123] ++ la_data_in[124] la_data_in[125] la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] ++ la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] ++ la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] ++ la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] ++ la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] ++ la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] ++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] ++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] ++ la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] ++ la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] ++ la_data_in[63] la_data_in[64] la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] ++ la_data_in[69] la_data_in[6] la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] ++ la_data_in[74] la_data_in[75] la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] ++ la_data_in[7] la_data_in[80] la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] ++ la_data_in[85] la_data_in[86] la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] ++ la_data_in[90] la_data_in[91] la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] ++ la_data_in[96] la_data_in[97] la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] ++ la_data_out[100] la_data_out[101] la_data_out[102] la_data_out[103] la_data_out[104] ++ la_data_out[105] la_data_out[106] la_data_out[107] la_data_out[108] la_data_out[109] ++ la_data_out[10] la_data_out[110] la_data_out[111] la_data_out[112] la_data_out[113] ++ la_data_out[114] la_data_out[115] la_data_out[116] la_data_out[117] la_data_out[118] ++ la_data_out[119] la_data_out[11] la_data_out[120] la_data_out[121] la_data_out[122] ++ la_data_out[123] la_data_out[124] la_data_out[125] la_data_out[126] la_data_out[127] ++ la_data_out[12] la_data_out[13] la_data_out[14] la_data_out[15] la_data_out[16] ++ la_data_out[17] la_data_out[18] la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] ++ la_data_out[22] la_data_out[23] la_data_out[24] la_data_out[25] la_data_out[26] ++ la_data_out[27] la_data_out[28] la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] ++ la_data_out[32] la_data_out[33] la_data_out[34] la_data_out[35] la_data_out[36] ++ la_data_out[37] la_data_out[38] la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] ++ la_data_out[42] la_data_out[43] la_data_out[44] la_data_out[45] la_data_out[46] ++ la_data_out[47] la_data_out[48] la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] ++ la_data_out[52] la_data_out[53] la_data_out[54] la_data_out[55] la_data_out[56] ++ la_data_out[57] la_data_out[58] la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] ++ la_data_out[62] la_data_out[63] la_data_out[64] la_data_out[65] la_data_out[66] ++ la_data_out[67] la_data_out[68] la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] ++ la_data_out[72] la_data_out[73] la_data_out[74] la_data_out[75] la_data_out[76] ++ la_data_out[77] la_data_out[78] la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] ++ la_data_out[82] la_data_out[83] la_data_out[84] la_data_out[85] la_data_out[86] ++ la_data_out[87] la_data_out[88] la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] ++ la_data_out[92] la_data_out[93] la_data_out[94] la_data_out[95] la_data_out[96] ++ la_data_out[97] la_data_out[98] la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100] ++ la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] ++ la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] ++ la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] ++ la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] ++ la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] ++ la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] ++ la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] ++ la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] ++ la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] ++ la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] ++ la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] ++ la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] ++ la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] ++ la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] ++ la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] ++ la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] ++ la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] ++ la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] ++ user_clock2 user_irq[0] user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssd1 vssd2 vssa2 ++ wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] ++ wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] ++ wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] ++ wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] ++ wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] ++ wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] ++ wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] ++ wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] ++ wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] ++ wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] ++ wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] ++ wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] ++ wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] ++ wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] ++ wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] ++ wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] ++ wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i +Xtop_0 gpio_analog[2] gpio_noesd[3] vccd1 io_clamp_high[2] la_data_in[118] la_data_in[119] ++ la_data_in[120] la_data_in[0] la_data_in[1] la_data_in[2] la_data_in[3] la_data_in[4] ++ la_data_in[5] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9] la_data_in[10] ++ la_data_in[11] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16] ++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[20] la_data_in[21] la_data_in[22] ++ la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] ++ la_data_in[29] la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34] ++ la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[40] ++ la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] ++ la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[50] la_data_in[51] la_data_in[52] ++ la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] ++ la_data_in[59] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] ++ la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[70] ++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76] ++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[80] la_data_in[81] la_data_in[82] ++ la_data_in[103] la_data_in[104] la_data_in[105] gpio_analog[17] la_data_in[112] ++ la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98] ++ la_data_out[97] gpio_noesd[6] gpio_analog[16] gpio_noesd[0] io_analog[4] gpio_noesd[5] ++ vssa1 top +.ends +
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym index a561ba9..5ccbd59 100644 --- a/xschem/user_analog_project_wrapper.sym +++ b/xschem/user_analog_project_wrapper.sym
@@ -1,4 +1,4 @@ -v {xschem version=2.9.9 file_version=1.2 } +v {xschem version=3.0.0 file_version=1.2 } G {} K {type=subcircuit format="@name @pinlist @symname" @@ -61,7 +61,7 @@ B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in } B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out } B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out } -B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in } +B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[0:127] dir=in } B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out } B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in } B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in } @@ -95,7 +95,7 @@ T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {} T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {} T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {} -T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {} +T {la_data_in[0:127]} -125 -24 0 0 0.2 0.2 {} T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {} T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {} T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}